diff --git a/ODIN_II/exec_wrapper.sh b/ODIN_II/exec_wrapper.sh index 711f9f084d6..20c20564e06 100755 --- a/ODIN_II/exec_wrapper.sh +++ b/ODIN_II/exec_wrapper.sh @@ -23,6 +23,8 @@ PERF_EXEC="perf stat record -a -d -d -d -o" GDB_EXEC="gdb --args" EXEC_PREFIX="" +TOOL_LIST="" + TEST_NAME="N/A" LOG="" LOG_FILE="" @@ -98,6 +100,7 @@ Usage: ./exec_wrapper.sh [options] --time_limit * stops Odin after X seconds --limit_ressource * limit ressource usage using ulimit -m (25% of hrdw memory) and nice value of 19 --verbosity [0, 1, 2] * [0] no output, [1] output on error, [2] output the log to stdout + --no_color * force no color on output " } @@ -213,6 +216,12 @@ then _exit_with_code "-1" fi +if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] +then + COLORIZE_OUTPUT="on" + log_it "Using colorized output\n" +fi + while [[ "$#" > 0 ]] do case $1 in @@ -242,6 +251,10 @@ do RESTRICT_RESSOURCE="on" ;; + --no_color) + COLORIZE_OUTPUT="off" + ;; + --verbosity) case "_$2" in _0) VERBOSE="0";; @@ -267,14 +280,17 @@ do else case $2 in valgrind) + TOOL_LIST="valgrind ${TOOL_LIST}" EXEC_PREFIX="${VALGRIND_EXEC} ${EXEC_PREFIX}" ;; gdb) + TOOL_LIST="gdb ${TOOL_LIST}" USE_TIMEOUT="off" USE_LOGS="off" EXEC_PREFIX="${GDB_EXEC} ${EXEC_PREFIX}" ;; perf) + TOOL_LIST="perf ${TOOL_LIST}" EXEC_PREFIX="${PERF_EXEC} ${EXEC_PREFIX}" shift ;; @@ -302,13 +318,6 @@ then restrict_ressource fi - -if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] -then - COLORIZE_OUTPUT="on" - log_it "Using colorized output\n" -fi - if [ "${USE_LOGS}" == "on" ] then if [ "_${LOG_FILE}" == "_" ] @@ -331,12 +340,14 @@ fi if [ "${USE_TIME}" == "on" ] then + TOOL_LIST="time ${TOOL_LIST}" EXEC_PREFIX="${TIME_EXEC} --output=${LOG_FILE} --append ${EXEC_PREFIX}" log_it "running with /bin/time\n" fi if [ "${USE_TIMEOUT}" == "on" ] then + TOOL_LIST="timeout ${TOOL_LIST}" EXEC_PREFIX="timeout ${TIME_LIMIT} ${EXEC_PREFIX}" log_it "running with timeout ${TIME_LIMIT}\n" fi @@ -352,23 +363,52 @@ then log_it "Must define a path to a valid argument file" dump_log else - _ARGS=$(cat ${ARG_FILE}) - if [ "${USE_LOGS}" == "on" ] + failed_requirements="" + # test all necessary tool + for tool_used in ${TOOL_LIST} + do + which ${tool_used} &> /dev/null + if [ "$?" != "0" ]; + then + failed_requirements="${tool_used} ${failed_requirements}" + fi + done + + if [ "_${failed_requirements}" != "_" ]; then - if [ "${VERBOSE}" == "2" ] + if [ "${USE_LOGS}" == "on" ] then - ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + if [ "${VERBOSE}" == "2" ] + then + echo "missing \"${failed_requirements}\"" | tee ${LOG_FILE} + else + echo "missing \"${failed_requirements}\"" &>> ${LOG_FILE} + fi else - ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + echo "missing \"${failed_requirements}\"" fi + + EXIT_CODE="-1" + pretty_print_status "Missing package: ${failed_requirements}" + else - ${EXEC_PREFIX} ${_ARGS} + _ARGS=$(cat ${ARG_FILE}) + if [ "${USE_LOGS}" == "on" ] + then + if [ "${VERBOSE}" == "2" ] + then + ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + else + ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + fi + else + ${EXEC_PREFIX} ${_ARGS} + fi + EXIT_CODE=$? + display "${EXIT_CODE}" fi - EXIT_CODE=$? fi -display "${EXIT_CODE}" - EXIT_STATUS=0 if [ "${EXIT_CODE}" != "0" ] then diff --git a/ODIN_II/regression_test/.library/output_on_error.conf b/ODIN_II/regression_test/.library/output_on_error.conf index 7db9a08a2f6..c13223adb16 100644 --- a/ODIN_II/regression_test/.library/output_on_error.conf +++ b/ODIN_II/regression_test/.library/output_on_error.conf @@ -1,2 +1,2 @@ -script_synthesis_params=--verbosity 1 -script_simulation_params=--verbosity 1 \ No newline at end of file +script_synthesis_params=--verbosity 1 --no_color +script_simulation_params=--verbosity 1 --no_color \ No newline at end of file diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh index 1f1ad028cbc..ec61de0cf03 100755 --- a/ODIN_II/verify_odin.sh +++ b/ODIN_II/verify_odin.sh @@ -23,7 +23,17 @@ ODIN_EXEC="${THIS_DIR}/odin_II" BENCHMARK_DIR="${REGRESSION_DIR}/benchmark" -TEST_DIR_LIST=$(ls -d ${BENCHMARK_DIR}/*/ | sed "s/\/$//g" | xargs -n1 -I TEST_FILE /bin/bash -c 'printf "$(basename TEST_FILE) "') + +VTR_REG_DIR="${THIS_DIR}/../vtr_flow/tasks/regression_tests" +VTR_REG_LIST=$(ls ${VTR_REG_DIR} | grep "vtr_reg") + +SUITE_DIR="${BENCHMARK_DIR}/suite" +SUITE_LIST=$(ls ${SUITE_DIR}) + +TASK_DIR="${BENCHMARK_DIR}/task" +TASK_LIST=$(ls ${TASK_DIR}) + +PREVIOUS_RUN_DIR="" NEW_RUN_DIR="${REGRESSION_DIR}/run001/" ############################################## @@ -63,12 +73,14 @@ _prt_cur_arg() { ############## # defaults _TEST="" +_TEST_NAME="" +_SUBTEST_LIST="" _NUMBER_OF_PROCESS="1" _SIM_COUNT="1" _RUN_DIR_OVERRIDE="" +_EXTRA_CONFIG="" -_CONFIG_OVERRIDE="" - +_OVERRIDE_CONFIG="off" _GENERATE_BENCH="off" _GENERATE_OUTPUT="off" _GENERATE_CONFIG="off" @@ -78,22 +90,41 @@ function help() { printf "Called program with $INPUT Usage: - $0 [ OPTIONS / FLAGS ] + $0 [ OPTIONS / FLAGS ] [ SUBTEST_LIST ... ] + SUBTEST_LIST + should be a list of the form < task_name/test_file_name/architecture_file_name > + passing this in will limit a task to a subset of test + current: $(_prt_cur_arg ${_SUBTEST_LIST}) - OPTIONS: - -h|--help $(_prt_cur_arg off) print this - -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is one of ( ${TEST_DIR_LIST} heavy_suite light_suite full_suite vtr_basic vtr_strong pre_commit pre_merge) - -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used - -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output - -C|--config $(_prt_cur_arg ${_CONFIG_OVERRIDE}) Add a config override file - - FLAGS: + FLAGS -g|--generate_bench $(_prt_cur_arg ${_GENERATE_BENCH}) Generate input and output vector for test -o|--generate_output $(_prt_cur_arg ${_GENERATE_OUTPUT}) Generate output vector for test given its input vector -b|--build_config $(_prt_cur_arg ${_GENERATE_CONFIG}) Generate a config file for a given directory -c|--clean $(_prt_cur_arg off ) Clean temporary directory -f|--force_simulate $(_prt_cur_arg ${_FORCE_SIM}) Force the simulation to be executed regardless of the config + --override $(_prt_cur_arg ${_OVERRIDE_CONFIG}) if a config file is passed in, override arguments rather than append + + OPTIONS + -h|--help $(_prt_cur_arg off) print this + -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used + -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output + -C|--config $(_prt_cur_arg ${_EXTRA_CONFIG}) Add a config file to append to the config for the tests + -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is either a absolute or relative path to + a directory containing a task.conf, task_list.conf + (see CONFIG FILE HELP) or one of the following predefined test + + AVAILABLE_TEST: + + regression_test/benchmark/suite/ +$( echo "${SUITE_LIST}" | awk '{print "\t " $0}') + + regression_test/benchmark/task/ +$( echo "${TASK_LIST}" | awk '{print "\t " $0}') + + vtr_reg_ +$( echo "${VTR_REG_LIST}" | awk '{print "\t " substr($0,9)}') + CONFIG FILE HELP: " @@ -131,11 +162,11 @@ function init_temp() { OUTPUT_DIRECTORY=${_RUN_DIR_OVERRIDE} fi - last_run=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) + PREVIOUS_RUN_DIR=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) n="1" - if [ "_${last_run}" != "_" ] + if [ "_${PREVIOUS_RUN_DIR}" != "_" ] then - n=$(echo ${last_run##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') + n=$(echo ${PREVIOUS_RUN_DIR##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') fi NEW_RUN_DIR=${OUTPUT_DIRECTORY}/run$(printf "%03d" $n) @@ -150,6 +181,11 @@ function create_temp() { rm -Rf ${REGRESSION_DIR}/latest || /bin/true ln -s ${NEW_RUN_DIR} ${REGRESSION_DIR}/latest + + # put in the passed parameter for keepsake + echo ${_TEST} > ${NEW_RUN_DIR}/cmd.task + echo "=========" + echo "$0 ${INPUT}" >> ${NEW_RUN_DIR}/cmd.task fi } @@ -212,94 +248,108 @@ function mv_failed() { fi } + function parse_args() { + PARSE_SUBTEST="off" while [[ "$#" > 0 ]] do - case $1 in + if [ ${PARSE_SUBTEST} == "on" ]; + then + # parse subtest + _SUBTEST_LIST="$1 ${_SUBTEST_LIST}" + shift + else + # parse [ OPTIONS / FLAGS ] + case $1 in - # Help Desk - -h|--help) - echo "Printing Help information" - help - _exit_with_code "0" + # Help Desk + -h|--help) + echo "Printing Help information" + help + _exit_with_code "0" - - ## directory in benchmark - ;;-t|--test) - # this is handled down stream - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi + + ## directory in benchmark + ;;-t|--test) + # this is handled down stream + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _TEST="$2" + shift + + ;;-d|--output_dir) + + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _RUN_DIR_OVERRIDE=$2 - _TEST="$2" - shift + if [ ! -d "${_RUN_DIR_OVERRIDE}" ] + then + echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" + _exit_with_code "-1" + fi - ;;-d|--output_dir) + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _RUN_DIR_OVERRIDE=$2 + ;;-C|--config) - if [ ! -d "${_RUN_DIR_OVERRIDE}" ] - then - echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" - _exit_with_code "-1" - fi + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _EXTRA_CONFIG=$2 + echo "Reading extra config directive from ${_EXTRA_CONFIG}" - shift + shift - ;;-C|--config) + ## number + ;;-j|--nb_of_process) + _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) + echo "Using [$2] processors for this benchmarking suite" + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _CONFIG_OVERRIDE=$2 - echo "Reading override from ${_CONFIG_OVERRIDE}" + # Boolean flags + ;;-g|--generate_bench) + _GENERATE_BENCH="on" + echo "generating output vector for test given predefined input" - shift + ;;-o|--generate_output) + _GENERATE_OUTPUT="on" + echo "generating input and output vector for test" - ## number - ;;-j|--nb_of_process) - _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) - echo "Using [$2] processors for this benchmarking suite" - shift + ;;-b|--build_config) + _GENERATE_CONFIG="on" + echo "generating a config file for test directory" - # Boolean flags - ;;-g|--generate_bench) - _GENERATE_BENCH="on" - echo "generating output vector for test given predefined input" + ;;-c|--clean) + echo "Cleaning temporary run in directory" + cleanup_temp - ;;-o|--generate_output) - _GENERATE_OUTPUT="on" - echo "generating input and output vector for test" + ;;-f|--force_simulate) + _FORCE_SIM="on" + echo "Forcing Simulation" - ;;-b|--build_config) - _GENERATE_CONFIG="on" - echo "generating a config file for test directory" + ;;--override) + _OVERRIDE_CONFIG="on" + echo "Forcing override of config" - ;;-c|--clean) - echo "Cleaning temporary run in directory" - cleanup_temp - - ;;-f|--force_simulate) - _FORCE_SIM="on" - echo "Forcing Simulation" + ;;*) + PARSE_SUBTEST="on" + esac - ;;*) - echo "Unknown parameter passed: $1" - help - _exit_with_code "-1" - esac - shift + # keep the subtest in case we caught the end of options and flags + [ ${PARSE_SUBTEST} != "on" ] && shift + fi done } @@ -440,11 +490,21 @@ function populate_arg_from_file() { IFS=${OLD_IFS} fi - _regression_params=$(echo "${_local_regression_params} ") - _script_simulation_params=$(echo "${_local_script_simulation_params} ") - _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") - _synthesis_params=$(echo "${_local_synthesis_params} ") - _simulation_params=$(echo "${_local_simulation_params} ") + if [ "${_OVERRIDE_CONFIG}" == "on" ]; + then + _regression_params=$(echo "${_local_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") + _synthesis_params=$(echo "${_local_synthesis_params} ") + _simulation_params=$(echo "${_local_simulation_params} ") + else + _regression_params=$(echo "${_local_regression_params} ${_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ${_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ${_script_synthesis_params}") + _synthesis_params=$(echo "${_local_synthesis_params} ${_synthesis_params}") + _simulation_params=$(echo "${_local_simulation_params} ${_simulation_params}") + fi + _circuit_list=$(echo "${_circuit_list} ") _arch_list=$(echo "${_arch_list} ") _circuit_dir=$(echo "${THIS_DIR}/${_circuit_dir}") @@ -560,7 +620,6 @@ function run_bench_in_parallel() { function sim() { - ########################################### # find the benchmark benchmark_dir=$1 @@ -577,283 +636,314 @@ function sim() { benchmark_dir=$(readlink -f "${benchmark_dir}") bench_name=$(basename ${benchmark_dir}) - echo "Task is: ${bench_name}" - ########################################## - # setup the parameters + # check if we only run some subtask + run_benchmark="off" + if [ "_${_SUBTEST_LIST}" == "_" ]; + then + run_benchmark="on" + else + for subtest in ${_SUBTEST_LIST}; + do + if [ "_${subtest%%/*}" == "_${bench_name}" ] + then + run_benchmark="on" + break; + fi + done + fi + + if [ "${run_benchmark}" == "on" ]; + then + echo "Task is: ${bench_name}" - init_args_for_test - populate_arg_from_file "${benchmark_dir}/task.conf" + ########################################## + # setup the parameters - ########################################## - # use the overrides from the user - if [ "_${_CONFIG_OVERRIDE}" != "_" ] - then - _CONFIG_OVERRIDE=$(readlink -f ${_CONFIG_OVERRIDE}) - if [ ! -f ${_CONFIG_OVERRIDE} ] + init_args_for_test + populate_arg_from_file "${benchmark_dir}/task.conf" + + ########################################## + # use the overrides from the user + if [ "_${_EXTRA_CONFIG}" != "_" ] then - echo "Passed in an invalid global configuration file ${_CONFIG_OVERRIDE}" - _exit_with_code "-1" - else - populate_arg_from_file "${_CONFIG_OVERRIDE}" + _EXTRA_CONFIG=$(readlink -f ${_EXTRA_CONFIG}) + if [ ! -f ${_EXTRA_CONFIG} ] + then + echo "Passed in an invalid global configuration file ${_EXTRA_CONFIG}" + _exit_with_code "-1" + else + populate_arg_from_file "${_EXTRA_CONFIG}" + fi fi - fi - #################################### - # parse the function commands passed - _threads=${_NUMBER_OF_PROCESS} - _generate_bench="off" - _generate_output="off" - _concat_circuit_list="off" - _synthesis="on" - _simulation="on" + #################################### + # parse the function commands passed + _threads=${_NUMBER_OF_PROCESS} + _generate_bench="off" + _generate_output="off" + _concat_circuit_list="off" + _synthesis="on" + _simulation="on" + + ########################################## + # populate the wrapper command using the configs + for _regression_param in ${_regression_params} + do + case ${_regression_param} in - ########################################## - # populate the wrapper command using the configs - for _regression_param in ${_regression_params} - do - case ${_regression_param} in + --concat_circuit_list) + _concat_circuit_list="on" + ;; - --concat_circuit_list) - _concat_circuit_list="on" - ;; + --generate_bench) + echo "This test will have the input and output regenerated" + _generate_bench="on" + ;; - --generate_bench) - echo "This test will have the input and output regenerated" - _generate_bench="on" - ;; + --generate_output) + echo "This test will have the output regenerated" + _generate_output="on" + ;; - --generate_output) - echo "This test will have the output regenerated" - _generate_output="on" - ;; + --disable_simulation) + echo "This test will not be simulated" + if [ "_${_FORCE_SIM}" == "on" ] + then + echo "WARNING: This test will be forcefully simulated, unexpected results may occur" + _simulation="on" + else + _simulation="off" + fi + ;; + + --disable_parallel_jobs) + echo "This test will not be multithreaded" + _threads="1" + ;; + + --include_default_arch) + _arch_list="no_arch ${_arch_list}" + ;; - --disable_simulation) - echo "This test will not be simulated" - if [ "_${_FORCE_SIM}" == "on" ] - then - echo "WARNING: This test will be forcefully simulated, unexpected results may occur" - _simulation="on" - else - _simulation="off" - fi - ;; - - --disable_parallel_jobs) - echo "This test will not be multithreaded" - _threads="1" + *) + echo "Unknown internal parameter passed: ${_regression_param}" + config_help + _exit_with_code "-1" + ;; + esac + done + + ########################################## + # setup defaults + global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" + global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + + wrapper_synthesis_file_name="wrapper_synthesis_params" + wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" + wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" + wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" + + circuit_list_temp="" + if [ ${_concat_circuit_list} == "on" ] + then + circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" + _circuit_list=${bench_name} + fi + + for circuit in $(echo ${_circuit_list}) + do + circuit_dir=$(dirname ${circuit}) + circuit_file=$(basename ${circuit}) + input_verilog_file="" + input_blif_file="" + + case "${circuit_file}" in + *.v) + input_verilog_file="${circuit}" + _synthesis="on" ;; - - --include_default_arch) - _arch_list="no_arch ${_arch_list}" + *.blif) + input_blif_file="${circuit}" + # disable synthesis for blif files + _synthesis="off" ;; - - *) - echo "Unknown internal parameter passed: ${_regression_param}" - config_help - _exit_with_code "-1" + *) + if [ ${_concat_circuit_list} == "on" ] + then + input_verilog_file="${circuit_list_temp}" + _synthesis="on" + else + echo "Invalid circuit passed in: ${circuit}, skipping" + continue + fi ;; - esac - done - - ########################################## - # setup defaults - global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" - global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + esac + circuit_name="${circuit_file%.*}" - wrapper_synthesis_file_name="wrapper_synthesis_params" - wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" - wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" - wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" - circuit_list_temp="" - if [ ${_concat_circuit_list} == "on" ] - then - circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" - _circuit_list=${bench_name} - fi + # lookup for input and output vector files to do comparison + input_vector_file="${circuit_dir}/${circuit_name}_input" + output_vector_file="${circuit_dir}/${circuit_name}_output" - for circuit in $(echo ${_circuit_list}) - do - circuit_dir=$(dirname ${circuit}) - circuit_file=$(basename ${circuit}) - input_verilog_file="" - input_blif_file="" - - case "${circuit_file}" in - *.v) - input_verilog_file="${circuit}" - _synthesis="on" - ;; - *.blif) - input_blif_file="${circuit}" - # disable synthesis for blif files - _synthesis="off" - ;; - *) - if [ ${_concat_circuit_list} == "on" ] + for arches in $(echo ${_arch_list}) + do + arch_cmd="" + if [ -e ${arches} ] then - input_verilog_file="${circuit_list_temp}" - _synthesis="on" - else - echo "Invalid circuit passed in: ${circuit}, skipping" - continue + arch_cmd="-a ${arches}" fi - ;; - esac - circuit_name="${circuit_file%.*}" + arch_name=$(basename ${arches%.*}) - # lookup for input and output vector files to do comparison - input_vector_file="${circuit_dir}/${circuit_name}_input" - output_vector_file="${circuit_dir}/${circuit_name}_output" + TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - for arches in $(echo ${_arch_list}) - do - arch_cmd="" - if [ -e ${arches} ] - then - arch_cmd="-a ${arches}" - fi + run_this_test="on" - arch_name=$(basename ${arches%.*}) - - TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" - mkdir -p $DIR - - ############################### - # Synthesis - if [ "${_synthesis}" == "on" ] - then - - # if synthesis was on, we need to specify a blif output name - input_blif_file="${DIR}/${circuit_name}.blif" - - synthesis_params_file=${DIR}/synthesis_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_synthesis_params} - --log_file ${DIR}/synthesis.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_synthesis_failure}.log - ${synthesis_params_file}" - - synthesis_command="${ODIN_EXEC} - ${_synthesis_params} - ${arch_cmd} - -V ${input_verilog_file} - -o ${input_blif_file} - -sim_dir ${DIR}" - - _echo_args "${synthesis_command}" > ${synthesis_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} - fi - ############################### - # Simulation - if [ "${_simulation}" == "on" ] - then - simulation_params_file=${DIR}/simulation_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_simulation_params} - --log_file ${DIR}/simulation.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_simulation_failure}.log - ${simulation_params_file}" - - simulation_command="${ODIN_EXEC} - ${_simulation_params} - ${arch_cmd} - -b ${input_blif_file} - -sim_dir ${DIR}" - - if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + if [ "_${_SUBTEST_LIST}" != "_" ]; then - _echo_args "${simulation_command}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + echo ${_SUBTEST_LIST} | grep "${TEST_FULL_REF}" &> /dev/null + [ "$?" != "0" ] && run_this_test="off" + fi - elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + if [ "${run_this_test}" == "on" ]; then - _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} - else - _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" + mkdir -p $DIR + ############################### + # Synthesis + if [ "${_synthesis}" == "on" ] + then + + # if synthesis was on, we need to specify a blif output name + input_blif_file="${DIR}/${circuit_name}.blif" + + synthesis_params_file=${DIR}/synthesis_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_synthesis_params} + --log_file ${DIR}/synthesis.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_synthesis_failure}.log + ${synthesis_params_file}" + + synthesis_command="${ODIN_EXEC} + ${_synthesis_params} + ${arch_cmd} + -V ${input_verilog_file} + -o ${input_blif_file} + -sim_dir ${DIR}" + + _echo_args "${synthesis_command}" > ${synthesis_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} + fi + ############################### + # Simulation + if [ "${_simulation}" == "on" ] + then + simulation_params_file=${DIR}/simulation_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_simulation_params} + --log_file ${DIR}/simulation.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_simulation_failure}.log + ${simulation_params_file}" + + simulation_command="${ODIN_EXEC} + ${_simulation_params} + ${arch_cmd} + -b ${input_blif_file} + -sim_dir ${DIR}" + + if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + then + _echo_args "${simulation_command}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + + elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + then + _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} + + else + _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + + fi + fi fi + done + done - fi - - done - done - - #synthesize the circuits - if [ "${_synthesis}" == "on" ] - then - run_bench_in_parallel \ - "Synthesis" \ - "${_threads}" \ - "${global_synthesis_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" - fi + #synthesize the circuits + if [ "${_synthesis}" == "on" ] + then + run_bench_in_parallel \ + "Synthesis" \ + "${_threads}" \ + "${global_synthesis_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" + fi - if [ "${_simulation}" == "on" ] - then + if [ "${_simulation}" == "on" ] + then - run_bench_in_parallel \ - "Generate_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" - - run_bench_in_parallel \ - "Generate_Output_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" - - run_bench_in_parallel \ - "Predefined_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" + run_bench_in_parallel \ + "Generate_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" + + run_bench_in_parallel \ + "Generate_Output_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" + + run_bench_in_parallel \ + "Predefined_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" - fi + fi - INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the input vectors - for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") - do - BM_DIR=$(dirname ${sim_input_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" + # move the input vectors + for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") + do + BM_DIR=$(dirname ${sim_input_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" - cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} - - done - fi + cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} + + done + fi - OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the output vectors - for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") - do - BM_DIR=$(dirname ${sim_output_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" + # move the output vectors + for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") + do + BM_DIR=$(dirname ${sim_output_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" - cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} + cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} - done + done + fi fi } @@ -914,7 +1004,7 @@ function run_suite() { input_path=$(ls -d -1 ${THIS_DIR}/${input_path} 2> /dev/null) ;; esac - + input_list=( ${input_list[@]} ${input_path[@]} ) done @@ -931,7 +1021,6 @@ function run_suite() { ;; *) - # bash expand when possible echo "no such Directory for task: ${current_input}" ;; esac @@ -978,8 +1067,9 @@ then fi _TEST=$(readlink -f ${_TEST}) +_TEST_NAME=$(basename ${_TEST}) -echo "Task: ${_TEST}" +echo "Task: ${_TEST_NAME} (${_TEST})" input_list=( "${_TEST}" ) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index f604e291657..28deac94516 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -110,7 +110,12 @@ std::vector t_physical_tile_type::get_clock_pins_indices() const { int clock_pins_start_idx = 0; int clock_pins_stop_idx = 0; - for (int capacity_num = 0; capacity_num < this->capacity; capacity_num++) { + int num_capacity = 1; + if (capacity_type == e_capacity_type::DUPLICATE) { + num_capacity = this->capacity; + } + + for (int capacity_num = 0; capacity_num < num_capacity; capacity_num++) { // Ranges are picked on the basis that pins are ordered: inputs, outputs, then clock pins // This is because ProcessPb_type assigns pb_type port indices in that order and // SetupPinLocationsAndPinClasses assigns t_logical_block_type_ptr pin indices in the order of port indices diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 36901e6f0ed..e28832bf918 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -523,6 +523,12 @@ enum class e_sb_type { }; +enum class e_capacity_type { + DUPLICATE, // Capacity duplicates ports. + EXPLICIT // Capacity increases the number of logical tiles, but does not + // modify the physical ports. +}; + constexpr int NO_SWITCH = -1; constexpr int DEFAULT_SWITCH = -2; @@ -577,6 +583,7 @@ struct t_physical_tile_type { int num_clock_pins = 0; int capacity = 0; + e_capacity_type capacity_type = e_capacity_type::DUPLICATE; int width = 0; int height = 0; @@ -625,18 +632,20 @@ struct t_physical_tile_type { * vtr::bimap container. */ struct t_logical_pin { + int z_index = -1; int pin = -1; - t_logical_pin(int value) { + t_logical_pin(int z_index_value, int value) { + z_index = z_index_value; pin = value; } bool operator==(const t_logical_pin o) const { - return pin == o.pin; + return z_index == o.z_index && pin == o.pin; } bool operator<(const t_logical_pin o) const { - return pin < o.pin; + return std::make_pair(z_index, pin) < std::make_pair(o.z_index, o.pin); } }; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 32381facab6..bba80f64fda 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -86,10 +86,10 @@ static void LoadPinLoc(pugi::xml_node Locations, t_physical_tile_type* type, const pugiutil::loc_data& loc_data); template -static std::pair ProcessPinString(pugi::xml_node Locations, - T type, - const char* pin_loc_string, - const pugiutil::loc_data& loc_data); +static std::pair> ProcessPinString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ static void ProcessTiles(pugi::xml_node Node, @@ -427,7 +427,12 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations, pugi::xml_node Cur; - capacity = PhysicalTileType->capacity; + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + capacity = PhysicalTileType->capacity; + } else { + VTR_ASSERT(PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } if (!Locations) { PhysicalTileType->pin_location_distribution = E_SPREAD_PIN_DISTR; } else { @@ -811,23 +816,40 @@ static void LoadPinLoc(pugi::xml_node Locations, VTR_ASSERT(ipin == output_pins.size()); } else { + int capacity; + if (type->capacity_type == e_capacity_type::DUPLICATE) { + capacity = type->capacity; + } else { + VTR_ASSERT(type->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } + VTR_ASSERT(type->pin_location_distribution == E_CUSTOM_PIN_DISTR); for (int width = 0; width < type->width; ++width) { for (int height = 0; height < type->height; ++height) { for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { for (int pin = 0; pin < type->num_pin_loc_assignments[width][height][side]; ++pin) { - auto pin_range = ProcessPinString(Locations, - type, - type->pin_loc_assignments[width][height][side][pin], - loc_data); + int instance_idx; + std::pair pin_range; + std::tie(instance_idx, pin_range) = ProcessPinString(Locations, + type, + type->pin_loc_assignments[width][height][side][pin], + loc_data); + if (instance_idx != 0) { + archfpga_throw( + loc_data.filename_c_str(), + loc_data.line(Locations), + "Instance index is not allocated on custom pin: %s\n", + type->pin_loc_assignments[width][height][side][pin]); + } for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { - VTR_ASSERT(pin_num < type->num_pins / type->capacity); - for (int capacity = 0; capacity < type->capacity; ++capacity) { - type->pinloc[width][height][side][pin_num + capacity * type->num_pins / type->capacity] = true; - type->pin_width_offset[pin_num + capacity * type->num_pins / type->capacity] += width; - type->pin_height_offset[pin_num + capacity * type->num_pins / type->capacity] += height; - physical_pin_counts[pin_num + capacity * type->num_pins / type->capacity] += 1; + VTR_ASSERT(pin_num < type->num_pins / capacity); + for (int icapacity = 0; icapacity < capacity; ++icapacity) { + type->pinloc[width][height][side][pin_num + icapacity * type->num_pins / capacity] = true; + type->pin_width_offset[pin_num + icapacity * type->num_pins / capacity] += width; + type->pin_height_offset[pin_num + icapacity * type->num_pins / capacity] += height; + physical_pin_counts[pin_num + icapacity * type->num_pins / capacity] += 1; } } } @@ -848,10 +870,11 @@ static void LoadPinLoc(pugi::xml_node Locations, } template -static std::pair ProcessPinString(pugi::xml_node Locations, - T type, - const char* pin_loc_string, - const pugiutil::loc_data& loc_data) { +static std::pair> ProcessPinString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data) { + int instance_idx = 0; int num_tokens; auto tokens = GetTokensFromString(pin_loc_string, &num_tokens); @@ -866,6 +889,31 @@ static std::pair ProcessPinString(pugi::xml_node Locations, token_index++; token = tokens[token_index]; + if (token.type == TOKEN_OPEN_SQUARE_BRACKET) { + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Instance index is not a valid number: %s\n", + pin_loc_string); + } + + instance_idx = vtr::atoi(token.data); + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Missing close brace on instance index: %s\n", + pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + } + if (token.type != TOKEN_DOT) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "No dot is present to separate type name and port name: %s\n", pin_loc_string); @@ -893,7 +941,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, // All the pins of the port are taken or the port has a single pin if (token_index == num_tokens) { freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx, abs_first_pin_idx + port->num_pins); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx, abs_first_pin_idx + port->num_pins)); } token = tokens[token_index]; @@ -931,7 +979,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, } freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + first_pin + 1); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + first_pin + 1)); } token_index++; @@ -964,7 +1012,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, } freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + last_pin + 1); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + last_pin + 1)); } static void ProcessPinToPinAnnotations(pugi::xml_node Parent, @@ -2065,9 +2113,16 @@ static void Process_Fc(pugi::xml_node Node, /* Go through all the port/segment combinations and create the (potentially * overriden) pin/seg Fc specifications */ - int pins_per_capacity_instance = PhysicalTileType->num_pins / PhysicalTileType->capacity; + int capacity; + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + capacity = PhysicalTileType->capacity; + } else { + VTR_ASSERT(PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } + int pins_per_capacity_instance = PhysicalTileType->num_pins / capacity; for (size_t iseg = 0; iseg < segments.size(); ++iseg) { - for (int icapacity = 0; icapacity < PhysicalTileType->capacity; ++icapacity) { + for (int icapacity = 0; icapacity < capacity; ++icapacity) { //If capacity > 0, we need t offset the block index by the number of pins per instance //this ensures that all pins have an Fc specification int iblk_pin = icapacity * pins_per_capacity_instance; @@ -2998,12 +3053,21 @@ static void ProcessTiles(pugi::xml_node Node, /* Process tile port definitions */ ProcessTilePorts(CurTileType, &PhysicalTileType, loc_data); - PhysicalTileType.num_pins = PhysicalTileType.capacity - * (PhysicalTileType.num_input_pins - + PhysicalTileType.num_output_pins - + PhysicalTileType.num_clock_pins); - PhysicalTileType.num_receivers = PhysicalTileType.capacity * PhysicalTileType.num_input_pins; - PhysicalTileType.num_drivers = PhysicalTileType.capacity * PhysicalTileType.num_output_pins; + if (PhysicalTileType.capacity_type == e_capacity_type::DUPLICATE) { + PhysicalTileType.num_pins = PhysicalTileType.capacity + * (PhysicalTileType.num_input_pins + + PhysicalTileType.num_output_pins + + PhysicalTileType.num_clock_pins); + PhysicalTileType.num_receivers = PhysicalTileType.capacity * PhysicalTileType.num_input_pins; + PhysicalTileType.num_drivers = PhysicalTileType.capacity * PhysicalTileType.num_output_pins; + } else { + VTR_ASSERT(PhysicalTileType.capacity_type == e_capacity_type::EXPLICIT); + PhysicalTileType.num_pins = (PhysicalTileType.num_input_pins + + PhysicalTileType.num_output_pins + + PhysicalTileType.num_clock_pins); + PhysicalTileType.num_receivers = PhysicalTileType.num_input_pins; + PhysicalTileType.num_drivers = PhysicalTileType.num_output_pins; + } /* Assign Fc, Pin locations ans Switch Block locations to the Physical Tile Type */ @@ -3050,7 +3114,7 @@ static void ProcessTiles(pugi::xml_node Node, static void ProcessTileProps(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data) { - expect_only_attributes(Node, {"name", "capacity", "width", "height", "area"}, loc_data); + expect_only_attributes(Node, {"name", "capacity", "capacity_type", "width", "height", "area"}, loc_data); /* Load type name */ auto Prop = get_attribute(Node, "name", loc_data).value(); @@ -3066,6 +3130,20 @@ static void ProcessTileProps(pugi::xml_node Node, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Area for type %s must be non-negative\n", PhysicalTileType->name); } + + const char* capacity_type = get_attribute(Node, "capacity_type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (capacity_type) { + if (strcmp(capacity_type, "duplicate") == 0) { + PhysicalTileType->capacity_type = e_capacity_type::DUPLICATE; + } else if (strcmp(capacity_type, "explicit") == 0) { + PhysicalTileType->capacity_type = e_capacity_type::EXPLICIT; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Unknown 'capacity_type' %s\n", capacity_type); + } + } else { + PhysicalTileType->capacity_type = e_capacity_type::DUPLICATE; + } } static void ProcessTilePorts(pugi::xml_node Parent, @@ -3261,11 +3339,16 @@ static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, PhysicalTileType->name); } + if (PhysicalTileType->capacity_type != e_capacity_type::DUPLICATE) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Custom site pins are required if capacity_type == explicit\n"); + } + vtr::bimap directs_map; for (int npin = 0; npin < num_pins; npin++) { t_physical_pin physical_pin(npin); - t_logical_pin logical_pin(npin); + t_logical_pin logical_pin(/*z_index=*/0, npin); directs_map.insert(logical_pin, physical_pin); } @@ -3302,8 +3385,35 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, // `to` attribute is relative to the logical block pins to = std::string(get_attribute(CurDirect, "to", loc_data).value()); - auto from_pins = ProcessPinString(CurDirect, PhysicalTileType, from.c_str(), loc_data); - auto to_pins = ProcessPinString(CurDirect, LogicalBlockType, to.c_str(), loc_data); + int to_idx; + int from_idx; + std::pair from_pins; + std::pair to_pins; + std::tie(from_idx, from_pins) = ProcessPinString(CurDirect, PhysicalTileType, from.c_str(), loc_data); + std::tie(to_idx, to_pins) = ProcessPinString(CurDirect, LogicalBlockType, to.c_str(), loc_data); + + if (from_idx != 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "No physical tile instance index is allowed: %s.\n", from.c_str()); + } + + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + if (to_idx != 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Logical tile instances are not allowed with capacity_type == DUPLICATE: %s\n", + to.c_str()); + } + } else if (PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT) { + if (to_idx < 0 || to_idx >= PhysicalTileType->capacity) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Logical tile instance %d is out of bounds of capacity: %s\n", + to_idx, to.c_str()); + } + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Unknown capacity_type %d.\n", + PhysicalTileType->capacity_type); + } // Checking that the number of pins is exactly the same if (from_pins.second - from_pins.first != to_pins.second - to_pins.first) { @@ -3316,7 +3426,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, int num_pins = from_pins.second - from_pins.first; for (int i = 0; i < num_pins; i++) { t_physical_pin physical_pin(from_pins.first + i); - t_logical_pin logical_pin(to_pins.first + i); + t_logical_pin logical_pin(to_idx, to_pins.first + i); auto result = directs_map.insert(logical_pin, physical_pin); if (!result.second) { @@ -4861,33 +4971,43 @@ static void link_physical_logical_types(std::vector& Physi for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) { for (auto& tile : logical_block.equivalent_tiles) { - auto direct_map = tile->tile_block_pin_directs_map.at(logical_block.index); - auto result = direct_map.find(t_logical_pin(pin)); - if (result == direct_map.end()) { - archfpga_throw(__FILE__, __LINE__, - "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", - pin, tile->name, logical_block.name); + int capacity; + if (tile->capacity_type == e_capacity_type::DUPLICATE) { + capacity = 1; + } else { + VTR_ASSERT(tile->capacity_type == e_capacity_type::EXPLICIT); + capacity = tile->capacity; } - int phy_index = result->second.pin; + for (int z_index = 0; z_index < capacity; ++z_index) { + const auto& direct_map = tile->tile_block_pin_directs_map.at(logical_block.index); + auto result = direct_map.find(t_logical_pin(z_index, pin)); + if (result == direct_map.end()) { + archfpga_throw(__FILE__, __LINE__, + "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", + pin, tile->name, logical_block.name); + } - bool is_ignored = tile->is_ignored_pin[phy_index]; - bool is_global = tile->is_pin_global[phy_index]; + int phy_index = result->second.pin; - auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); - if (!ignored_result.second && ignored_result.first->second != is_ignored) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); - } + bool is_ignored = tile->is_ignored_pin[phy_index]; + bool is_global = tile->is_pin_global[phy_index]; - auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); - if (!global_result.second && global_result.first->second != is_global) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); + auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); + if (!ignored_result.second && ignored_result.first->second != is_ignored) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } + + auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); + if (!global_result.second && global_result.first->second != is_global) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } } } } @@ -4905,7 +5025,15 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t auto& pin_direct_mapping = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - if (pb_type->num_pins != (int)pin_direct_mapping.size()) { + int capacity; + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + capacity = 1; + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + capacity = physical_tile->capacity; + } + + if (pb_type->num_pins * capacity != (int)pin_direct_mapping.size()) { archfpga_throw(__FILE__, __LINE__, "Logical block (%s) and Physical tile (%s) have a different number of ports.\n", logical_block->name, physical_tile->name); diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index 982f313cafc..e306dda21a5 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -25,9 +25,9 @@ #include "expr_eval.h" static DeviceGrid auto_size_device_grid(const std::vector& grid_layouts, const std::map& minimum_instance_counts, float maximum_device_utilization); -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map instance_counts, float maximum_utilization); -static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); static void CheckGrid(const DeviceGrid& grid); @@ -152,7 +152,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo //specifications size_t width = 3; size_t height = 3; - std::vector limiting_resources; + std::vector limiting_resources; do { //Scale opposite dimension to match aspect ratio height = vtr::nint(width / grid_def.aspect_ratio); @@ -203,7 +203,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo }; std::stable_sort(grid_layouts_view.begin(), grid_layouts_view.end(), area_cmp); - std::vector limiting_resources; + std::vector limiting_resources; //Try all the fixed devices in order from smallest to largest for (const auto* grid_def : grid_layouts_view) { @@ -220,37 +220,58 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo return grid; //Unreachable } -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { + //Estimates what logical block types will be unimplementable due to resource limits in the available grid + // + //Performs a fast counting based estimate, allocating the least flexible block types (those with the fewest + //equivalent tiles) first. auto& device_ctx = g_vpr_ctx.device(); - std::vector overused_resources; + std::vector overused_resources; std::unordered_map min_count_map; // Initialize min_count_map - for (const auto& physical_tile : device_ctx.physical_tile_types) { - min_count_map.insert(std::make_pair(&physical_tile, size_t(0))); + for (const auto& tile_type : device_ctx.physical_tile_types) { + min_count_map.insert(std::make_pair(&tile_type, size_t(0))); } - //Are the resources satisified? - for (auto kv : instance_counts) { - t_physical_tile_type_ptr type = nullptr; + //Initialize available tile counts + std::unordered_map avail_tiles; + for (auto& tile_type : device_ctx.physical_tile_types) { + avail_tiles[&tile_type] = grid.num_instances(&tile_type); + } - size_t inst_cnt = 0; - for (auto& physical_tile : kv.first->equivalent_tiles) { - size_t tmp_inst_cnt = grid.num_instances(physical_tile); + //Sort so we allocate logical blocks with the fewest equivalent sites first (least flexible) + std::vector logical_block_types; + for (auto& block_type : device_ctx.logical_block_types) { + logical_block_types.push_back(&block_type); + } - if (inst_cnt <= tmp_inst_cnt) { - type = physical_tile; - inst_cnt = tmp_inst_cnt; - } - } + auto by_ascending_equiv_tiles = [](t_logical_block_type_ptr lhs, t_logical_block_type_ptr rhs) { + return lhs->equivalent_tiles.size() < rhs->equivalent_tiles.size(); + }; + std::stable_sort(logical_block_types.begin(), logical_block_types.end(), by_ascending_equiv_tiles); + + //Allocate logical blocks to available tiles + for (auto block_type : logical_block_types) { + if (instance_counts.count(block_type)) { + int required_blocks = instance_counts[block_type]; + + for (auto tile_type : block_type->equivalent_tiles) { + if (avail_tiles[tile_type] >= required_blocks) { + avail_tiles[tile_type] -= required_blocks; + required_blocks = 0; + } else { + required_blocks -= avail_tiles[tile_type]; + avail_tiles[tile_type] = 0; + } - VTR_ASSERT(type); - size_t min_count = min_count_map.at(type) + kv.second; - min_count_map.at(type) = min_count; + if (required_blocks == 0) break; + } - if (inst_cnt < min_count) { - overused_resources.push_back(type); + if (required_blocks > 0) { + overused_resources.push_back(block_type); + } } } @@ -276,7 +297,7 @@ static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map limiting_resources) { +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range, const std::vector limiting_resources) { if (grid_def.grid_type == GridDefType::FIXED) { if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 0ffa8c306f7..5c8cf3eaa0e 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -378,6 +378,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->write_router_lookahead = Options.write_router_lookahead; RouterOpts->read_router_lookahead = Options.read_router_lookahead; RouterOpts->disable_check_route = Options.disable_check_route; + RouterOpts->quick_check_route = Options.quick_check_route; } static void SetupAnnealSched(const t_options& Options, diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index ac2f324eb92..dc9d1e51d01 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -79,7 +79,7 @@ void printClusteredNetlistStats() { num_blocks_type[logical_block->index]++; if (is_io_type(physical_tile)) { for (j = 0; j < logical_block->pb_type->num_pins; j++) { - int physical_pin = get_physical_pin(physical_tile, logical_block, j); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, j); auto pin_class = physical_tile->pin_class[physical_pin]; auto class_inf = physical_tile->class_inf[pin_class]; diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index ba8e6eea93e..bd1af72f348 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -839,26 +839,16 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { }); std::string new_net_name; - if (!driver_is_pi && !po_in_input_sinks && !po_in_output_sinks) { - //No PIs or POs, we can choose arbitarily in this case - new_net_name = netlist.net_name(output_net); - } else if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { + if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { //Must use the input name to perserve primary-input or primary-output name new_net_name = netlist.net_name(input_net); - - } else if ((!driver_is_pi && !po_in_input_sinks) && po_in_output_sinks) { + } else if (!(driver_is_pi || po_in_input_sinks) && po_in_output_sinks) { //Must use the output name to perserve primary-output name new_net_name = netlist.net_name(output_net); - } else { - VTR_ASSERT((driver_is_pi || po_in_input_sinks) && po_in_output_sinks); - //This is a buffered connection from a primary input to primary output, or to - //more than one primary output. - //TODO: consider implications of removing these... - - //Do not remove such buffers - return false; + //Arbitrarily merge the net names + new_net_name = netlist.net_name(input_net) + "__" + netlist.net_name(output_net); } size_t initial_input_net_pins = netlist.net_pins(input_net).size(); diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index ee77a8b8fff..aeafa487e82 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -95,7 +95,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi auto physical_type = pick_best_physical_type(logical_type); int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); - int pin_index = get_physical_pin(physical_type, logical_type, log_index); + int pin_index = get_physical_pin(physical_type, /*z_index=*/0, logical_type, log_index); if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !is_io_type(physical_type)) { diff --git a/vpr/src/base/device_grid.cpp b/vpr/src/base/device_grid.cpp index 3be488d26dd..e4e05a7241c 100644 --- a/vpr/src/base/device_grid.cpp +++ b/vpr/src/base/device_grid.cpp @@ -7,7 +7,7 @@ DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid) count_instances(); } -DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) +DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) : DeviceGrid(grid_name, grid) { limiting_resources_ = limiting_res; } diff --git a/vpr/src/base/device_grid.h b/vpr/src/base/device_grid.h index 6f0584c94db..44bdc8b6659 100644 --- a/vpr/src/base/device_grid.h +++ b/vpr/src/base/device_grid.h @@ -8,7 +8,7 @@ class DeviceGrid { public: DeviceGrid() = default; DeviceGrid(std::string grid_name, vtr::Matrix grid); - DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); + DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); const std::string& name() const { return name_; } @@ -25,7 +25,7 @@ class DeviceGrid { //Returns the block types which limits the device size (may be empty if //resource limits were not considered when selecting the device). - std::vector limiting_resources() const { return limiting_resources_; } + std::vector limiting_resources() const { return limiting_resources_; } private: void count_instances(); @@ -39,7 +39,7 @@ class DeviceGrid { std::map instance_counts_; - std::vector limiting_resources_; + std::vector limiting_resources_; }; #endif diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index a44ad17e6b3..c2b570740f4 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -951,7 +951,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { block_type = clb_nlist.block_type(blk_id); auto tile_type = pick_best_physical_type(block_type); for (j = 0; j < block_type->pb_type->num_pins; j++) { - int physical_pin = get_physical_pin(tile_type, block_type, j); + int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, j); //Iterate through each pin of the block, and see if there is a net allocated/used for it clb_net_id = clb_nlist.block_net(blk_id, j); @@ -1001,7 +1001,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id)); auto tile_type = pick_best_physical_type(block_type); int logical_pin = clb_nlist.pin_logical_index(pin_id); - int physical_pin = get_physical_pin(tile_type, block_type, logical_pin); + int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, logical_pin); if (tile_type->is_ignored_pin[physical_pin] != is_ignored_net) { VTR_LOG_WARN( diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 123c4d854be..1235d001302 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1645,6 +1645,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.quick_check_route, "--quick_check_route") + .help("Runs check_route, disabling slow checks, once routing step has finished or when routing file is loaded") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.router_debug_net, "--router_debug_net") .help( "Controls when router debugging is enabled.\n" diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 55c2695d828..59a67ddbeb8 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -135,6 +135,7 @@ struct t_options { argparse::ArgValue RouterAlgorithm; argparse::ArgValue min_incremental_reroute_fanout; argparse::ArgValue disable_check_route; + argparse::ArgValue quick_check_route; /* Timing-driven router options only */ argparse::ArgValue astar_fac; diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 9ec4069fe2c..6d4dd1142ed 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -23,6 +23,7 @@ #include "rr_graph.h" #include "vtr_assert.h" #include "vtr_util.h" +#include "vtr_time.h" #include "tatum/echo_writer.hpp" #include "vtr_log.h" #include "check_route.h" @@ -40,6 +41,7 @@ #include "echo_files.h" #include "route_common.h" #include "read_route.h" +#include "rr_graph2.h" /*************Functions local to this module*************/ static void process_route(std::ifstream& fp, const char* filename, int& lineno); @@ -192,7 +194,7 @@ static void process_nets(std::ifstream& fp, ClusterNetId inet, std::string name, static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno) { /* Not a global net. Goes through every node and add it into trace.head*/ - auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); + auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.mutable_device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); auto& place_ctx = g_vpr_ctx.placement(); @@ -206,6 +208,45 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file std::string input; std::vector tokens; + // Build lookup from SOURCE/SINK node to ClusterBlockId. + std::unordered_map node_to_block; + + { + vtr::ScopedStartFinishTimer timer("Building ClusterBlockId lookup"); + + for (auto net_id : cluster_ctx.clb_nlist.nets()) { + int pin_count = 0; + for (auto pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) { + auto block_id = cluster_ctx.clb_nlist.pin_block(pin_id); + + const auto* logical_tile = cluster_ctx.clb_nlist.block_type(block_id); + const auto* physical_tile = physical_tile_type(block_id); + VTR_ASSERT(block_id); + int i = place_ctx.block_locs[block_id].loc.x; + int j = place_ctx.block_locs[block_id].loc.y; + + int logical_pin_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); + int physical_pin_index = get_physical_pin( + physical_tile, place_ctx.block_locs[block_id].loc.z, + logical_tile, logical_pin_index); + int physical_pin_class = physical_tile->pin_class[physical_pin_index]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */ + physical_pin_class); + + auto result = node_to_block.insert(std::make_pair(class_inode, block_id)); + if (!result.second && result.first->second != block_id) { + vpr_throw(VPR_ERROR_ROUTE, filename, lineno, + "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?", + class_inode, (size_t)block_id, result.first->second); + } + pin_count++; + } + } + + VTR_LOG("ClusterBlockId lookup has %zu entries\n", node_to_block.size()); + } + /*Walk through every line that begins with Node:*/ while (std::getline(fp, input)) { ++lineno; @@ -285,9 +326,22 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file if (tokens[6 + offset] != "Switch:") { /*This is an opin or ipin, process its pin nums*/ if (!is_io_type(device_ctx.grid[x][y].type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { + // Convert this IPIN/OPIN back to class. + auto rr_type = device_ctx.rr_nodes[inode].type(); + VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); int pin_num = device_ctx.rr_nodes[inode].ptc_num(); - int height_offset = device_ctx.grid[x][y].height_offset; - ClusterBlockId iblock = place_ctx.grid_blocks[x][y - height_offset].blocks[0]; + int iclass = device_ctx.grid[x][y].type->pin_class[pin_num]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + x, y, (rr_type == OPIN ? SOURCE : SINK), iclass); + + auto itr = node_to_block.find(class_inode); + if (itr == node_to_block.end()) { + vpr_throw(VPR_ERROR_ROUTE, filename, lineno, + "Class RR node %d does not have an associated ClusterBlockId?", class_inode); + } + + ClusterBlockId iblock = itr->second; + VTR_ASSERT(iblock); t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num); t_pb_type* pb_type = pb_pin->parent_node->pb_type; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1688f0ae932..cde7cf9dab7 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -689,7 +689,7 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { if (route_status.success()) { //Sanity check the routing if (!router_opts.disable_check_route) { - check_route(router_opts.route_type); + check_route(router_opts.route_type, router_opts.quick_check_route); } get_serial_num(); diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 06b3731cf2b..9cd7e176bb0 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -286,6 +286,7 @@ struct RoutingContext : public Context { vtr::vector> trace_nodes; vtr::vector> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ + std::unordered_map rr_net_map; vtr::vector> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */ diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index f5266ef97a4..b92f5743049 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -956,6 +956,7 @@ struct t_router_opts { std::string write_router_lookahead; std::string read_router_lookahead; bool disable_check_route; + bool quick_check_route; }; struct t_analysis_opts { diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index 21a2781ee31..aac65fff2e3 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -59,7 +59,7 @@ void button_for_toggle_blk_internal() { t_draw_state* draw_state = get_draw_state_vars(); //spin box for toggle_blk_internal, set the range and increment step - GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)draw_state->max_sub_blk_lvl, 1.); + GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)(draw_state->max_sub_blk_lvl - 1), 1.); GtkWidget* toggle_blk_internal_label = gtk_label_new("Toggle Block Internal:"); gtk_widget_set_name(toggle_blk_internal_widget, "toggle_blk_internal"); diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index d29ede76133..8743140e6ec 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -124,7 +124,6 @@ static t_edge_size find_edge(int prev_inode, int inode); static void draw_color_map_legend(const vtr::ColorMap& cmap, ezgl::renderer* g); -ezgl::color get_block_type_color(t_physical_tile_type_ptr type); ezgl::color lighten_color(ezgl::color color, float amount); static void draw_block_pin_util(); @@ -826,7 +825,8 @@ void alloc_draw_structs(const t_arch* arch) { draw_internal_alloc_blk(); draw_state->net_color.resize(cluster_ctx.clb_nlist.nets().size()); - draw_state->block_color.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->use_default_block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); /* Space is allocated for draw_rr_node but not initialized because we do * * not yet know information about the routing resources. */ @@ -934,6 +934,7 @@ static void drawplace(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); + auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_ctx = g_vpr_ctx.placement(); ClusterBlockId bnum; @@ -961,15 +962,20 @@ static void drawplace(ezgl::renderer* g) { if (bnum == INVALID_BLOCK_ID) continue; //Determine the block color ezgl::color block_color; + t_logical_block_type_ptr logical_block_type = nullptr; if (bnum != EMPTY_BLOCK_ID) { - block_color = draw_state->block_color[bnum]; + block_color = draw_state->block_color(bnum); + logical_block_type = cluster_ctx.clb_nlist.block_type(bnum); } else { block_color = get_block_type_color(device_ctx.grid[i][j].type); block_color = lighten_color(block_color, EMPTY_BLOCK_LIGHTEN_FACTOR); + + auto tile_type = device_ctx.grid[i][j].type; + logical_block_type = pick_best_logical_type(tile_type); } g->set_color(block_color); /* Get coords of current sub_tile */ - ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k); + ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k, logical_block_type); ezgl::point2d center = abs_clb_bbox.center(); g->fill_rectangle(abs_clb_bbox); @@ -980,7 +986,6 @@ static void drawplace(ezgl::renderer* g) { g->draw_rectangle(abs_clb_bbox); /* Draw text if the space has parts of the netlist */ if (bnum != EMPTY_BLOCK_ID && bnum != INVALID_BLOCK_ID) { - auto& cluster_ctx = g_vpr_ctx.clustering(); std::string name = cluster_ctx.clb_nlist.block_name(bnum) + vtr::string_fmt(" (#%zu)", size_t(bnum)); g->draw_text(center, name.c_str(), abs_clb_bbox.width(), abs_clb_bbox.height()); @@ -2661,12 +2666,12 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b continue; auto physical_tile = physical_tile_type(blk_id); - int physical_pin = get_physical_pin(physical_tile, type, k); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, type, k); iclass = physical_tile->pin_class[physical_pin]; if (physical_tile->class_inf[iclass].type == DRIVER) { /* Fanout */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanout. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { @@ -2678,11 +2683,11 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b draw_state->net_color[net_id] = DRIVES_IT_COLOR; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { fanblk = cluster_ctx.clb_nlist.pin_block(pin_id); - draw_state->block_color[fanblk] = DRIVES_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVES_IT_COLOR); } } } else { /* This net is fanin to the block. */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanin. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ @@ -2691,17 +2696,17 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b /* Highlight the fanin */ draw_state->net_color[net_id] = DRIVEN_BY_IT_COLOR; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ - draw_state->block_color[fanblk] = DRIVEN_BY_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVEN_BY_IT_COLOR); } } } - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the selected block. */ draw_reset_blk_color(blk_id); } else { /* Highlight the selected block. */ - draw_state->block_color[blk_id] = SELECTED_COLOR; + draw_state->set_block_color(blk_id, SELECTED_COLOR); } } @@ -2730,13 +2735,8 @@ void deselect_all() { } static void draw_reset_blk_color(ClusterBlockId blk_id) { - auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - auto logical_block = clb_nlist.block_type(blk_id); - t_draw_state* draw_state = get_draw_state_vars(); - - draw_state->block_color[blk_id] = get_block_type_color(pick_best_physical_type(logical_block)); + draw_state->reset_block_color(blk_id); } /** @@ -3337,7 +3337,7 @@ static void draw_block_pin_util() { for (auto blk : blks) { ezgl::color color = to_ezgl_color(cmap->color(pin_util[blk])); - draw_state->block_color[blk] = color; + draw_state->set_block_color(blk, color); } draw_state->color_map = std::move(cmap); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index eb8dd4c2df7..acc9d214572 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -77,6 +77,8 @@ void toggle_block_pin_util(GtkWidget* /*widget*/, gint /*response_id*/, gpointer void toggle_router_rr_costs(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); void toggle_placement_macros(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); +ezgl::color get_block_type_color(t_physical_tile_type_ptr type); + #endif /* NO_GRAPHICS */ #endif /* DRAW_H */ diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index 68e6df6062d..158546f7ec4 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -15,8 +15,6 @@ # include "draw_types.h" -# define MAX_BLOCK_COLOURS 5 - constexpr float DEFAULT_ARROW_SIZE = 0.3; // a very small area, in (screen pixels)^2 diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index 5d6e4ca7a83..fdb0755b689 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -4,11 +4,34 @@ # include "draw_types.h" # include "globals.h" # include "vpr_utils.h" +# include "draw.h" # include /******************************************* * begin t_draw_state function definitions * *******************************************/ +ezgl::color t_draw_state::block_color(ClusterBlockId blk) const { + if (use_default_block_color_[blk]) { + t_physical_tile_type_ptr tile_type = get_physical_tile_type(blk); + return get_block_type_color(tile_type); + } else { + return block_color_[blk]; + } +} + +void t_draw_state::set_block_color(ClusterBlockId blk, ezgl::color color) { + block_color_[blk] = color; + use_default_block_color_[blk] = false; +} + +void t_draw_state::reset_block_color(ClusterBlockId blk) { + use_default_block_color_[blk] = true; +} +void t_draw_state::reset_block_colors() { + std::fill(use_default_block_color_.begin(), + use_default_block_color_.end(), + true); +} void t_draw_state::reset_nets_congestion_and_rr() { show_nets = DRAW_NO_NETS; @@ -19,6 +42,7 @@ void t_draw_state::reset_nets_congestion_and_rr() { bool t_draw_state::showing_sub_blocks() { return show_blk_internal > 0; } + /************************************************** * begin t_draw_pb_type_info function definitions * **************************************************/ @@ -53,14 +77,33 @@ float t_draw_coords::get_tile_height() { ezgl::rectangle t_draw_coords::get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode) { auto& place_ctx = g_vpr_ctx.placement(); - return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, pb_gnode); + auto& cluster_ctx = g_vpr_ctx.clustering(); + return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, cluster_ctx.clb_nlist.block_type(clb_index), pb_gnode); +} + +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type, const t_pb_graph_node& pb_gnode) { + auto& device_ctx = g_vpr_ctx.device(); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); + + ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); + + // if getting clb bbox, apply location info. + if (pb_gnode.is_root()) { + float sub_blk_offset = this->tile_width * (sub_block_index / (float)device_ctx.grid[grid_x][grid_y].type->capacity); + + result += ezgl::point2d(this->tile_x[grid_x], this->tile_y[grid_y]); + if (sub_block_index != 0) { + result += ezgl::point2d(sub_blk_offset, 0); + } + } + return result; } -ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode) { +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { auto& device_ctx = g_vpr_ctx.device(); - const int clb_type_id = device_ctx.grid[grid_x][grid_y].type->index; - t_draw_pb_type_info& blk_type_info = this->blk_info.at(clb_type_id); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); + auto& pb_gnode = *logical_block_type->pb_graph_head; ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); // if getting clb bbox, apply location info. @@ -89,13 +132,20 @@ ezgl::rectangle t_draw_coords::get_absolute_pb_bbox(const ClusterBlockId clb_ind return result; } -ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type) { - return get_pb_bbox(clb_index, *type->pb_graph_head); +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr block_type) { + auto& place_ctx = g_vpr_ctx.placement(); + + t_pl_loc loc = place_ctx.block_locs[clb_index].loc; + return get_pb_bbox(loc.x, loc.y, loc.z, block_type); } ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index) { auto& device_ctx = g_vpr_ctx.device(); - return get_pb_bbox(grid_x, grid_y, sub_block_index, *pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head); + return get_pb_bbox(grid_x, grid_y, sub_block_index, pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)); +} + +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { + return get_pb_bbox(grid_x, grid_y, sub_block_index, logical_block_type); } #endif // NO_GRAPHICS diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index f6e507a02ac..1ef320afabc 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -172,7 +172,6 @@ struct t_draw_state { e_route_type draw_route_type = GLOBAL; char default_message[vtr::bufsize]; vtr::vector net_color; - vtr::vector block_color; t_draw_rr_node* draw_rr_node = nullptr; std::shared_ptr setup_timing_info; const t_arch* arch_info = nullptr; @@ -185,6 +184,16 @@ struct t_draw_state { void reset_nets_congestion_and_rr(); bool showing_sub_blocks(); + + ezgl::color block_color(ClusterBlockId blk) const; + void set_block_color(ClusterBlockId blk, ezgl::color color); + void reset_block_color(ClusterBlockId blk); + void reset_block_colors(); + + private: + friend void alloc_draw_structs(const t_arch* arch); + vtr::vector block_color_; + vtr::vector use_default_block_color_; }; /* For each cluster type, this structure stores drawing @@ -228,7 +237,8 @@ struct t_draw_coords { * clb, from this data structure */ ezgl::rectangle get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode); - ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type); /** * Return a bounding box for the given pb in the given @@ -243,6 +253,8 @@ struct t_draw_coords { ezgl::rectangle get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type); ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index); + ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr block_type); + private: float tile_width; friend void init_draw_coords(float); diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index a3771f7fed5..2c2166ecd95 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -40,7 +40,6 @@ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height); static int draw_internal_find_max_lvl(const t_pb_type& pb_type); static void draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, int num_pb_types, int type_index, int num_pb, int pb_index, float parent_width, float parent_height, float* blk_width, float* blk_height); -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type); std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); @@ -68,7 +67,7 @@ void draw_internal_alloc_blk() { draw_coords->blk_info.resize(device_ctx.logical_block_types.size()); for (const auto& type : device_ctx.logical_block_types) { - if (&type == device_ctx.EMPTY_LOGICAL_BLOCK_TYPE) { + if (is_empty_type(&type)) { continue; } @@ -90,17 +89,24 @@ void draw_internal_init_blk() { t_pb_graph_node* pb_graph_head_node; auto& device_ctx = g_vpr_ctx.device(); - for (const auto& type : device_ctx.physical_tile_types) { + for (const auto& type : device_ctx.logical_block_types) { /* Empty block has no sub_blocks */ if (is_empty_type(&type)) { continue; } - auto logical_block = pick_best_logical_type(&type); - pb_graph_head_node = logical_block->pb_graph_head; + pb_graph_head_node = type.pb_graph_head; int type_descriptor_index = type.index; - int num_sub_tiles = type.capacity; + //We use the maximum over all tiles which can implement this logical block type + int num_sub_tiles = 1; + int width = 1; + int height = 1; + for (const auto& tile : type.equivalent_tiles) { + num_sub_tiles = std::max(num_sub_tiles, tile->capacity); + width = std::max(width, tile->width); + height = std::max(height, tile->height); + } // set the clb dimensions ezgl::rectangle& clb_bbox = draw_coords->blk_info.at(type_descriptor_index).subblk_array.at(0); @@ -110,17 +116,17 @@ void draw_internal_init_blk() { // note, that all clbs of the same type are the same size, // and that consequently we have *one* model for each type. bot_left = {0, 0}; - if (size_t(type.width) > device_ctx.grid.width() || size_t(type.height) > device_ctx.grid.height()) { + if (size_t(width) > device_ctx.grid.width() || size_t(height) > device_ctx.grid.height()) { // in this case, the clb certainly wont't fit, but this prevents // an out-of-bounds access, and provides some sort of (probably right) // value top_right = ezgl::point2d( - (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (type.width - 1), - (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (type.height - 1)); + (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (width - 1), + (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (height - 1)); } else { top_right = ezgl::point2d( - draw_coords->tile_x[type.width - 1], - draw_coords->tile_y[type.height - 1]); + draw_coords->tile_x[width - 1], + draw_coords->tile_y[height - 1]); } top_right += ezgl::point2d( draw_coords->get_tile_width() / num_sub_tiles, @@ -131,9 +137,10 @@ void draw_internal_init_blk() { clb_bbox.width(), clb_bbox.height()); /* Determine the max number of sub_block levels in the FPGA */ - draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*logical_block->pb_type), + draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*type.pb_type), draw_state->max_sub_blk_lvl); } + //draw_state->max_sub_blk_lvl -= 1; } # ifndef NO_GRAPHICS @@ -153,7 +160,7 @@ void draw_internal_draw_subblk(ezgl::renderer* g) { continue; /* Don't draw if tile is empty. This includes corners. */ - if (device_ctx.grid[i][j].type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) + if (is_empty_type(device_ctx.grid[i][j].type)) continue; int num_sub_tiles = device_ctx.grid[i][j].type->capacity; @@ -331,54 +338,33 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg if (pb_type->depth > draw_state->show_blk_internal) { return; } - /// first draw box /// - if (pb_type->depth == 0) { - if (!is_top_lvl_block_highlighted(clb_index, type)) { - // if this is a top level pb, and only if it isn't selected (ie. a funny colour), - // overwrite it. (but stil draw the text) + /// first draw box /// - g->set_color(ezgl::WHITE); - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->set_line_dash(ezgl::line_dash::none); - g->draw_rectangle(abs_bbox); + if (pb->name != nullptr) { + // If block is used, draw it in colour with solid border. + g->set_line_dash(ezgl::line_dash::none); + + // determine default background color + if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { + g->set_color(SELECTED_COLOR); + } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVES_IT_COLOR); + } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVEN_BY_IT_COLOR); + } else { + g->set_color(draw_state->block_color(clb_index)); } } else { - if (pb->name != nullptr) { - // If block is used, draw it in colour with solid border. - g->set_line_dash(ezgl::line_dash::none); - - // type_index indicates what type of block. - const int type_index = type->index; - - // determine default background color - if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { - g->set_color(SELECTED_COLOR); - } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVES_IT_COLOR); - } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVEN_BY_IT_COLOR); - } else if (pb_type->depth != draw_state->show_blk_internal && pb->child_pbs != nullptr) { - g->set_color(ezgl::WHITE); // draw anything else that will have a child as white - } else if (type_index < 3) { - g->set_color(blk_LIGHTGREY); - } else if (type_index < 3 + MAX_BLOCK_COLOURS) { - g->set_color((block_colors[MAX_BLOCK_COLOURS + type_index - 3])); - } else { - g->set_color((block_colors[2 * MAX_BLOCK_COLOURS - 1])); - } - } else { - // If block is not used, draw as empty block (ie. white - // background with dashed border). + // If block is not used, draw as empty block (ie. white + // background with dashed border). - g->set_line_dash(ezgl::line_dash::asymmetric_5_3); - g->set_color(ezgl::WHITE); - } - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->draw_rectangle(abs_bbox); + g->set_line_dash(ezgl::line_dash::asymmetric_5_3); + g->set_color(ezgl::WHITE); } + g->fill_rectangle(abs_bbox); + g->set_color(ezgl::BLACK); + g->draw_rectangle(abs_bbox); /// then draw text /// @@ -393,7 +379,7 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg int tot_len = type_len + name_len; char* blk_tag = (char*)vtr::malloc((tot_len + 8) * sizeof(char)); - sprintf(blk_tag, "%s(%s)", pb_type->name, pb->name); + sprintf(blk_tag, "%s (%s)", pb_type->name, pb->name); g->draw_text( abs_bbox.center(), @@ -444,10 +430,10 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg t_pb_type* pb_child_type = child_pb->pb_graph_node->pb_type; - // don't go farther if 0 modes - if (pb_child_type == nullptr || pb_child_type->num_modes == 0) { + if (pb_child_type == nullptr) { continue; } + // now recurse draw_internal_pb(clb_index, child_pb, abs_bbox, type, g); } @@ -662,31 +648,6 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p } # endif /* NO_GRAPHICS */ -/* This function checks whether a top-level clb has been highlighted. It does - * so by checking whether the color in this block is default color. - */ -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type) { - t_draw_state* draw_state; - - /* Call accessor function to retrieve global variables. */ - draw_state = get_draw_state_vars(); - - if (type->index < 3) { - if (draw_state->block_color[blk_id] == blk_LIGHTGREY) - return false; - } else if (type->index < 3 + MAX_BLOCK_COLOURS) { - if (draw_state->block_color[blk_id] == block_colors[MAX_BLOCK_COLOURS + type->index - 3]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + MAX_BLOCK_COLOURS + type->index - 3))) - return false; - } else { - if (draw_state->block_color[blk_id] == block_colors[2 * MAX_BLOCK_COLOURS - 1]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + 2 * MAX_BLOCK_COLOURS - 1))) - return false; - } - - return true; -} - int highlight_sub_block(const ezgl::point2d& point_in_clb, ClusterBlockId clb_index, t_pb* pb) { t_draw_state* draw_state = get_draw_state_vars(); diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index bb8a98ae5d0..257793b86ff 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -66,7 +66,7 @@ static void print_stats() { auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); auto physical_tile = pick_best_physical_type(logical_block); for (ipin = 0; ipin < logical_block->pb_type->num_pins; ipin++) { - int physical_pin = get_physical_pin(physical_tile, logical_block, ipin); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, ipin); auto pin_class = physical_tile->pin_class[physical_pin]; auto pin_class_inf = physical_tile->class_inf[pin_class]; diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index c79d8647578..7060f629e5f 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -167,7 +167,6 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca ClusterBlockId blk_id; auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.placement(); auto& pl_macros = place_ctx.pl_macros; @@ -185,9 +184,7 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca return lhs_num_tiles < rhs_num_tiles; }; - if (device_ctx.has_multiple_equivalent_tiles) { - std::sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); - } + std::stable_sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); /* Macros are harder to place. Do them first */ for (auto pl_macro : sorted_pl_macros) { @@ -196,57 +193,57 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca // Assume that all the blocks in the macro are of the same type blk_id = pl_macro.members[0].blk_index; - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto type = pick_placement_type(logical_block, int(pl_macro.members.size()), free_locations); - - if (type == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); - } - - itype = type->index; + auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); - // Try to place the macro first, if can be placed - place them, otherwise try again - for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { - // Choose a random position for the head - ipos = vtr::irand(free_locations[itype] - 1); + for (auto tile_type : block_type->equivalent_tiles) { //Try each possible tile type + itype = tile_type->index; - // Try to place the macro - macro_placed = try_place_macro(itype, ipos, pl_macro); + // Try to place the macro first, if can be placed - place them, otherwise try again + for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { + // Choose a random position for the head + ipos = vtr::irand(free_locations[itype] - 1); - } // Finished all tries - - if (macro_placed == false) { - // if a macro still could not be placed after macros_max_num_tries times, - // go through the chip exhaustively to find a legal placement for the macro - // place the macro on the first location that is legal - // then set macro_placed = true; - // if there are no legal positions, error out - - // Exhaustive placement of carry macros - for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { // Try to place the macro macro_placed = try_place_macro(itype, ipos, pl_macro); - } // Exhausted all the legal placement position for this macro + } // Finished all tries - // If macro could not be placed after exhaustive placement, error out if (macro_placed == false) { - // Error out - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "Please manually size the FPGA because VPR can't do this yet.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), device_ctx.physical_tile_types[itype].name, itype); + // if a macro still could not be placed after macros_max_num_tries times, + // go through the chip exhaustively to find a legal placement for the macro + // place the macro on the first location that is legal + // then set macro_placed = true; + // if there are no legal positions, error out + + // Exhaustive placement of carry macros + for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { + // Try to place the macro + macro_placed = try_place_macro(itype, ipos, pl_macro); + + } // Exhausted all the legal placement position for this macro + + // If macro could not be placed after exhaustive placement, error out + } else { + // This macro has been placed successfully + break; } + } - } else { - // This macro has been placed successfully, proceed to place the next macro - continue; + if (macro_placed == false) { + std::vector tried_types; + for (auto tile_type : block_type->equivalent_tiles) { + tried_types.push_back(tile_type->name); + } + std::string tried_types_str = "{" + vtr::join(tried_types, ", ") + "}"; + + // Error out + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type(s) %s.\n" + "Please manually size the FPGA because VPR can't do this yet.\n", + pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), tried_types_str.c_str()); } + } // Finish placing all the pl_macros successfully } diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index ef00c65cbbe..b2ea57bf1c5 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -217,8 +217,8 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //At the moment, we only support blk_to being the first element of the 'to' macro. // //For instance, this means that we can swap two carry chains so long as one starts - //below the other (not a big limitation since swapping in the oppostie direction would - //allow these blocks to swap) + //below the other (not a big limitation since swapping in the opposite direction + //allows these blocks to swap) if (place_ctx.pl_macros[imacro_to].members[0].blk_index != blk_to) { int imember_to = 0; auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset); diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 8a2b32fd962..0d82de03fdf 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -800,6 +800,8 @@ void try_place(const t_placer_opts& placer_opts, size_t total_swap_attempts = num_swap_rejected + num_swap_accepted + num_swap_aborted; VTR_ASSERT(total_swap_attempts > 0); + print_resources_utilization(); + size_t num_swap_print_digits = ceil(log10(total_swap_attempts)); float reject_rate = (float)num_swap_rejected / total_swap_attempts; float accept_rate = (float)num_swap_accepted / total_swap_attempts; @@ -812,8 +814,6 @@ void try_place(const t_placer_opts& placer_opts, report_aborted_moves(); - print_resources_utilization(); - free_placement_structs(placer_opts); if (placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE || placer_opts.enable_timing_computations) { @@ -2572,6 +2572,9 @@ static void print_resources_utilization() { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); + int max_block_name = 0; + int max_tile_name = 0; + //Record the resource requirement std::map num_type_instances; std::map> num_placed_instances; @@ -2584,15 +2587,17 @@ static void print_resources_utilization() { num_type_instances[logical_block]++; num_placed_instances[logical_block][physical_tile]++; + + max_block_name = std::max(max_block_name, strlen(logical_block->name)); + max_tile_name = std::max(max_tile_name, strlen(physical_tile->name)); } + VTR_LOG("\n"); + VTR_LOG("Placement resource usage:\n"); for (auto logical_block : num_type_instances) { - VTR_LOG("Logical Block: %s\n", logical_block.first->name); - VTR_LOG("\tInstances -> %d\n", logical_block.second); - - VTR_LOG("\tPhysical Tiles used:\n"); for (auto physical_tile : num_placed_instances[logical_block.first]) { - VTR_LOG("\t\t%s: %d\n", physical_tile.first->name, physical_tile.second); + VTR_LOG(" %-*s implemented as %-*s: %d\n", max_block_name, logical_block.first->name, max_tile_name, physical_tile.first->name, physical_tile.second); } } + VTR_LOG("\n"); } diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 5411e3223f8..18b89732735 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -82,7 +82,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { - int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin); + int to_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, to_iblk_pin); to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); to_idirect = f_idirect_from_blk_pin[physical_tile->index][to_physical_pin]; @@ -102,7 +102,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p || (is_constant_clb_net(to_net_id) && !net_is_driven_by_direct(to_net_id)))) { for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { - int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); + int from_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, from_iblk_pin); from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); from_idirect = f_idirect_from_blk_pin[physical_tile->index][from_physical_pin]; diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index e9fa206736d..855c5d8670d 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -3,6 +3,7 @@ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_memory.h" +#include "vtr_time.h" #include "vpr_types.h" #include "vpr_error.h" @@ -27,12 +28,13 @@ static void reset_flags(ClusterNetId inet, bool* connected_to_route); static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_locally, enum e_route_type route_type); +static void check_all_non_configurable_edges(); static bool check_non_configurable_edges(ClusterNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets); static void check_net_for_stubs(ClusterNetId net); /************************ Subroutine definitions ****************************/ -void check_route(enum e_route_type route_type) { +void check_route(enum e_route_type route_type, bool quick) { /* This routine checks that a routing: (1) Describes a properly * * connected path for each net, (2) this path connects all the * * pins spanned by that net, and (3) that no routing resources are * @@ -68,8 +70,6 @@ void check_route(enum e_route_type route_type) { check_locally_used_clb_opins(route_ctx.clb_opins_used_locally, route_type); - auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); - connected_to_route = (bool*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(bool)); max_pins = 0; @@ -156,8 +156,6 @@ void check_route(enum e_route_type route_type) { } } - check_non_configurable_edges(net_id, non_configurable_rr_sets); - check_net_for_stubs(net_id); reset_flags(net_id, connected_to_route); @@ -166,6 +164,11 @@ void check_route(enum e_route_type route_type) { free(pin_done); free(connected_to_route); + + if (!quick) { + check_all_non_configurable_edges(); + } + VTR_LOG("Completed routing consistency check successfully.\n"); VTR_LOG("\n"); } @@ -625,6 +628,18 @@ static void check_node_and_range(int inode, enum e_route_type route_type) { check_rr_node(inode, route_type, device_ctx); } +//Checks that all non-configurable edges are in a legal configuration +//This check is slow, so it has been moved out of check_route() +static void check_all_non_configurable_edges() { + vtr::ScopedStartFinishTimer timer("Checking to ensure non-configurable edges are legal"); + auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); + auto& cluster_ctx = g_vpr_ctx.clustering(); + + for (auto net_id : cluster_ctx.clb_nlist.nets()) { + check_non_configurable_edges(net_id, non_configurable_rr_sets); + } +} + //Checks that the specified routing is legal with respect to non-configurable edges // //For routing to be legal if *any* non-configurable edge is used, so must *all* diff --git a/vpr/src/route/check_route.h b/vpr/src/route/check_route.h index 4ad6075ec4e..5e73383d00c 100644 --- a/vpr/src/route/check_route.h +++ b/vpr/src/route/check_route.h @@ -3,7 +3,7 @@ #include "physical_types.h" #include "route_common.h" -void check_route(enum e_route_type route_type); +void check_route(enum e_route_type route_type, bool quick); void recompute_occupancy_from_scratch(); diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp index 2c0e7c435a1..66609917624 100644 --- a/vpr/src/route/check_rr_graph.cpp +++ b/vpr/src/route/check_rr_graph.cpp @@ -177,8 +177,9 @@ void check_rr_graph(const t_graph_type graph_type, if (node.type() == IPIN || node.type() == OPIN) { if (has_adjacent_channel(node, device_ctx.grid)) { auto block_type = device_ctx.grid[node.xlow()][node.ylow()].type; - VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s has no fanin.\n", - inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string()); + std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num()); + VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n", + inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string(), pin_name.c_str()); } } else { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) has no fanin.\n", diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index c6dd9449a4e..4da1df55862 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -86,7 +86,8 @@ static t_trace_branch traceback_branch(int node, std::unordered_set& main_b static std::pair add_trace_non_configurable(t_trace* head, t_trace* tail, int node, std::unordered_set& visited); static std::pair add_trace_non_configurable_recurr(int node, std::unordered_set& visited, int depth = 0); -static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices); +static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices, + std::unordered_map* rr_net_map); static vtr::vector> load_rr_clb_sources(const t_rr_node_indices& L_rr_node_indices); static t_clb_opins_used alloc_and_load_clb_opins_used_locally(); @@ -479,7 +480,7 @@ void init_route_structs(int bb_factor) { Bucket::init(device_ctx.grid); //Various look-ups - route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices); + route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices, &route_ctx.rr_net_map); route_ctx.route_bb = load_route_bb(bb_factor); route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_node_indices); route_ctx.clb_opins_used_locally = alloc_and_load_clb_opins_used_locally(); @@ -990,7 +991,11 @@ void reset_rr_node_route_structs() { /* Allocates and loads the route_ctx.net_rr_terminals data structure. For each net it stores the rr_node * * index of the SOURCE of the net and all the SINKs of the net [clb_nlist.nets()][clb_nlist.net_pins()]. * * Entry [inet][pnum] stores the rr index corresponding to the SOURCE (opin) or SINK (ipin) of the pin. */ -static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices) { +static vtr::vector> load_net_rr_terminals( + const t_rr_node_indices& L_rr_node_indices, + std::unordered_map* rr_net_map) { + VTR_ASSERT(rr_net_map != nullptr); + rr_net_map->clear(); vtr::vector> net_rr_terminals; auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -1020,6 +1025,16 @@ static vtr::vector> load_net_rr_terminals(const t int inode = get_rr_node_index(L_rr_node_indices, i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */ iclass); net_rr_terminals[net_id][pin_count] = inode; + + auto result = rr_net_map->insert(std::make_pair(inode, block_id)); + // If the map already contains an entry for inode, make sure it + // is consistent with the existing entry. + if (!result.second && block_id != result.first->second) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?", + inode, (size_t)block_id, (size_t)result.first->second); + } + pin_count++; } } @@ -1263,11 +1278,18 @@ void print_route(FILE* fp, const vtr::vector& traceba fprintf(fp, "%d ", device_ctx.rr_nodes[inode].ptc_num()); if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) { + // Go from IPIN/OPIN to SOURCE/SINK + auto* type = device_ctx.grid[ilow][jlow].type; int pin_num = device_ctx.rr_nodes[inode].ptc_num(); - int xoffset = device_ctx.grid[ilow][jlow].width_offset; - int yoffset = device_ctx.grid[ilow][jlow].height_offset; - ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0]; - VTR_ASSERT(iblock); + int iclass = type->pin_class[pin_num]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + ilow, jlow, (rr_type == OPIN ? SOURCE : SINK), iclass); + + // Use the rr_net_map to go from class inode back to ClusterBlockId. + auto itr = route_ctx.rr_net_map.find(class_inode); + VTR_ASSERT(itr != route_ctx.rr_net_map.end()); + ClusterBlockId iblock = itr->second; + t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num); t_pb_type* pb_type = pb_pin->parent_node->pb_type; fprintf(fp, " %s.%s[%d] ", pb_type->name, pb_pin->port->name, pb_pin->pin_number); diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index 8987e1aaf3a..b36d674aacb 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -179,7 +179,6 @@ static std::vector timing_driven_find_all_shortest_paths_from_heap(const RouterStats& router_stats); void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* node); - static inline void timing_driven_expand_cheapest(t_heap* cheapest, int target_node, const t_conn_cost_params cost_params, @@ -1602,8 +1601,8 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, int inode = cheapest->index; - float old_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; - float old_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; float new_total_cost = cheapest->cost; float new_back_cost = cheapest->backward_path_cost; @@ -1616,7 +1615,9 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, * than one with higher cost. Test whether or not I should disallow * * re-expansion based on a higher total cost. */ - if (old_total_cost > new_total_cost && old_back_cost > new_back_cost) { + if (best_total_cost > new_total_cost && best_back_cost > new_back_cost) { + //Explore from this node, since the current/new partial path has the best cost + //found so far VTR_LOGV_DEBUG(f_router_debug, " Better cost to %d\n", inode); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); @@ -1634,9 +1635,11 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, target_node, router_stats); } else { + //Post-heap prune, do not re-explore from the current/new partial path as it + //has worse cost than the best partial path to this node found so far VTR_LOGV_DEBUG(f_router_debug, " Worse cost to %d\n", inode); - VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", old_total_cost); - VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", old_back_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", best_total_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", best_back_cost); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); } @@ -2089,22 +2092,25 @@ static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_para auto& route_ctx = g_vpr_ctx.routing(); - float old_next_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; - float old_next_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; + + float new_total_cost = next->cost; + float new_back_cost = next->backward_path_cost; - float new_next_total_cost = next->cost; - float new_next_back_cost = next->backward_path_cost; + VTR_ASSERT_SAFE(next->index == to_node); - if (old_next_total_cost > new_next_total_cost && old_next_back_cost > new_next_back_cost) { - //Add node to the heap only if the current cost is less than its historic cost, since - //there is no point in for the router to expand more expensive paths. + if (new_total_cost < best_total_cost && new_back_cost < best_back_cost) { + //Add node to the heap only if the cost via the current partial path is less than the + //best known cost, since there is no reason for the router to expand more expensive paths. + // + //Pre-heap prune to keep the heap small, by not putting paths which are known to be + //sub-optimal (at this point in time) into the heap. VTR_LOGV_DEBUG(f_router_debug, " Adding node %8d to heap from init route tree with cost %g (%s)\n", - next->index, new_next_total_cost, describe_rr_node(next->index).c_str()); + next->index, new_total_cost, describe_rr_node(next->index).c_str()); add_to_heap(next); ++router_stats.heap_pushes; - } - - else { + } else { free_heap_data(next); } } diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 13a0da96c0f..50d1e11eacf 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -192,15 +192,21 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_ std::string pin_name = type->name; - if (type->capacity > 1) { - int pins_per_inst = type->num_pins / type->capacity; - int inst_num = pin_index / pins_per_inst; - pin_index %= pins_per_inst; + if (type->capacity_type == e_capacity_type::DUPLICATE) { + if (type->capacity > 1) { + int pins_per_inst = type->num_pins / type->capacity; + int inst_num = pin_index / pins_per_inst; + pin_index %= pins_per_inst; - pin_name += "[" + std::to_string(inst_num) + "]"; - } + pin_name += "[" + std::to_string(inst_num) + "]"; + } - pin_name += "."; + pin_name += "."; + } else { + VTR_ASSERT(type->capacity_type == e_capacity_type::EXPLICIT); + VTR_ASSERT(pin_index < type->num_pins); + pin_name += "."; + } int curr_index = 0; for (auto const& port : type->ports) { @@ -319,7 +325,7 @@ std::vector find_clb_pin_connected_atom_pins(ClusterBlockId clb, int auto logical_block = clb_nlist.block_type(clb); auto physical_tile = pick_best_physical_type(logical_block); - int physical_pin = get_physical_pin(physical_tile, logical_block, logical_pin); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, logical_pin); if (is_opin(physical_pin, physical_tile)) { //output @@ -2067,21 +2073,18 @@ void place_sync_external_block_connections(ClusterBlockId iblk) { auto physical_tile = physical_tile_type(iblk); auto logical_block = clb_nlist.block_type(iblk); - VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0); - int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity; - /* Logical location and physical location is offset by z * max_num_block_pins */ - for (auto pin : clb_nlist.block_pins(iblk)) { int logical_pin_index = clb_nlist.pin_logical_index(pin); - int physical_pin_index = get_physical_pin(physical_tile, logical_block, logical_pin_index); - - int new_physical_pin_index = physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins; - auto result = place_ctx.physical_pins.find(pin); - if (result != place_ctx.physical_pins.end()) { - place_ctx.physical_pins[pin] = new_physical_pin_index; + int new_physical_pin = get_physical_pin( + physical_tile, place_ctx.block_locs[iblk].loc.z, + logical_block, logical_pin_index); + auto iter = place_ctx.physical_pins.find(pin); + if (iter != place_ctx.physical_pins.end()) { + *iter = new_physical_pin; } else { - place_ctx.physical_pins.insert(pin, new_physical_pin_index); + place_ctx.physical_pins.insert( + pin, new_physical_pin); } } } @@ -2123,32 +2126,48 @@ t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physica return physical_tile->equivalent_sites[0]; } -int get_logical_pin(t_physical_tile_type_ptr physical_tile, - t_logical_block_type_ptr logical_block, - int pin) { - t_physical_pin physical_pin(pin); +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) { + auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& place_ctx = g_vpr_ctx.placement(); + if (place_ctx.block_locs.empty()) { //No placement, pick best match + return pick_best_physical_type(cluster_ctx.clb_nlist.block_type(blk)); + } else { //Have placement, select physical tile implementing blk + auto& device_ctx = g_vpr_ctx.device(); - auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - auto result = direct_map.find(physical_pin); + t_pl_loc loc = place_ctx.block_locs[blk].loc; - if (result == direct_map.inverse_end()) { - VTR_LOG_WARN( - "Couldn't find the corresponding logical pin of the physical pin %d." - "Physical Tile: %s, Logical Block: %s.\n", - pin, physical_tile->name, logical_block->name); - return OPEN; + return device_ctx.grid[loc.x][loc.y].type; } +} - return result->second.pin; +int get_physical_pin(const ClusterBlockId blk, + t_logical_block_type_ptr logical_block, + int pin) { + auto& place_ctx = g_vpr_ctx.placement(); + auto& device_ctx = g_vpr_ctx.device(); + + auto block_loc = place_ctx.block_locs[blk]; + auto loc = block_loc.loc; + + return get_physical_pin( + device_ctx.grid[loc.x][loc.y].type, + loc.z, + logical_block, + pin); } int get_physical_pin(t_physical_tile_type_ptr physical_tile, + int z_index, t_logical_block_type_ptr logical_block, int pin) { - t_logical_pin logical_pin(pin); - - auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - auto result = direct_map.find(logical_pin); + const auto& direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); + auto result = direct_map.begin(); + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + result = direct_map.find(t_logical_pin(/*z_index=*/0, pin)); + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + result = direct_map.find(t_logical_pin(z_index, pin)); + } if (result == direct_map.end()) { VTR_LOG_WARN( @@ -2158,7 +2177,15 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, return OPEN; } - return result->second.pin; + int physical_pin_index = result->second.pin; + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity; + /* Logical location and physical location is offset by z * max_num_block_pins */ + return physical_pin_index + z_index * max_num_block_pins; + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + return physical_pin_index; + } } int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index c511bc243df..6ea3a5d4a1a 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -156,13 +156,22 @@ void place_sync_external_block_connections(ClusterBlockId iblk); int get_max_num_pins(t_logical_block_type_ptr logical_block); bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block); + +//Returns the physical tile type which 'best' matches logical_block t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block); + +//Returns the logical block type which 'best' matches the physical tile t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile); -int get_logical_pin(t_physical_tile_type_ptr physical_tile, - t_logical_block_type_ptr logical_block, - int pin); +//Returns the current tile implemnting blk (if placement is valid), or +//the best expected physical tile the block should use (if no valid placement). +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk); + int get_physical_pin(t_physical_tile_type_ptr physical_tile, + int z_index, + t_logical_block_type_ptr logical_block, + int pin); +int get_physical_pin(const ClusterBlockId blk, t_logical_block_type_ptr logical_block, int pin); diff --git a/vtr_flow/benchmarks/tests/riscv_core_lut6.blif b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif new file mode 100644 index 00000000000..a313bebc127 --- /dev/null +++ b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif @@ -0,0 +1,19187 @@ +# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os) + +.model riscv_core +.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31] +.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31] +.names $false +.names $true +1 +.names $undef +.names $abc$8517$new_n299_ $abc$8517$new_n303_ inst[2] regfile_write_enable +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n302_ $abc$8517$new_n301_ $abc$8517$new_n300_ $abc$8517$new_n299_ +000 1 +.names inst[1] inst[0] inst[2] inst[4] inst[3] inst[6] $abc$8517$new_n300_ +111100 1 +.names inst[1] inst[0] inst[4] inst[2] inst[3] inst[6] $abc$8517$new_n301_ +111000 1 +.names inst[1] inst[0] inst[2] inst[6] inst[5] inst[4] $abc$8517$new_n302_ +111110 1 +.names inst[1] inst[0] inst[3] inst[6] inst[5] inst[4] $abc$8517$new_n303_ +110000 1 +.names $abc$8517$new_n1349_ $abc$8517$new_n1352_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1344_ bus_address[0] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n307_ $abc$8517$new_n374_ $abc$8517$new_n407_ $abc$8517$new_n404_ $abc$8517$new_n409_ $abc$8517$new_n340_ $abc$8517$new_n306_ +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n308_ $abc$8517$new_n322_ $abc$8517$new_n336_ $abc$8517$new_n307_ +110 1 +.names $abc$8517$new_n319_ $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n308_ +000 1 +.names $abc$8517$new_n315_ $abc$8517$new_n310_ $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ rs2_data[19] $abc$8517$new_n309_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[4] inst[6] $abc$8517$new_n302_ inst[5] inst[2] $abc$8517$new_n310_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names inst[1] inst[0] inst[3] $abc$8517$new_n311_ +110 1 +.names $abc$8517$new_n313_ inst[3] inst[6] inst[5] inst[4] inst[2] $abc$8517$new_n312_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[1] inst[0] $abc$8517$new_n313_ +11 1 +.names inst[19] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n314_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[19] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n315_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n318_ $abc$8517$new_n310_ $abc$8517$new_n317_ inst[31] $abc$8517$new_n312_ rs2_data[18] $abc$8517$new_n316_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[18] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n317_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[18] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n318_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n321_ $abc$8517$new_n310_ $abc$8517$new_n320_ inst[31] $abc$8517$new_n312_ rs2_data[17] $abc$8517$new_n319_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[17] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n320_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[17] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[17] $abc$8517$new_n321_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n333_ $abc$8517$new_n330_ $abc$8517$new_n327_ $abc$8517$new_n323_ $abc$8517$new_n322_ +0000 1 +.names $abc$8517$new_n326_ $abc$8517$new_n310_ $abc$8517$new_n325_ inst[31] $abc$8517$new_n324_ rs2_data[23] $abc$8517$new_n323_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[5] inst[2] inst[6] inst[4] $abc$8517$new_n302_ $abc$8517$new_n324_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100110 1 +101010 1 +101100 1 +101110 1 +110010 1 +110110 1 +111010 1 +111100 1 +111110 1 +.names inst[23] $abc$8517$new_n300_ $abc$8517$new_n325_ +11 1 +.names rs1_data[23] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n326_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n329_ $abc$8517$new_n310_ $abc$8517$new_n328_ inst[31] $abc$8517$new_n324_ rs2_data[22] $abc$8517$new_n327_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[22] $abc$8517$new_n300_ $abc$8517$new_n328_ +11 1 +.names rs1_data[22] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n329_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n332_ $abc$8517$new_n310_ $abc$8517$new_n331_ inst[31] $abc$8517$new_n324_ rs2_data[21] $abc$8517$new_n330_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[21] $abc$8517$new_n300_ $abc$8517$new_n331_ +11 1 +.names rs1_data[21] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[21] $abc$8517$new_n332_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n335_ $abc$8517$new_n310_ $abc$8517$new_n334_ inst[31] $abc$8517$new_n324_ rs2_data[20] $abc$8517$new_n333_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[20] $abc$8517$new_n300_ $abc$8517$new_n334_ +11 1 +.names rs1_data[20] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n335_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n339_ $abc$8517$new_n337_ $abc$8517$new_n336_ +01 1 +10 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[16] inst[31] inst[16] $abc$8517$new_n337_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n300_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n338_ +000 1 +001 1 +010 1 +.names rs1_data[16] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[16] $abc$8517$new_n339_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n369_ $abc$8517$new_n341_ $abc$8517$new_n367_ $abc$8517$new_n365_ $abc$8517$new_n351_ $abc$8517$new_n340_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n341_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n342_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n344_ $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n343_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[5] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[5] $abc$8517$new_n344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[4] $abc$8517$new_n346_ inst[11] inst[24] $abc$8517$new_n347_ $abc$8517$new_n345_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n346_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n348_ $abc$8517$new_n349_ $abc$8517$new_n347_ +0000 1 +0001 1 +0010 1 +.names inst[1] inst[0] inst[2] inst[3] $abc$8517$new_n348_ +1100 1 +.names inst[6] inst[5] $abc$8517$new_n349_ +00 1 +.names rs1_data[4] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[4] $abc$8517$new_n350_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n359_ $abc$8517$new_n363_ $abc$8517$new_n356_ $abc$8517$new_n352_ $abc$8517$new_n351_ +000000 1 +000100 1 +000101 1 +000110 1 +110000 1 +110100 1 +110101 1 +110110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n353_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n352_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names rs1_data[0] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n353_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names inst[7] $abc$8517$new_n311_ inst[5] inst[6] inst[4] $abc$8517$new_n354_ +11100 1 +.names inst[20] $abc$8517$new_n303_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n355_ +100010 1 +100110 1 +101010 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ rs2_data[1] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n356_ +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names inst[8] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n357_ +111000 1 +111001 1 +111010 1 +.names inst[21] $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n358_ +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n361_ $abc$8517$new_n310_ $abc$8517$new_n360_ inst[23] $abc$8517$new_n347_ rs2_data[3] $abc$8517$new_n359_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[10] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n360_ +111000 1 +111001 1 +111010 1 +.names rs1_data[3] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n361_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[2] $abc$8517$new_n346_ inst[9] inst[22] $abc$8517$new_n347_ $abc$8517$new_n362_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names rs1_data[1] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n363_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[2] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n364_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n366_ $abc$8517$new_n365_ +100 1 +.names $abc$8517$new_n310_ $abc$8517$new_n361_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n366_ +000000 1 +000010 1 +000011 1 +000100 1 +000110 1 +000111 1 +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names $abc$8517$new_n343_ $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n361_ $abc$8517$new_n368_ $abc$8517$new_n367_ +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n368_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n370_ $abc$8517$new_n372_ $abc$8517$new_n373_ $abc$8517$new_n369_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n371_ $abc$8517$new_n310_ rs2_data[7] inst[27] $abc$8517$new_n324_ $abc$8517$new_n370_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[7] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n371_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n372_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[6] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n373_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n375_ $abc$8517$new_n381_ $abc$8517$new_n829_ $abc$8517$new_n402_ $abc$8517$new_n395_ $abc$8517$new_n387_ $abc$8517$new_n374_ +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n376_ $abc$8517$new_n377_ $abc$8517$new_n375_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[14] inst[31] inst[14] $abc$8517$new_n376_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n379_ $abc$8517$new_n310_ $abc$8517$new_n378_ inst[31] $abc$8517$new_n312_ rs2_data[15] $abc$8517$new_n377_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[15] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n378_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[15] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n379_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[14] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[14] $abc$8517$new_n380_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n386_ $abc$8517$new_n385_ $abc$8517$new_n382_ $abc$8517$new_n381_ +000 1 +110 1 +.names $abc$8517$new_n384_ $abc$8517$new_n310_ $abc$8517$new_n383_ inst[31] $abc$8517$new_n312_ rs2_data[13] $abc$8517$new_n382_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[13] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n383_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[13] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n384_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[12] inst[31] inst[12] $abc$8517$new_n385_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[12] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n386_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n394_ $abc$8517$new_n388_ $abc$8517$new_n392_ $abc$8517$new_n387_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n389_ rs2_data[11] $abc$8517$new_n390_ inst[31] $abc$8517$new_n388_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n313_ inst[3] inst[2] inst[5] inst[6] inst[4] $abc$8517$new_n389_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +101001 1 +101010 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[20] inst[3] $abc$8517$new_n302_ $abc$8517$new_n390_ +111 1 +.names inst[7] inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n391_ +11110 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ inst[30] $abc$8517$new_n324_ rs2_data[10] $abc$8517$new_n392_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names rs1_data[10] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[10] $abc$8517$new_n393_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[11] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[11] $abc$8517$new_n394_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n399_ $abc$8517$new_n398_ $abc$8517$new_n397_ $abc$8517$new_n396_ $abc$8517$new_n395_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ rs2_data[9] inst[29] $abc$8517$new_n324_ $abc$8517$new_n396_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n310_ rs2_data[8] inst[28] $abc$8517$new_n324_ $abc$8517$new_n397_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[9] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[9] $abc$8517$new_n398_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[8] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n399_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n383_ rs2_data[13] $abc$8517$new_n312_ inst[31] $abc$8517$new_n401_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n394_ $abc$8517$new_n403_ $abc$8517$new_n388_ $abc$8517$new_n402_ +010 1 +100 1 +110 1 +111 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ rs2_data[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n403_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n405_ $abc$8517$new_n387_ $abc$8517$new_n381_ $abc$8517$new_n375_ $abc$8517$new_n404_ +1111 1 +.names $abc$8517$new_n399_ $abc$8517$new_n397_ $abc$8517$new_n406_ $abc$8517$new_n405_ +000 1 +110 1 +.names $abc$8517$new_n398_ $abc$8517$new_n310_ inst[29] $abc$8517$new_n324_ rs2_data[9] $abc$8517$new_n406_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n379_ $abc$8517$new_n376_ $abc$8517$new_n408_ $abc$8517$new_n407_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n378_ rs2_data[15] $abc$8517$new_n312_ inst[31] $abc$8517$new_n408_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n371_ $abc$8517$new_n410_ inst[27] $abc$8517$new_n324_ rs2_data[7] $abc$8517$new_n409_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +011111 1 +100000 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n373_ rs2_data[6] $abc$8517$new_n324_ inst[26] $abc$8517$new_n410_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n326_ $abc$8517$new_n428_ $abc$8517$new_n1347_ $abc$8517$new_n426_ $abc$8517$new_n411_ +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1101 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n413_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n328_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n414_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n418_ $abc$8517$new_n335_ $abc$8517$new_n332_ $abc$8517$new_n416_ $abc$8517$new_n415_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n331_ rs2_data[21] $abc$8517$new_n324_ inst[31] $abc$8517$new_n416_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n334_ rs2_data[20] $abc$8517$new_n324_ inst[31] $abc$8517$new_n418_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n339_ $abc$8517$new_n321_ $abc$8517$new_n337_ $abc$8517$new_n420_ $abc$8517$new_n419_ +000100 1 +000110 1 +001000 1 +001100 1 +001101 1 +001110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n320_ rs2_data[17] $abc$8517$new_n312_ inst[31] $abc$8517$new_n420_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n314_ rs2_data[19] $abc$8517$new_n312_ inst[31] $abc$8517$new_n422_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n317_ rs2_data[18] $abc$8517$new_n312_ inst[31] $abc$8517$new_n423_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n427_ rs2_data[23] $abc$8517$new_n426_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n325_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n427_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n329_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n428_ +0010 1 +0011 1 +1000 1 +1010 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[30] inst[31] inst[30] $abc$8517$new_n431_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[30] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[30] $abc$8517$new_n432_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n434_ $abc$8517$new_n310_ inst[31] rs2_data[31] $abc$8517$new_n433_ +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names rs1_data[31] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n434_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n440_ $abc$8517$new_n438_ $abc$8517$new_n437_ $abc$8517$new_n436_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[29] inst[31] inst[29] $abc$8517$new_n437_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n439_ rs2_data[28] $abc$8517$new_n324_ inst[31] $abc$8517$new_n438_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[28] $abc$8517$new_n300_ $abc$8517$new_n439_ +11 1 +.names rs1_data[29] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n440_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[28] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[28] $abc$8517$new_n441_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n443_ $abc$8517$new_n442_ +000 1 +110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n310_ $abc$8517$new_n439_ inst[31] $abc$8517$new_n324_ rs2_data[28] $abc$8517$new_n443_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n449_ $abc$8517$new_n447_ $abc$8517$new_n445_ $abc$8517$new_n444_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n446_ rs2_data[27] $abc$8517$new_n324_ inst[31] $abc$8517$new_n445_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[27] $abc$8517$new_n300_ $abc$8517$new_n446_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n448_ rs2_data[26] $abc$8517$new_n324_ inst[31] $abc$8517$new_n447_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[26] $abc$8517$new_n300_ $abc$8517$new_n448_ +11 1 +.names rs1_data[27] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n449_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[26] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[26] $abc$8517$new_n450_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n453_ $abc$8517$new_n452_ $abc$8517$new_n451_ +00 1 +.names $abc$8517$new_n449_ $abc$8517$new_n310_ $abc$8517$new_n446_ inst[31] $abc$8517$new_n324_ rs2_data[27] $abc$8517$new_n452_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n310_ $abc$8517$new_n448_ inst[31] $abc$8517$new_n324_ rs2_data[26] $abc$8517$new_n453_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n460_ $abc$8517$new_n459_ $abc$8517$new_n457_ $abc$8517$new_n455_ $abc$8517$new_n454_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n456_ rs2_data[25] $abc$8517$new_n324_ inst[31] $abc$8517$new_n455_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[25] $abc$8517$new_n300_ $abc$8517$new_n456_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n458_ rs2_data[24] $abc$8517$new_n324_ inst[31] $abc$8517$new_n457_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[24] $abc$8517$new_n300_ $abc$8517$new_n458_ +11 1 +.names rs1_data[25] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n459_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[24] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[24] $abc$8517$new_n460_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n462_ $abc$8517$new_n442_ $abc$8517$new_n461_ +11 1 +.names $abc$8517$new_n464_ $abc$8517$new_n463_ $abc$8517$new_n453_ $abc$8517$new_n452_ $abc$8517$new_n462_ +0000 1 +.names $abc$8517$new_n459_ $abc$8517$new_n310_ $abc$8517$new_n456_ inst[31] $abc$8517$new_n324_ rs2_data[25] $abc$8517$new_n463_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n460_ $abc$8517$new_n310_ $abc$8517$new_n458_ inst[31] $abc$8517$new_n324_ rs2_data[24] $abc$8517$new_n464_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n478_ $abc$8517$new_n489_ $abc$8517$new_n467_ $abc$8517$new_n466_ +100 1 +.names $abc$8517$new_n476_ $abc$8517$new_n470_ $abc$8517$new_n468_ $abc$8517$new_n404_ $abc$8517$new_n467_ +1111 1 +.names $abc$8517$new_n469_ $abc$8517$new_n442_ $abc$8517$new_n322_ $abc$8517$new_n308_ $abc$8517$new_n462_ $abc$8517$new_n336_ $abc$8517$new_n468_ +111110 1 +.names $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n433_ $abc$8517$new_n469_ +000 1 +110 1 +.names $abc$8517$new_n474_ $abc$8517$new_n472_ $abc$8517$new_n359_ $abc$8517$new_n352_ $abc$8517$new_n471_ $abc$8517$new_n470_ +11000 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n471_ +01 1 +10 1 +.names $abc$8517$new_n363_ $abc$8517$new_n356_ $abc$8517$new_n473_ $abc$8517$new_n472_ +000 1 +110 1 +.names $abc$8517$new_n353_ $abc$8517$new_n310_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n473_ +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n373_ $abc$8517$new_n372_ $abc$8517$new_n475_ $abc$8517$new_n474_ +000 1 +110 1 +.names $abc$8517$new_n371_ $abc$8517$new_n310_ inst[27] $abc$8517$new_n324_ rs2_data[7] $abc$8517$new_n475_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n350_ $abc$8517$new_n345_ $abc$8517$new_n477_ $abc$8517$new_n476_ +000 1 +110 1 +.names $abc$8517$new_n344_ $abc$8517$new_n310_ inst[25] $abc$8517$new_n324_ rs2_data[5] $abc$8517$new_n477_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n486_ $abc$8517$new_n479_ $abc$8517$new_n478_ +00 1 +.names $abc$8517$new_n481_ $abc$8517$new_n484_ $abc$8517$new_n482_ $abc$8517$new_n485_ $abc$8517$new_n310_ $abc$8517$new_n479_ +00001 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8517$new_n311_ inst[2] inst[4] inst[5] inst[6] $abc$8517$new_n302_ $abc$8517$new_n481_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100010 1 +101000 1 +101010 1 +101110 1 +110000 1 +110010 1 +110100 1 +110110 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n301_ $abc$8517$new_n483_ $abc$8517$new_n482_ +10 1 +.names inst[30] inst[12] inst[13] $abc$8517$new_n483_ +100 1 +101 1 +111 1 +.names inst[5] $abc$8517$new_n348_ inst[14] inst[4] inst[13] $abc$8517$new_n484_ +11100 1 +.names inst[12] inst[14] inst[13] inst[30] $abc$8517$new_n485_ +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$8517$new_n487_ $abc$8517$new_n481_ $abc$8517$new_n488_ $abc$8517$new_n301_ $abc$8517$new_n483_ $abc$8517$new_n486_ +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names inst[6] inst[5] $abc$8517$new_n348_ inst[4] inst[13] inst[14] $abc$8517$new_n487_ +111000 1 +111001 1 +111010 1 +.names inst[13] inst[12] inst[14] $abc$8517$new_n488_ +010 1 +100 1 +101 1 +111 1 +.names $abc$8517$new_n487_ inst[14] inst[12] inst[13] $abc$8517$new_n482_ $abc$8517$new_n481_ $abc$8517$new_n489_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n469_ $abc$8517$new_n442_ $abc$8517$new_n436_ $abc$8517$new_n444_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n492_ +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n434_ $abc$8517$new_n310_ $abc$8517$new_n494_ rs2_data[31] $abc$8517$new_n493_ +1000 1 +1001 1 +1101 1 +1111 1 +.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n338_ $abc$8517$new_n494_ +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n496_ $abc$8517$new_n470_ $abc$8517$new_n468_ $abc$8517$new_n404_ $abc$8517$new_n476_ $abc$8517$new_n495_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n479_ $abc$8517$new_n486_ $abc$8517$new_n497_ $abc$8517$new_n496_ +110 1 +.names $abc$8517$new_n482_ $abc$8517$new_n481_ inst[14] inst[12] inst[13] $abc$8517$new_n498_ $abc$8517$new_n497_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +011100 1 +011101 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +111100 1 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$abc$8517$new_n819_ $abc$8517$new_n766_ $abc$8517$new_n965_ +10000 1 +10001 1 +10011 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n874_ $abc$8517$new_n923_ $abc$8517$new_n967_ $abc$8517$new_n966_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n356_ $abc$8517$new_n944_ $abc$8517$new_n537_ $abc$8517$new_n535_ $abc$8517$new_n967_ +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$8517$new_n441_ $abc$8517$new_n576_ $abc$8517$new_n438_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n968_ +00000 1 +00010 1 +00100 1 +00101 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n692_ $abc$8517$new_n719_ $abc$8517$new_n630_ $abc$8517$new_n629_ $abc$8517$new_n718_ $abc$8517$new_n969_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 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$abc$8517$new_n974_ +10 1 +.names $abc$8517$new_n543_ $abc$8517$new_n976_ $abc$8517$new_n777_ $abc$8517$new_n819_ $abc$8517$new_n886_ $abc$8517$new_n368_ $abc$8517$new_n975_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +101010 1 +101110 1 +110000 1 +110001 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n934_ $abc$8517$new_n958_ $abc$8517$new_n977_ $abc$8517$new_n976_ +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110010 1 +110011 1 +110110 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n563_ $abc$8517$new_n519_ $abc$8517$new_n440_ $abc$8517$new_n977_ +000 1 +001 1 +011 1 +.names $abc$8517$new_n811_ $abc$8517$new_n440_ $abc$8517$new_n576_ $abc$8517$new_n437_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n978_ +000000 1 +000010 1 +000100 1 +000101 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n345_ $abc$8517$new_n692_ $abc$8517$new_n718_ $abc$8517$new_n651_ $abc$8517$new_n719_ $abc$8517$new_n652_ $abc$8517$new_n979_ +100010 1 +100110 1 +101010 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n983_ $abc$8517$new_n546_ $abc$8517$new_n981_ bus_address[30] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n982_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n962_ $abc$8517$new_n981_ +000110 1 +000111 1 +001011 1 +001101 1 +001110 1 +001111 1 +010011 1 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$abc$8517$new_n986_ $abc$8517$new_n985_ +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n539_ $abc$8517$new_n538_ $abc$8517$new_n535_ $abc$8517$new_n537_ $abc$8517$new_n986_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n988_ $abc$8517$new_n789_ $abc$8517$new_n819_ $abc$8517$new_n345_ $abc$8517$new_n795_ $abc$8517$new_n987_ +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n811_ $abc$8517$new_n432_ $abc$8517$new_n576_ $abc$8517$new_n431_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n988_ +000000 1 +000010 1 +000100 1 +000101 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n546_ $abc$8517$new_n433_ $abc$8517$new_n990_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n991_ bus_address[31] +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n982_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n962_ $abc$8517$new_n990_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001010 1 +001100 1 +010000 1 +010001 1 +010010 1 +010100 1 +011000 1 +011001 1 +.names $abc$8517$new_n992_ $abc$8517$new_n433_ $abc$8517$new_n431_ $abc$8517$new_n432_ $abc$8517$new_n984_ $abc$8517$new_n548_ $abc$8517$new_n991_ +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n996_ $abc$8517$new_n997_ $abc$8517$new_n995_ $abc$8517$new_n993_ $abc$8517$new_n803_ $abc$8517$new_n819_ $abc$8517$new_n992_ +100000 1 +100010 1 +100011 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n994_ $abc$8517$new_n910_ $abc$8517$new_n957_ $abc$8517$new_n362_ $abc$8517$new_n993_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n519_ $abc$8517$new_n977_ $abc$8517$new_n434_ $abc$8517$new_n432_ $abc$8517$new_n994_ +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n434_ $abc$8517$new_n576_ rs2_data[31] $abc$8517$new_n494_ $abc$8517$new_n547_ $abc$8517$new_n995_ +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010101 1 +011000 1 +011001 1 +011100 1 +011101 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110101 1 +110111 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n434_ $abc$8517$new_n579_ $abc$8517$new_n310_ $abc$8517$new_n568_ $abc$8517$new_n494_ rs2_data[31] $abc$8517$new_n996_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010010 1 +010011 1 +011000 1 +011010 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n690_ $abc$8517$new_n608_ $abc$8517$new_n549_ $abc$8517$new_n997_ +1111 1 +.names singlecycle_datapath.program_counter.value[0] reset $abc$8517$new_n1013_ $abc$8517$new_n1011_ $abc$8517$new_n999_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] +00000 1 +00001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n302_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n999_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names $abc$8517$new_n1001_ $abc$8517$new_n983_ bus_address[29] bus_address[28] $abc$8517$new_n981_ $abc$8517$new_n546_ $abc$8517$new_n1000_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n1396_ $abc$8517$new_n1002_ $abc$8517$new_n950_ bus_address[26] bus_address[25] $abc$8517$new_n1001_ +11000 1 +.names $abc$8517$new_n1003_ $abc$8517$new_n1007_ bus_address[21] bus_address[24] bus_address[23] bus_address[22] $abc$8517$new_n1002_ +110000 1 +.names $abc$8517$new_n1004_ bus_address[11] bus_address[14] bus_address[16] bus_address[20] $abc$8517$new_n1003_ +10000 1 +.names $abc$8517$new_n1005_ $abc$8517$new_n1006_ bus_address[9] bus_address[10] $abc$8517$new_n1004_ +1100 1 +.names $abc$8517$new_n1352_ $abc$8517$new_n1349_ bus_address[1] $abc$8517$new_n1344_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1005_ +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +.names bus_address[2] bus_address[8] bus_address[7] bus_address[5] bus_address[4] bus_address[3] $abc$8517$new_n1006_ +000000 1 +.names $abc$8517$new_n1008_ bus_address[12] bus_address[19] $abc$8517$new_n1007_ +100 1 +.names bus_address[6] bus_address[13] bus_address[15] bus_address[18] bus_address[17] $abc$8517$new_n1008_ +00000 1 +.names inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n1009_ +1110 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1010_ +100 1 +101 1 +111 1 +.names $abc$8517$new_n1012_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n1011_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names inst[3] $abc$8517$new_n302_ $abc$8517$new_n1012_ +11 1 +.names $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n1013_ +00 1 +.names reset $abc$8517$new_n1015_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n999_ $abc$8517$new_n1017_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[1] $abc$8517$new_n1015_ +11 1 +.names $abc$8517$new_n302_ inst[3] $abc$8517$new_n1016_ +10 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.program_counter.value[0] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n1013_ $abc$8517$new_n1017_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names reset $abc$8517$new_n1019_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n999_ $abc$8517$new_n1020_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001010 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[2] $abc$8517$new_n1019_ +11 1 +.names singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1020_ +001 1 +010 1 +100 1 +111 1 +.names inst[9] $abc$8517$new_n346_ inst[22] $abc$8517$new_n347_ $abc$8517$new_n1021_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n358_ $abc$8517$new_n357_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n354_ $abc$8517$new_n355_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n1022_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +.names reset $abc$8517$new_n1024_ $abc$8517$new_n1028_ $abc$8517$new_n999_ $abc$8517$new_n1025_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[3] $abc$8517$new_n1024_ +11 1 +.names singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1025_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1022_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1021_ $abc$8517$new_n1026_ +001 1 +100 1 +101 1 +111 1 +.names $abc$8517$new_n360_ $abc$8517$new_n347_ inst[23] $abc$8517$new_n1027_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1028_ +01 1 +10 1 +.names reset $abc$8517$new_n1030_ $abc$8517$new_n1033_ $abc$8517$new_n999_ $abc$8517$new_n1031_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[4] $abc$8517$new_n1030_ +11 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1031_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[11] $abc$8517$new_n346_ inst[24] $abc$8517$new_n347_ $abc$8517$new_n1032_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1033_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1035_ $abc$8517$new_n1042_ $abc$8517$new_n999_ $abc$8517$new_n1036_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[5] $abc$8517$new_n1035_ +11 1 +.names $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1036_ +00 1 +11 1 +.names $abc$8517$new_n1039_ $abc$8517$new_n1038_ $abc$8517$new_n1037_ +00 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ $abc$8517$new_n1038_ +10 1 +.names $abc$8517$new_n1040_ singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1027_ $abc$8517$new_n1039_ +100000 1 +101000 1 +101010 1 +101100 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n347_ inst[24] inst[11] $abc$8517$new_n1040_ +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n1041_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1042_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1044_ $abc$8517$new_n1048_ $abc$8517$new_n999_ $abc$8517$new_n1045_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[6] $abc$8517$new_n1044_ +11 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1045_ +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names inst[25] singlecycle_datapath.program_counter.value[5] $abc$8517$new_n324_ $abc$8517$new_n1046_ +110 1 +.names singlecycle_datapath.program_counter.value[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n1047_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1048_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1050_ $abc$8517$new_n1054_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[7] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1051_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1050_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1051_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n1041_ $abc$8517$new_n1038_ $abc$8517$new_n1039_ $abc$8517$new_n1052_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1054_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1056_ $abc$8517$new_n1060_ $abc$8517$new_n999_ $abc$8517$new_n1057_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[8] $abc$8517$new_n1056_ +11 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1057_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1058_ +000 1 +001 1 +011 1 +101 1 +.names inst[28] $abc$8517$new_n324_ $abc$8517$new_n1059_ +10 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1060_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1061_ +111111 1 +.names reset $abc$8517$new_n1063_ $abc$8517$new_n1067_ $abc$8517$new_n999_ $abc$8517$new_n1064_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[9] $abc$8517$new_n1063_ +11 1 +.names $abc$8517$new_n1066_ $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1064_ +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names inst[29] singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ $abc$8517$new_n1065_ +110 1 +.names singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ inst[29] $abc$8517$new_n1066_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1067_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1069_ $abc$8517$new_n1073_ $abc$8517$new_n999_ $abc$8517$new_n1070_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[10] $abc$8517$new_n1069_ +11 1 +.names $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1070_ +000 1 +101 1 +110 1 +111 1 +.names $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1052_ $abc$8517$new_n1071_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001011 1 +001101 1 +010000 1 +010001 1 +010011 1 +010101 1 +011000 1 +011001 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1072_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1073_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1075_ $abc$8517$new_n1079_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[11] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1076_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1075_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1078_ $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1076_ +000100 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +110100 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n390_ $abc$8517$new_n391_ $abc$8517$new_n389_ inst[31] $abc$8517$new_n1077_ +0000 1 +0010 1 +0011 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1078_ +110 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1079_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1081_ $abc$8517$new_n1086_ $abc$8517$new_n999_ $abc$8517$new_n1082_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[12] $abc$8517$new_n1081_ +11 1 +.names singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1084_ $abc$8517$new_n1083_ $abc$8517$new_n1082_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1072_ $abc$8517$new_n1071_ $abc$8517$new_n1066_ $abc$8517$new_n1078_ $abc$8517$new_n1083_ +000001 1 +000011 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001101 1 +001111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[12] $abc$8517$new_n1084_ +000 1 +010 1 +011 1 +.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n1085_ +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1086_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1091_ $abc$8517$new_n1092_ $abc$8517$new_n999_ $abc$8517$new_n1088_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1088_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1084_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1083_ $abc$8517$new_n1089_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n383_ $abc$8517$new_n1085_ $abc$8517$new_n1090_ +00 1 +.names $abc$8517$new_n1016_ bus_address[13] $abc$8517$new_n1091_ +11 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1092_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1093_ +111111 1 +.names reset $abc$8517$new_n1095_ $abc$8517$new_n1098_ $abc$8517$new_n999_ $abc$8517$new_n1096_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[14] $abc$8517$new_n1095_ +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1096_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[14] $abc$8517$new_n1097_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1098_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1106_ $abc$8517$new_n1107_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1100_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1100_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ $abc$8517$new_n1101_ +00 1 +.names $abc$8517$new_n1103_ singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1084_ $abc$8517$new_n1090_ $abc$8517$new_n1083_ $abc$8517$new_n1102_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1103_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1104_ +10 1 +.names $abc$8517$new_n378_ $abc$8517$new_n1085_ $abc$8517$new_n1105_ +00 1 +.names $abc$8517$new_n1016_ bus_address[15] $abc$8517$new_n1106_ +11 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1107_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1109_ $abc$8517$new_n1112_ $abc$8517$new_n999_ $abc$8517$new_n1110_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[16] $abc$8517$new_n1109_ +11 1 +.names singlecycle_datapath.program_counter.value[16] $abc$8517$new_n1111_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1110_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[16] $abc$8517$new_n1111_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1112_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1114_ $abc$8517$new_n1118_ $abc$8517$new_n999_ bus_address[17] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1115_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1114_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1115_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1111_ $abc$8517$new_n1116_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n320_ $abc$8517$new_n1085_ $abc$8517$new_n1117_ +00 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1118_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1123_ $abc$8517$new_n1124_ $abc$8517$new_n999_ $abc$8517$new_n1120_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1120_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1121_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n317_ $abc$8517$new_n1085_ $abc$8517$new_n1122_ +00 1 +.names $abc$8517$new_n1016_ bus_address[18] $abc$8517$new_n1123_ +11 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1124_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1125_ +111111 1 +.names reset $abc$8517$new_n1129_ $abc$8517$new_n1130_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1127_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1127_ +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n314_ $abc$8517$new_n1085_ $abc$8517$new_n1128_ +00 1 +.names $abc$8517$new_n1016_ bus_address[19] $abc$8517$new_n1129_ +11 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1130_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1132_ $abc$8517$new_n1138_ $abc$8517$new_n999_ $abc$8517$new_n1133_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[20] $abc$8517$new_n1132_ +11 1 +.names singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1133_ +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n1135_ $abc$8517$new_n1117_ singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1116_ $abc$8517$new_n1134_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ $abc$8517$new_n1135_ +10 1 +.names $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1136_ +10 1 +.names $abc$8517$new_n334_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1137_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1138_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1140_ $abc$8517$new_n1143_ $abc$8517$new_n999_ $abc$8517$new_n1141_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[21] $abc$8517$new_n1140_ +11 1 +.names singlecycle_datapath.program_counter.value[21] $abc$8517$new_n1142_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1141_ +000000 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101101 1 +101110 1 +101111 1 +110000 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +.names $abc$8517$new_n331_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1142_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1143_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1145_ $abc$8517$new_n1146_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names reset bus_address[22] $abc$8517$new_n1016_ $abc$8517$new_n1145_ +000 1 +001 1 +010 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n414_ $abc$8517$new_n1147_ $abc$8517$new_n1146_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1137_ $abc$8517$new_n1142_ $abc$8517$new_n1147_ +000000 1 +010000 1 +010010 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101010 1 +101100 1 +101110 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +111000 1 +111001 1 +111010 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1148_ +11111 1 +.names reset $abc$8517$new_n1152_ $abc$8517$new_n1153_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1150_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1150_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n414_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1147_ $abc$8517$new_n1151_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n1016_ bus_address[23] $abc$8517$new_n1152_ +11 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1153_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1154_ +11 1 +.names reset $abc$8517$new_n1158_ $abc$8517$new_n1159_ $abc$8517$new_n999_ $abc$8517$new_n1156_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1156_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n458_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1157_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[24] $abc$8517$new_n1158_ +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1159_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1160_ +11 1 +.names reset $abc$8517$new_n1168_ $abc$8517$new_n1169_ $abc$8517$new_n999_ $abc$8517$new_n1162_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1162_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ $abc$8517$new_n1163_ +00 1 +.names $abc$8517$new_n1165_ singlecycle_datapath.program_counter.value[22] singlecycle_datapath.program_counter.value[23] $abc$8517$new_n414_ $abc$8517$new_n427_ $abc$8517$new_n1147_ $abc$8517$new_n1164_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1165_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1166_ +10 1 +.names $abc$8517$new_n456_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1167_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[25] $abc$8517$new_n1168_ +11 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1169_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1173_ $abc$8517$new_n1174_ $abc$8517$new_n999_ $abc$8517$new_n1171_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[26] $abc$8517$new_n1172_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1171_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n448_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1172_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[26] $abc$8517$new_n1173_ +11 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1174_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1176_ $abc$8517$new_n1180_ $abc$8517$new_n999_ $abc$8517$new_n1177_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[27] $abc$8517$new_n1176_ +11 1 +.names singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1177_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1172_ $abc$8517$new_n1178_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n446_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1179_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1180_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1182_ $abc$8517$new_n1185_ $abc$8517$new_n999_ bus_address[28] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1183_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1182_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1183_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n439_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1184_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1185_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1190_ $abc$8517$new_n1191_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1187_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1187_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1179_ singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ $abc$8517$new_n1178_ $abc$8517$new_n1188_ +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[29] $abc$8517$new_n1189_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n1016_ bus_address[29] $abc$8517$new_n1190_ +11 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1191_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1192_ +111111 1 +.names reset $abc$8517$new_n1194_ $abc$8517$new_n1197_ $abc$8517$new_n999_ $abc$8517$new_n1195_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[30] $abc$8517$new_n1194_ +11 1 +.names singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1195_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[30] $abc$8517$new_n1196_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1197_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ $abc$8517$new_n1199_ $abc$8517$new_n1202_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001010 1 +001011 1 +001101 1 +001110 1 +001111 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1200_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1199_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n1201_ $abc$8517$new_n1189_ singlecycle_datapath.program_counter.value[29] singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ $abc$8517$new_n1188_ $abc$8517$new_n1200_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101100 1 +101101 1 +101110 1 +101111 1 +110100 1 +110101 1 +111000 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[31] $abc$8517$new_n494_ $abc$8517$new_n1201_ +00 1 +11 1 +.names $abc$8517$new_n1016_ bus_address[31] $abc$8517$new_n1202_ +11 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1203_ +111 1 +.names $abc$8517$new_n1005_ inst[13] inst[12] bus_byte_enable[0] +100 1 +101 1 +110 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +.names inst[13] inst[12] bus_address[0] bus_address[1] bus_byte_enable[2] +0001 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[3] +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1209_ bus_address[0] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n302_ rd_data[0] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[24] bus_read_data[8] bus_read_data[16] bus_read_data[0] $abc$8517$new_n1209_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n301_ $abc$8517$new_n300_ inst[5] $abc$8517$new_n1210_ +000 1 +001 1 +011 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1212_ bus_address[1] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n302_ rd_data[1] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[25] bus_read_data[9] bus_read_data[17] bus_read_data[1] $abc$8517$new_n1212_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1214_ bus_address[2] $abc$8517$new_n1210_ $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[2] rd_data[2] +000010 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010010 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110010 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names bus_address[1] bus_address[0] bus_read_data[26] bus_read_data[10] bus_read_data[18] bus_read_data[2] $abc$8517$new_n1214_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1216_ bus_address[3] $abc$8517$new_n1210_ $abc$8517$new_n1028_ $abc$8517$new_n302_ rd_data[3] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[27] bus_read_data[11] bus_read_data[19] bus_read_data[3] $abc$8517$new_n1216_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1218_ bus_address[4] $abc$8517$new_n1210_ $abc$8517$new_n1033_ $abc$8517$new_n302_ rd_data[4] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[28] bus_read_data[12] bus_read_data[20] bus_read_data[4] $abc$8517$new_n1218_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1220_ bus_address[5] $abc$8517$new_n1210_ $abc$8517$new_n1042_ $abc$8517$new_n302_ rd_data[5] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[29] bus_read_data[13] bus_read_data[21] bus_read_data[5] $abc$8517$new_n1220_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1222_ bus_address[6] $abc$8517$new_n1210_ $abc$8517$new_n1048_ $abc$8517$new_n302_ rd_data[6] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[30] bus_read_data[14] bus_read_data[22] bus_read_data[6] $abc$8517$new_n1222_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1224_ bus_address[7] $abc$8517$new_n1210_ $abc$8517$new_n1054_ $abc$8517$new_n302_ rd_data[7] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[31] bus_read_data[15] bus_read_data[23] bus_read_data[7] $abc$8517$new_n1224_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1226_ $abc$8517$new_n1210_ bus_address[8] $abc$8517$new_n1060_ $abc$8517$new_n302_ rd_data[8] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1228_ $abc$8517$new_n1227_ $abc$8517$new_n1226_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names inst[13] inst[12] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1227_ +0000 1 +1100 1 +.names bus_address[1] bus_address[0] bus_read_data[16] bus_read_data[24] bus_read_data[8] $abc$8517$new_n1228_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1230_ $abc$8517$new_n1210_ bus_address[9] $abc$8517$new_n1067_ $abc$8517$new_n302_ rd_data[9] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1231_ $abc$8517$new_n1227_ $abc$8517$new_n1230_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[17] bus_read_data[25] bus_read_data[9] $abc$8517$new_n1231_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1233_ $abc$8517$new_n1210_ bus_address[10] $abc$8517$new_n1073_ $abc$8517$new_n302_ rd_data[10] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1234_ $abc$8517$new_n1227_ $abc$8517$new_n1233_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[18] bus_read_data[26] bus_read_data[10] $abc$8517$new_n1234_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1236_ $abc$8517$new_n1210_ bus_address[11] $abc$8517$new_n1079_ $abc$8517$new_n302_ rd_data[11] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1237_ $abc$8517$new_n1227_ $abc$8517$new_n1236_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[19] bus_read_data[27] bus_read_data[11] $abc$8517$new_n1237_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1239_ $abc$8517$new_n302_ $abc$8517$new_n1086_ rd_data[12] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1241_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1240_ $abc$8517$new_n1239_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[20] bus_read_data[28] bus_read_data[12] $abc$8517$new_n1240_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1210_ bus_address[12] $abc$8517$new_n300_ $abc$8517$new_n1084_ $abc$8517$new_n1241_ +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n1243_ bus_address[13] $abc$8517$new_n1210_ rd_data[13] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1245_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1244_ $abc$8517$new_n1243_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[21] bus_read_data[29] bus_read_data[13] $abc$8517$new_n1244_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1092_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1090_ $abc$8517$new_n1245_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1247_ bus_address[14] $abc$8517$new_n1210_ rd_data[14] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1249_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1248_ $abc$8517$new_n1247_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[22] bus_read_data[30] bus_read_data[14] $abc$8517$new_n1248_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1098_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1097_ $abc$8517$new_n1249_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1251_ bus_address[15] $abc$8517$new_n1210_ rd_data[15] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1253_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1252_ $abc$8517$new_n1251_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[23] bus_read_data[31] bus_read_data[15] $abc$8517$new_n1252_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1107_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1105_ $abc$8517$new_n1253_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1255_ bus_address[16] $abc$8517$new_n1210_ rd_data[16] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1256_ $abc$8517$new_n302_ $abc$8517$new_n1112_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1111_ $abc$8517$new_n1255_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[24] bus_read_data[16] $abc$8517$new_n1256_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1252_ $abc$8517$new_n1257_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names inst[13] inst[12] bus_address[1] $abc$8517$new_n1258_ +100 1 +.names $abc$8517$new_n1260_ $abc$8517$new_n302_ $abc$8517$new_n1118_ rd_data[17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1261_ bus_address[17] $abc$8517$new_n1210_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1117_ $abc$8517$new_n1260_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[25] bus_read_data[17] $abc$8517$new_n1261_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1263_ bus_address[18] $abc$8517$new_n1210_ rd_data[18] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1264_ $abc$8517$new_n302_ $abc$8517$new_n1124_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1122_ $abc$8517$new_n1263_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[26] bus_read_data[18] $abc$8517$new_n1264_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1266_ bus_address[19] $abc$8517$new_n1210_ rd_data[19] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1267_ $abc$8517$new_n302_ $abc$8517$new_n1130_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1128_ $abc$8517$new_n1266_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[27] bus_read_data[19] $abc$8517$new_n1267_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1269_ bus_address[20] $abc$8517$new_n1210_ rd_data[20] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1270_ $abc$8517$new_n302_ $abc$8517$new_n1138_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1137_ $abc$8517$new_n1269_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[28] bus_read_data[20] $abc$8517$new_n1270_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1272_ bus_address[21] $abc$8517$new_n1210_ rd_data[21] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1273_ $abc$8517$new_n302_ $abc$8517$new_n1143_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1142_ $abc$8517$new_n1272_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[29] bus_read_data[21] $abc$8517$new_n1273_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1276_ $abc$8517$new_n1275_ bus_address[22] $abc$8517$new_n1210_ rd_data[22] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[30] bus_read_data[22] $abc$8517$new_n1275_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n414_ $abc$8517$new_n1276_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n1278_ bus_address[23] $abc$8517$new_n1210_ rd_data[23] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1279_ $abc$8517$new_n302_ $abc$8517$new_n1153_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n427_ $abc$8517$new_n1278_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[31] bus_read_data[23] $abc$8517$new_n1279_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1281_ bus_address[24] $abc$8517$new_n1210_ rd_data[24] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1283_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[24] $abc$8517$new_n1281_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1282_ +10 1 +.names $abc$8517$new_n1159_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1157_ $abc$8517$new_n1283_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1285_ bus_address[25] $abc$8517$new_n1210_ rd_data[25] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1286_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[25] $abc$8517$new_n1285_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1169_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1167_ $abc$8517$new_n1286_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1288_ bus_address[26] $abc$8517$new_n1210_ rd_data[26] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1289_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[26] $abc$8517$new_n1288_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1174_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1172_ $abc$8517$new_n1289_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1291_ bus_address[27] $abc$8517$new_n1210_ rd_data[27] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1292_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[27] $abc$8517$new_n1291_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1180_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1179_ $abc$8517$new_n1292_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1294_ bus_address[28] $abc$8517$new_n1210_ rd_data[28] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1295_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[28] $abc$8517$new_n1294_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1185_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1184_ $abc$8517$new_n1295_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1297_ bus_address[29] $abc$8517$new_n1210_ rd_data[29] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1298_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[29] $abc$8517$new_n1297_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1191_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1189_ $abc$8517$new_n1298_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1300_ bus_address[30] $abc$8517$new_n1210_ rd_data[30] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1301_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[30] $abc$8517$new_n1300_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1197_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1196_ $abc$8517$new_n1301_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1304_ $abc$8517$new_n1303_ bus_address[31] $abc$8517$new_n1210_ rd_data[31] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1257_ bus_read_data[31] $abc$8517$new_n1282_ $abc$8517$new_n1303_ +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n494_ $abc$8517$new_n1304_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1009_ $abc$8517$new_n348_ $abc$8517$new_n1307_ $abc$8517$new_n1306_ inst[3] bus_write_enable +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names inst[2] $abc$8517$new_n313_ $abc$8517$new_n1306_ +11 1 +.names inst[6] inst[5] inst[4] $abc$8517$new_n1307_ +000 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1306_ $abc$8517$new_n346_ $abc$8517$new_n1310_ bus_read_enable +1010 1 +1011 1 +1100 1 +1110 1 +.names inst[3] $abc$8517$new_n1307_ $abc$8517$new_n1310_ +11 1 +.names rs2_data[0] $abc$8517$new_n1005_ bus_write_data[0] +11 1 +.names rs2_data[1] $abc$8517$new_n1005_ bus_write_data[1] +11 1 +.names rs2_data[2] $abc$8517$new_n1005_ bus_write_data[2] +11 1 +.names rs2_data[3] $abc$8517$new_n1005_ bus_write_data[3] +11 1 +.names rs2_data[4] $abc$8517$new_n1005_ bus_write_data[4] +11 1 +.names rs2_data[5] $abc$8517$new_n1005_ bus_write_data[5] +11 1 +.names rs2_data[6] $abc$8517$new_n1005_ bus_write_data[6] +11 1 +.names rs2_data[7] $abc$8517$new_n1005_ bus_write_data[7] +11 1 +.names bus_address[0] bus_address[1] rs2_data[0] rs2_data[8] bus_write_data[8] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[1] rs2_data[9] bus_write_data[9] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[2] rs2_data[10] bus_write_data[10] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[3] rs2_data[11] bus_write_data[11] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[4] rs2_data[12] bus_write_data[12] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[5] rs2_data[13] bus_write_data[13] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[6] rs2_data[14] bus_write_data[14] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[7] rs2_data[15] bus_write_data[15] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[1] bus_address[0] rs2_data[8] rs2_data[0] rs2_data[16] bus_write_data[16] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[9] rs2_data[1] rs2_data[17] bus_write_data[17] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[10] rs2_data[2] rs2_data[18] bus_write_data[18] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[11] rs2_data[3] rs2_data[19] bus_write_data[19] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[12] rs2_data[4] rs2_data[20] bus_write_data[20] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[13] rs2_data[5] rs2_data[21] bus_write_data[21] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[14] rs2_data[6] rs2_data[22] bus_write_data[22] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[15] rs2_data[7] rs2_data[23] bus_write_data[23] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[0] rs2_data[16] rs2_data[8] rs2_data[24] bus_write_data[24] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[1] rs2_data[17] rs2_data[9] rs2_data[25] bus_write_data[25] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[2] rs2_data[18] rs2_data[10] rs2_data[26] bus_write_data[26] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[3] rs2_data[19] rs2_data[11] rs2_data[27] bus_write_data[27] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[4] rs2_data[20] rs2_data[12] rs2_data[28] bus_write_data[28] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[5] rs2_data[21] rs2_data[13] rs2_data[29] bus_write_data[29] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[6] rs2_data[22] rs2_data[14] rs2_data[30] bus_write_data[30] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[7] rs2_data[23] rs2_data[15] rs2_data[31] bus_write_data[31] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n462_ $abc$8517$new_n444_ $abc$8517$new_n306_ $abc$8517$new_n411_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n1343_ +000011 1 +000111 1 +001011 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n433_ $abc$8517$new_n436_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n442_ $abc$8517$new_n1343_ $abc$8517$new_n1344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +010100 1 +010101 1 +010110 1 +010111 1 +.names $abc$8517$new_n310_ rs2_data[19] $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ $abc$8517$new_n1345_ +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n318_ $abc$8517$new_n315_ $abc$8517$new_n423_ $abc$8517$new_n1345_ $abc$8517$new_n335_ $abc$8517$new_n418_ $abc$8517$new_n1346_ +000000 1 +000001 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +100000 1 +100001 1 +100011 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n1346_ $abc$8517$new_n413_ $abc$8517$new_n419_ $abc$8517$new_n330_ $abc$8517$new_n329_ $abc$8517$new_n415_ $abc$8517$new_n1347_ +000000 1 +000100 1 +001000 1 +001100 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100100 1 +101000 1 +101100 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110110 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n433_ $abc$8517$new_n461_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n411_ $abc$8517$new_n306_ $abc$8517$new_n1348_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +001111 1 +010010 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n495_ $abc$8517$new_n1348_ $abc$8517$new_n493_ $abc$8517$new_n492_ $abc$8517$new_n1349_ +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n479_ $abc$8517$new_n497_ $abc$8517$new_n519_ $abc$8517$new_n353_ $abc$8517$new_n467_ $abc$8517$new_n489_ $abc$8517$new_n1350_ +000000 1 +000001 1 +000010 1 +000011 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 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$abc$8517$new_n571_ $abc$8517$new_n574_ $abc$8517$new_n572_ $abc$8517$new_n1353_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n575_ $abc$8517$new_n578_ $abc$8517$new_n345_ $abc$8517$new_n554_ $abc$8517$new_n1353_ $abc$8517$new_n549_ bus_address[1] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 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+11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n659_ $abc$8517$new_n547_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n576_ $abc$8517$new_n579_ $abc$8517$new_n1359_ +000000 1 +000100 1 +000101 1 +001000 1 +001001 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010010 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1359_ $abc$8517$new_n653_ $abc$8517$new_n647_ $abc$8517$new_n646_ $abc$8517$new_n549_ $abc$8517$new_n657_ bus_address[5] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 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$abc$8517$new_n497_ $abc$8517$new_n486_ $abc$8517$new_n399_ $abc$8517$new_n479_ $abc$8517$new_n397_ $abc$8517$new_n489_ $abc$8517$new_n1368_ +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +001111 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n712_ $abc$8517$new_n1368_ $abc$8517$new_n497_ $abc$8517$new_n701_ $abc$8517$new_n548_ $abc$8517$new_n711_ $abc$8517$new_n1369_ +001000 1 +001001 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010101 1 +010110 1 +011100 1 +011101 1 +011110 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n571_ $abc$8517$new_n556_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n1371_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n724_ $abc$8517$new_n720_ $abc$8517$new_n717_ $abc$8517$new_n549_ $abc$8517$new_n1371_ $abc$8517$new_n345_ $abc$8517$new_n1372_ +100001 1 +100011 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +.names $abc$8517$new_n1372_ $abc$8517$new_n715_ $abc$8517$new_n406_ $abc$8517$new_n714_ $abc$8517$new_n709_ $abc$8517$new_n546_ bus_address[9] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 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$abc$8517$new_n1375_ $abc$8517$new_n746_ $abc$8517$new_n1374_ $abc$8517$new_n549_ $abc$8517$new_n1376_ +1000 1 +1001 1 +1010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n521_ $abc$8517$new_n531_ $abc$8517$new_n1377_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n768_ $abc$8517$new_n772_ $abc$8517$new_n770_ $abc$8517$new_n769_ $abc$8517$new_n711_ $abc$8517$new_n548_ $abc$8517$new_n1378_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101010 1 +101100 1 +101101 1 +101110 1 +110000 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n1378_ $abc$8517$new_n763_ $abc$8517$new_n766_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1377_ $abc$8517$new_n1379_ +100000 1 +100001 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n556_ $abc$8517$new_n649_ $abc$8517$new_n1380_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n782_ $abc$8517$new_n781_ $abc$8517$new_n777_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1380_ $abc$8517$new_n1381_ +100000 1 +100001 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101110 1 +.names $abc$8517$new_n1381_ $abc$8517$new_n382_ $abc$8517$new_n783_ $abc$8517$new_n775_ $abc$8517$new_n548_ $abc$8517$new_n1382_ +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n345_ $abc$8517$new_n362_ $abc$8517$new_n837_ $abc$8517$new_n838_ $abc$8517$new_n778_ $abc$8517$new_n1383_ +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names $abc$8517$new_n1383_ $abc$8517$new_n820_ $abc$8517$new_n345_ $abc$8517$new_n840_ $abc$8517$new_n554_ $abc$8517$new_n581_ $abc$8517$new_n1384_ +000100 1 +000101 1 +000110 1 +000111 1 +001110 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +011111 1 +100100 1 +100101 1 +100110 1 +100111 1 +101110 1 +101111 1 +110100 1 +110110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n820_ $abc$8517$new_n588_ $abc$8517$new_n345_ $abc$8517$new_n734_ $abc$8517$new_n850_ $abc$8517$new_n1385_ +000100 1 +000101 1 +000110 1 +000111 1 +010110 1 +010111 1 +100100 1 +100101 1 +100110 1 +100111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names $abc$8517$new_n853_ $abc$8517$new_n345_ $abc$8517$new_n845_ $abc$8517$new_n1385_ $abc$8517$new_n600_ $abc$8517$new_n583_ $abc$8517$new_n1386_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +110100 1 +110110 1 +.names $abc$8517$new_n546_ $abc$8517$new_n843_ $abc$8517$new_n316_ $abc$8517$new_n1386_ bus_address[18] +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n874_ $abc$8517$new_n819_ $abc$8517$new_n634_ $abc$8517$new_n877_ $abc$8517$new_n1388_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010011 1 +010101 1 +010111 1 +011001 1 +011011 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1388_ $abc$8517$new_n878_ $abc$8517$new_n879_ $abc$8517$new_n869_ $abc$8517$new_n333_ $abc$8517$new_n548_ $abc$8517$new_n1389_ +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +110111 1 +.names $abc$8517$new_n413_ $abc$8517$new_n329_ $abc$8517$new_n497_ $abc$8517$new_n552_ $abc$8517$new_n547_ $abc$8517$new_n478_ $abc$8517$new_n1390_ +000000 1 +000010 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +011000 1 +011001 1 +011100 1 +011101 1 +100000 1 +100001 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1390_ $abc$8517$new_n901_ $abc$8517$new_n897_ $abc$8517$new_n896_ $abc$8517$new_n894_ $abc$8517$new_n811_ bus_address[22] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n345_ $abc$8517$new_n717_ $abc$8517$new_n933_ $abc$8517$new_n543_ $abc$8517$new_n568_ $abc$8517$new_n434_ $abc$8517$new_n1392_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +110000 1 +110001 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n936_ $abc$8517$new_n1392_ $abc$8517$new_n932_ $abc$8517$new_n929_ $abc$8517$new_n546_ $abc$8517$new_n927_ bus_address[25] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n820_ $abc$8517$new_n368_ $abc$8517$new_n863_ $abc$8517$new_n362_ $abc$8517$new_n612_ $abc$8517$new_n1394_ +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n345_ $abc$8517$new_n748_ $abc$8517$new_n692_ $abc$8517$new_n1394_ $abc$8517$new_n719_ $abc$8517$new_n747_ $abc$8517$new_n1395_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100111 1 +.names $abc$8517$new_n959_ $abc$8517$new_n1395_ $abc$8517$new_n956_ $abc$8517$new_n811_ $abc$8517$new_n548_ $abc$8517$new_n952_ $abc$8517$new_n1396_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n623_ $abc$8517$new_n620_ $abc$8517$new_n624_ $abc$8517$new_n621_ $abc$8517$new_n1397_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1355_ $abc$8517$new_n603_ $abc$8517$new_n1397_ $abc$8517$new_n549_ bus_address[3] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n503_ $abc$8517$new_n521_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n1399_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1369_ $abc$8517$new_n707_ $abc$8517$new_n703_ $abc$8517$new_n1399_ $abc$8517$new_n549_ bus_address[8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] singlecycle_datapath.program_counter.value[0] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] singlecycle_datapath.program_counter.value[1] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] singlecycle_datapath.program_counter.value[2] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] singlecycle_datapath.program_counter.value[3] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] singlecycle_datapath.program_counter.value[4] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] singlecycle_datapath.program_counter.value[5] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] singlecycle_datapath.program_counter.value[6] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] singlecycle_datapath.program_counter.value[7] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] singlecycle_datapath.program_counter.value[11] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] singlecycle_datapath.program_counter.value[15] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] singlecycle_datapath.program_counter.value[16] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] singlecycle_datapath.program_counter.value[17] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] singlecycle_datapath.program_counter.value[18] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] singlecycle_datapath.program_counter.value[19] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] singlecycle_datapath.program_counter.value[20] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] singlecycle_datapath.program_counter.value[21] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] singlecycle_datapath.program_counter.value[22] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] singlecycle_datapath.program_counter.value[23] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] singlecycle_datapath.program_counter.value[24] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] singlecycle_datapath.program_counter.value[25] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] singlecycle_datapath.program_counter.value[26] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] singlecycle_datapath.program_counter.value[27] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] singlecycle_datapath.program_counter.value[28] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] singlecycle_datapath.program_counter.value[29] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] singlecycle_datapath.program_counter.value[30] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2 +.names bus_address[0] address[0] +1 1 +.names bus_address[1] address[1] +1 1 +.names bus_address[2] address[2] +1 1 +.names bus_address[3] address[3] +1 1 +.names bus_address[4] address[4] +1 1 +.names bus_address[5] address[5] +1 1 +.names bus_address[6] address[6] +1 1 +.names bus_address[7] address[7] +1 1 +.names bus_address[8] address[8] +1 1 +.names bus_address[9] address[9] +1 1 +.names bus_address[10] address[10] +1 1 +.names bus_address[11] address[11] +1 1 +.names bus_address[12] address[12] +1 1 +.names bus_address[13] address[13] +1 1 +.names bus_address[14] address[14] +1 1 +.names bus_address[15] address[15] +1 1 +.names bus_address[16] address[16] +1 1 +.names bus_address[17] address[17] +1 1 +.names bus_address[18] address[18] +1 1 +.names bus_address[19] address[19] +1 1 +.names bus_address[20] address[20] +1 1 +.names bus_address[21] address[21] +1 1 +.names bus_address[22] address[22] +1 1 +.names bus_address[23] address[23] +1 1 +.names bus_address[24] address[24] +1 1 +.names bus_address[25] address[25] +1 1 +.names bus_address[26] address[26] +1 1 +.names bus_address[27] address[27] +1 1 +.names bus_address[28] address[28] +1 1 +.names bus_address[29] address[29] +1 1 +.names bus_address[30] address[30] +1 1 +.names bus_address[31] address[31] +1 1 +.names $false alu_function[4] +1 1 +.names bus_address[0] data_memory_interface.address[0] +1 1 +.names bus_address[1] data_memory_interface.address[1] +1 1 +.names bus_address[2] data_memory_interface.address[2] +1 1 +.names bus_address[3] data_memory_interface.address[3] +1 1 +.names bus_address[4] data_memory_interface.address[4] +1 1 +.names bus_address[5] data_memory_interface.address[5] +1 1 +.names bus_address[6] data_memory_interface.address[6] +1 1 +.names bus_address[7] data_memory_interface.address[7] +1 1 +.names bus_address[8] data_memory_interface.address[8] +1 1 +.names bus_address[9] data_memory_interface.address[9] +1 1 +.names bus_address[10] data_memory_interface.address[10] +1 1 +.names bus_address[11] data_memory_interface.address[11] +1 1 +.names bus_address[12] data_memory_interface.address[12] +1 1 +.names bus_address[13] data_memory_interface.address[13] +1 1 +.names bus_address[14] data_memory_interface.address[14] +1 1 +.names bus_address[15] data_memory_interface.address[15] +1 1 +.names bus_address[16] data_memory_interface.address[16] +1 1 +.names bus_address[17] data_memory_interface.address[17] +1 1 +.names bus_address[18] data_memory_interface.address[18] +1 1 +.names bus_address[19] data_memory_interface.address[19] +1 1 +.names bus_address[20] data_memory_interface.address[20] +1 1 +.names bus_address[21] data_memory_interface.address[21] +1 1 +.names bus_address[22] data_memory_interface.address[22] +1 1 +.names bus_address[23] data_memory_interface.address[23] +1 1 +.names bus_address[24] data_memory_interface.address[24] +1 1 +.names bus_address[25] data_memory_interface.address[25] +1 1 +.names bus_address[26] data_memory_interface.address[26] +1 1 +.names bus_address[27] data_memory_interface.address[27] +1 1 +.names bus_address[28] data_memory_interface.address[28] +1 1 +.names bus_address[29] data_memory_interface.address[29] +1 1 +.names bus_address[30] data_memory_interface.address[30] +1 1 +.names bus_address[31] data_memory_interface.address[31] +1 1 +.names bus_address[0] data_memory_interface.bus_address[0] +1 1 +.names bus_address[1] data_memory_interface.bus_address[1] +1 1 +.names bus_address[2] data_memory_interface.bus_address[2] +1 1 +.names bus_address[3] data_memory_interface.bus_address[3] +1 1 +.names bus_address[4] data_memory_interface.bus_address[4] +1 1 +.names bus_address[5] data_memory_interface.bus_address[5] +1 1 +.names bus_address[6] data_memory_interface.bus_address[6] +1 1 +.names bus_address[7] data_memory_interface.bus_address[7] +1 1 +.names bus_address[8] data_memory_interface.bus_address[8] +1 1 +.names bus_address[9] data_memory_interface.bus_address[9] +1 1 +.names bus_address[10] data_memory_interface.bus_address[10] +1 1 +.names bus_address[11] data_memory_interface.bus_address[11] +1 1 +.names bus_address[12] data_memory_interface.bus_address[12] +1 1 +.names bus_address[13] data_memory_interface.bus_address[13] +1 1 +.names bus_address[14] data_memory_interface.bus_address[14] +1 1 +.names bus_address[15] data_memory_interface.bus_address[15] +1 1 +.names bus_address[16] data_memory_interface.bus_address[16] +1 1 +.names bus_address[17] data_memory_interface.bus_address[17] +1 1 +.names bus_address[18] data_memory_interface.bus_address[18] +1 1 +.names bus_address[19] data_memory_interface.bus_address[19] +1 1 +.names bus_address[20] data_memory_interface.bus_address[20] +1 1 +.names bus_address[21] data_memory_interface.bus_address[21] +1 1 +.names bus_address[22] data_memory_interface.bus_address[22] +1 1 +.names bus_address[23] data_memory_interface.bus_address[23] +1 1 +.names bus_address[24] data_memory_interface.bus_address[24] +1 1 +.names bus_address[25] data_memory_interface.bus_address[25] +1 1 +.names bus_address[26] data_memory_interface.bus_address[26] +1 1 +.names bus_address[27] data_memory_interface.bus_address[27] +1 1 +.names bus_address[28] data_memory_interface.bus_address[28] +1 1 +.names bus_address[29] data_memory_interface.bus_address[29] +1 1 +.names bus_address[30] data_memory_interface.bus_address[30] +1 1 +.names bus_address[31] data_memory_interface.bus_address[31] +1 1 +.names bus_byte_enable[0] data_memory_interface.bus_byte_enable[0] +1 1 +.names bus_byte_enable[1] data_memory_interface.bus_byte_enable[1] +1 1 +.names bus_byte_enable[2] data_memory_interface.bus_byte_enable[2] +1 1 +.names bus_byte_enable[3] data_memory_interface.bus_byte_enable[3] +1 1 +.names bus_read_data[0] data_memory_interface.bus_read_data[0] +1 1 +.names bus_read_data[1] data_memory_interface.bus_read_data[1] +1 1 +.names bus_read_data[2] data_memory_interface.bus_read_data[2] +1 1 +.names bus_read_data[3] data_memory_interface.bus_read_data[3] +1 1 +.names bus_read_data[4] data_memory_interface.bus_read_data[4] +1 1 +.names bus_read_data[5] data_memory_interface.bus_read_data[5] +1 1 +.names bus_read_data[6] data_memory_interface.bus_read_data[6] +1 1 +.names bus_read_data[7] data_memory_interface.bus_read_data[7] +1 1 +.names bus_read_data[8] data_memory_interface.bus_read_data[8] +1 1 +.names bus_read_data[9] data_memory_interface.bus_read_data[9] +1 1 +.names bus_read_data[10] data_memory_interface.bus_read_data[10] +1 1 +.names bus_read_data[11] data_memory_interface.bus_read_data[11] +1 1 +.names bus_read_data[12] data_memory_interface.bus_read_data[12] +1 1 +.names bus_read_data[13] data_memory_interface.bus_read_data[13] +1 1 +.names bus_read_data[14] data_memory_interface.bus_read_data[14] +1 1 +.names bus_read_data[15] data_memory_interface.bus_read_data[15] +1 1 +.names bus_read_data[16] data_memory_interface.bus_read_data[16] +1 1 +.names bus_read_data[17] data_memory_interface.bus_read_data[17] +1 1 +.names bus_read_data[18] data_memory_interface.bus_read_data[18] +1 1 +.names bus_read_data[19] data_memory_interface.bus_read_data[19] +1 1 +.names bus_read_data[20] data_memory_interface.bus_read_data[20] +1 1 +.names bus_read_data[21] data_memory_interface.bus_read_data[21] +1 1 +.names bus_read_data[22] data_memory_interface.bus_read_data[22] +1 1 +.names bus_read_data[23] data_memory_interface.bus_read_data[23] +1 1 +.names bus_read_data[24] data_memory_interface.bus_read_data[24] +1 1 +.names bus_read_data[25] data_memory_interface.bus_read_data[25] +1 1 +.names bus_read_data[26] data_memory_interface.bus_read_data[26] +1 1 +.names bus_read_data[27] data_memory_interface.bus_read_data[27] +1 1 +.names bus_read_data[28] data_memory_interface.bus_read_data[28] +1 1 +.names bus_read_data[29] data_memory_interface.bus_read_data[29] +1 1 +.names bus_read_data[30] data_memory_interface.bus_read_data[30] +1 1 +.names bus_read_data[31] data_memory_interface.bus_read_data[31] +1 1 +.names bus_read_enable data_memory_interface.bus_read_enable +1 1 +.names bus_write_data[0] data_memory_interface.bus_write_data[0] +1 1 +.names bus_write_data[1] data_memory_interface.bus_write_data[1] +1 1 +.names bus_write_data[2] data_memory_interface.bus_write_data[2] +1 1 +.names bus_write_data[3] data_memory_interface.bus_write_data[3] +1 1 +.names bus_write_data[4] data_memory_interface.bus_write_data[4] +1 1 +.names bus_write_data[5] data_memory_interface.bus_write_data[5] +1 1 +.names bus_write_data[6] data_memory_interface.bus_write_data[6] +1 1 +.names bus_write_data[7] data_memory_interface.bus_write_data[7] +1 1 +.names bus_write_data[8] data_memory_interface.bus_write_data[8] +1 1 +.names bus_write_data[9] data_memory_interface.bus_write_data[9] +1 1 +.names bus_write_data[10] data_memory_interface.bus_write_data[10] +1 1 +.names bus_write_data[11] data_memory_interface.bus_write_data[11] +1 1 +.names bus_write_data[12] data_memory_interface.bus_write_data[12] +1 1 +.names bus_write_data[13] data_memory_interface.bus_write_data[13] +1 1 +.names bus_write_data[14] data_memory_interface.bus_write_data[14] +1 1 +.names bus_write_data[15] data_memory_interface.bus_write_data[15] +1 1 +.names bus_write_data[16] data_memory_interface.bus_write_data[16] +1 1 +.names bus_write_data[17] data_memory_interface.bus_write_data[17] +1 1 +.names bus_write_data[18] data_memory_interface.bus_write_data[18] +1 1 +.names bus_write_data[19] data_memory_interface.bus_write_data[19] +1 1 +.names bus_write_data[20] data_memory_interface.bus_write_data[20] +1 1 +.names bus_write_data[21] data_memory_interface.bus_write_data[21] +1 1 +.names bus_write_data[22] data_memory_interface.bus_write_data[22] +1 1 +.names bus_write_data[23] data_memory_interface.bus_write_data[23] +1 1 +.names bus_write_data[24] data_memory_interface.bus_write_data[24] +1 1 +.names bus_write_data[25] data_memory_interface.bus_write_data[25] +1 1 +.names bus_write_data[26] data_memory_interface.bus_write_data[26] +1 1 +.names bus_write_data[27] data_memory_interface.bus_write_data[27] +1 1 +.names bus_write_data[28] data_memory_interface.bus_write_data[28] +1 1 +.names bus_write_data[29] data_memory_interface.bus_write_data[29] +1 1 +.names bus_write_data[30] data_memory_interface.bus_write_data[30] +1 1 +.names bus_write_data[31] data_memory_interface.bus_write_data[31] +1 1 +.names bus_write_enable data_memory_interface.bus_write_enable +1 1 +.names clock data_memory_interface.clock +1 1 +.names inst[12] data_memory_interface.data_format[0] +1 1 +.names inst[13] data_memory_interface.data_format[1] +1 1 +.names inst[14] data_memory_interface.data_format[2] +1 1 +.names bus_read_enable data_memory_interface.read_enable +1 1 +.names rs2_data[0] data_memory_interface.write_data[0] +1 1 +.names rs2_data[1] data_memory_interface.write_data[1] +1 1 +.names rs2_data[2] data_memory_interface.write_data[2] +1 1 +.names rs2_data[3] data_memory_interface.write_data[3] +1 1 +.names rs2_data[4] data_memory_interface.write_data[4] +1 1 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inst_funct7[3] +1 1 +.names inst[29] inst_funct7[4] +1 1 +.names inst[30] inst_funct7[5] +1 1 +.names inst[31] inst_funct7[6] +1 1 +.names inst[0] inst_opcode[0] +1 1 +.names inst[1] inst_opcode[1] +1 1 +.names inst[2] inst_opcode[2] +1 1 +.names inst[3] inst_opcode[3] +1 1 +.names inst[4] inst_opcode[4] +1 1 +.names inst[5] inst_opcode[5] +1 1 +.names inst[6] inst_opcode[6] +1 1 +.names singlecycle_datapath.program_counter.value[0] pc[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] pc[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] pc[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] pc[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] pc[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] pc[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] pc[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] pc[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] pc[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] pc[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] pc[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] pc[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] pc[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] pc[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] pc[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] pc[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] pc[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] pc[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] pc[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] pc[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] pc[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] pc[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] pc[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] pc[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] pc[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] pc[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] pc[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] pc[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] pc[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] pc[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] pc[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] pc[31] +1 1 +.names $true pc_write_enable +1 1 +.names inst[7] rd_address[0] +1 1 +.names $false rd_address[1] +1 1 +.names $false rd_address[2] +1 1 +.names $false rd_address[3] +1 1 +.names $false rd_address[4] +1 1 +.names bus_read_enable read_enable +1 1 +.names inst[15] rs1_address[0] +1 1 +.names $false rs1_address[1] +1 1 +.names $false rs1_address[2] +1 1 +.names $false rs1_address[3] +1 1 +.names $false rs1_address[4] +1 1 +.names inst[20] rs2_address[0] +1 1 +.names $false rs2_address[1] +1 1 +.names $false rs2_address[2] +1 1 +.names $false rs2_address[3] +1 1 +.names $false rs2_address[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_control.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_control.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_control.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_control.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_control.alu_function[4] +1 1 +.names singlecycle_ctlpath.alu_control.branch_funct[2] singlecycle_ctlpath.alu_control.branch_funct[1] +1 1 +.names inst[12] singlecycle_ctlpath.alu_control.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.alu_control.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.alu_control.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.alu_control.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.alu_control.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.alu_control.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.alu_control.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.alu_control.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.alu_control.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.alu_control.inst_funct7[6] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_funct[4] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_imm_funct[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_function[4] +1 1 +.names inst[12] singlecycle_ctlpath.control_transfer.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.control_transfer.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.control_transfer.inst_funct3[2] +1 1 +.names bus_read_enable singlecycle_ctlpath.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.data_mem_write_enable +1 1 +.names inst[12] singlecycle_ctlpath.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.inst_funct7[6] +1 1 +.names inst[0] singlecycle_ctlpath.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.regfile_write_enable +1 1 +.names bus_read_enable singlecycle_ctlpath.singlecycle_control.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.singlecycle_control.data_mem_write_enable +1 1 +.names inst[0] singlecycle_ctlpath.singlecycle_control.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.singlecycle_control.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.singlecycle_control.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.singlecycle_control.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.singlecycle_control.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.singlecycle_control.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.singlecycle_control.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.singlecycle_control.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.singlecycle_control.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.singlecycle_control.regfile_write_enable +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[0] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[1] +1 1 +.names $true singlecycle_datapath.adder_pc_plus_4.operand_a[2] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[3] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[4] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[5] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[6] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[7] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[8] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[9] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[10] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[11] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[12] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[13] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[14] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[15] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[16] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[17] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[18] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[19] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[20] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[21] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[22] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[23] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[24] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[25] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[26] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[27] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[28] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[29] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[30] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.operand_b[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.operand_b[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_4.operand_b[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_4.operand_b[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_4.operand_b[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_4.operand_b[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_4.operand_b[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_4.operand_b[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_4.operand_b[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_4.operand_b[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_4.operand_b[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_4.operand_b[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_4.operand_b[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_4.operand_b[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_4.operand_b[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_4.operand_b[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_4.operand_b[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_4.operand_b[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_4.operand_b[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_4.operand_b[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_4.operand_b[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_4.operand_b[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_4.operand_b[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_4.operand_b[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_4.operand_b[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_4.operand_b[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_4.operand_b[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_4.operand_b[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_4.operand_b[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_4.operand_b[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_4.operand_b[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_4.operand_b[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.result[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.result[1] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_immediate.operand_a[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_immediate.operand_a[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_immediate.operand_a[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_immediate.operand_a[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] 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bus_address[11] singlecycle_datapath.mux_next_pc_select.in2[11] +1 1 +.names bus_address[12] singlecycle_datapath.mux_next_pc_select.in2[12] +1 1 +.names bus_address[13] singlecycle_datapath.mux_next_pc_select.in2[13] +1 1 +.names bus_address[14] singlecycle_datapath.mux_next_pc_select.in2[14] +1 1 +.names bus_address[15] singlecycle_datapath.mux_next_pc_select.in2[15] +1 1 +.names bus_address[16] singlecycle_datapath.mux_next_pc_select.in2[16] +1 1 +.names bus_address[17] singlecycle_datapath.mux_next_pc_select.in2[17] +1 1 +.names bus_address[18] singlecycle_datapath.mux_next_pc_select.in2[18] +1 1 +.names bus_address[19] singlecycle_datapath.mux_next_pc_select.in2[19] +1 1 +.names bus_address[20] singlecycle_datapath.mux_next_pc_select.in2[20] +1 1 +.names bus_address[21] singlecycle_datapath.mux_next_pc_select.in2[21] +1 1 +.names bus_address[22] singlecycle_datapath.mux_next_pc_select.in2[22] +1 1 +.names bus_address[23] singlecycle_datapath.mux_next_pc_select.in2[23] +1 1 +.names bus_address[24] singlecycle_datapath.mux_next_pc_select.in2[24] +1 1 +.names bus_address[25] singlecycle_datapath.mux_next_pc_select.in2[25] +1 1 +.names bus_address[26] singlecycle_datapath.mux_next_pc_select.in2[26] +1 1 +.names bus_address[27] singlecycle_datapath.mux_next_pc_select.in2[27] +1 1 +.names bus_address[28] singlecycle_datapath.mux_next_pc_select.in2[28] +1 1 +.names bus_address[29] singlecycle_datapath.mux_next_pc_select.in2[29] +1 1 +.names bus_address[30] singlecycle_datapath.mux_next_pc_select.in2[30] +1 1 +.names bus_address[31] singlecycle_datapath.mux_next_pc_select.in2[31] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.in3[0] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.in3[1] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.in3[2] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.in3[3] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.in3[4] +1 1 +.names $false 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bus_address[16] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[48] +1 1 +.names bus_address[17] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[49] +1 1 +.names bus_address[18] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[50] +1 1 +.names bus_address[19] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[51] +1 1 +.names bus_address[20] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[52] +1 1 +.names bus_address[21] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[53] +1 1 +.names bus_address[22] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[54] +1 1 +.names bus_address[23] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[55] +1 1 +.names bus_address[24] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[56] +1 1 +.names bus_address[25] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[57] +1 1 +.names bus_address[26] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[58] 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singlecycle_datapath.adder_pc_plus_4.result[4] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[100] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[5] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[101] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[6] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[102] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[7] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[103] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[8] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[104] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[9] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[105] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[10] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[106] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[11] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[107] +1 1 +.names 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singlecycle_datapath.rs1_data[13] +1 1 +.names rs1_data[14] singlecycle_datapath.rs1_data[14] +1 1 +.names rs1_data[15] singlecycle_datapath.rs1_data[15] +1 1 +.names rs1_data[16] singlecycle_datapath.rs1_data[16] +1 1 +.names rs1_data[17] singlecycle_datapath.rs1_data[17] +1 1 +.names rs1_data[18] singlecycle_datapath.rs1_data[18] +1 1 +.names rs1_data[19] singlecycle_datapath.rs1_data[19] +1 1 +.names rs1_data[20] singlecycle_datapath.rs1_data[20] +1 1 +.names rs1_data[21] singlecycle_datapath.rs1_data[21] +1 1 +.names rs1_data[22] singlecycle_datapath.rs1_data[22] +1 1 +.names rs1_data[23] singlecycle_datapath.rs1_data[23] +1 1 +.names rs1_data[24] singlecycle_datapath.rs1_data[24] +1 1 +.names rs1_data[25] singlecycle_datapath.rs1_data[25] +1 1 +.names rs1_data[26] singlecycle_datapath.rs1_data[26] +1 1 +.names rs1_data[27] singlecycle_datapath.rs1_data[27] +1 1 +.names rs1_data[28] singlecycle_datapath.rs1_data[28] +1 1 +.names rs1_data[29] singlecycle_datapath.rs1_data[29] +1 1 +.names rs1_data[30] singlecycle_datapath.rs1_data[30] +1 1 +.names rs1_data[31] singlecycle_datapath.rs1_data[31] +1 1 +.names inst[20] singlecycle_datapath.rs2_address[0] +1 1 +.names $false singlecycle_datapath.rs2_address[1] +1 1 +.names $false singlecycle_datapath.rs2_address[2] +1 1 +.names $false singlecycle_datapath.rs2_address[3] +1 1 +.names $false singlecycle_datapath.rs2_address[4] +1 1 +.names rs2_data[0] singlecycle_datapath.rs2_data[0] +1 1 +.names rs2_data[1] singlecycle_datapath.rs2_data[1] +1 1 +.names rs2_data[2] singlecycle_datapath.rs2_data[2] +1 1 +.names rs2_data[3] singlecycle_datapath.rs2_data[3] +1 1 +.names rs2_data[4] singlecycle_datapath.rs2_data[4] +1 1 +.names rs2_data[5] singlecycle_datapath.rs2_data[5] +1 1 +.names rs2_data[6] singlecycle_datapath.rs2_data[6] +1 1 +.names rs2_data[7] singlecycle_datapath.rs2_data[7] +1 1 +.names rs2_data[8] singlecycle_datapath.rs2_data[8] +1 1 +.names rs2_data[9] singlecycle_datapath.rs2_data[9] +1 1 +.names rs2_data[10] singlecycle_datapath.rs2_data[10] +1 1 +.names rs2_data[11] singlecycle_datapath.rs2_data[11] +1 1 +.names rs2_data[12] singlecycle_datapath.rs2_data[12] +1 1 +.names rs2_data[13] singlecycle_datapath.rs2_data[13] +1 1 +.names rs2_data[14] singlecycle_datapath.rs2_data[14] +1 1 +.names rs2_data[15] singlecycle_datapath.rs2_data[15] +1 1 +.names rs2_data[16] singlecycle_datapath.rs2_data[16] +1 1 +.names rs2_data[17] singlecycle_datapath.rs2_data[17] +1 1 +.names rs2_data[18] singlecycle_datapath.rs2_data[18] +1 1 +.names rs2_data[19] singlecycle_datapath.rs2_data[19] +1 1 +.names rs2_data[20] singlecycle_datapath.rs2_data[20] +1 1 +.names rs2_data[21] singlecycle_datapath.rs2_data[21] +1 1 +.names rs2_data[22] singlecycle_datapath.rs2_data[22] +1 1 +.names rs2_data[23] singlecycle_datapath.rs2_data[23] +1 1 +.names rs2_data[24] singlecycle_datapath.rs2_data[24] +1 1 +.names rs2_data[25] singlecycle_datapath.rs2_data[25] +1 1 +.names rs2_data[26] singlecycle_datapath.rs2_data[26] +1 1 +.names rs2_data[27] singlecycle_datapath.rs2_data[27] +1 1 +.names rs2_data[28] singlecycle_datapath.rs2_data[28] +1 1 +.names rs2_data[29] singlecycle_datapath.rs2_data[29] +1 1 +.names rs2_data[30] singlecycle_datapath.rs2_data[30] +1 1 +.names rs2_data[31] singlecycle_datapath.rs2_data[31] +1 1 +.names rs2_data[0] write_data[0] +1 1 +.names rs2_data[1] write_data[1] +1 1 +.names rs2_data[2] write_data[2] +1 1 +.names rs2_data[3] write_data[3] +1 1 +.names rs2_data[4] write_data[4] +1 1 +.names rs2_data[5] write_data[5] +1 1 +.names rs2_data[6] write_data[6] +1 1 +.names rs2_data[7] write_data[7] +1 1 +.names rs2_data[8] write_data[8] +1 1 +.names rs2_data[9] write_data[9] +1 1 +.names rs2_data[10] write_data[10] +1 1 +.names rs2_data[11] write_data[11] +1 1 +.names rs2_data[12] write_data[12] +1 1 +.names rs2_data[13] write_data[13] +1 1 +.names rs2_data[14] write_data[14] +1 1 +.names rs2_data[15] write_data[15] +1 1 +.names rs2_data[16] write_data[16] +1 1 +.names rs2_data[17] write_data[17] +1 1 +.names rs2_data[18] write_data[18] +1 1 +.names rs2_data[19] write_data[19] +1 1 +.names rs2_data[20] write_data[20] +1 1 +.names rs2_data[21] write_data[21] +1 1 +.names rs2_data[22] write_data[22] +1 1 +.names rs2_data[23] write_data[23] +1 1 +.names rs2_data[24] write_data[24] +1 1 +.names rs2_data[25] write_data[25] +1 1 +.names rs2_data[26] write_data[26] +1 1 +.names rs2_data[27] write_data[27] +1 1 +.names rs2_data[28] write_data[28] +1 1 +.names rs2_data[29] write_data[29] +1 1 +.names rs2_data[30] write_data[30] +1 1 +.names rs2_data[31] write_data[31] +1 1 +.names bus_write_enable write_enable +1 1 +.end diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt new file mode 100644 index 00000000000..e06768cd4cf --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt @@ -0,0 +1,31 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/tests + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=riscv_core_lut6.blif #Contains dangling LUT buffers + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-starting_stage vpr -track_memory_usage --pack + +script_params_list_add=--absorb_buffer_luts on +script_params_list_add=--absorb_buffer_luts off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt new file mode 100644 index 00000000000..54fc8433be0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -0,0 +1,3 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33088 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 32980 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 3c52ef71400..d4ffa0b7bb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.97 0.02 9300 4 0.13 -1 -1 33000 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25448 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.22 0.04 9516 5 0.14 -1 -1 33248 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.06 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 0.05 9344 4 0.16 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25420 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.08 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.72 0.05 9596 5 0.12 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28136 11 30 313 321 2 117 55 7 7 49 clb auto 0.32 380 0.12 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 2cb5bad9888..ea2684cd3c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_n4_v7_bidir.xml styr.blif common 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21744 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1261 0.12 5.33383 -68.3994 -5.33383 16 1903 29 2.43e+06 2.01e+06 -1 -1 0.48 1826 16 939 2863 195365 30983 7.17859 -89.6405 -7.17859 0 0 -1 -1 0.06 -k4_n4_v7_longline_bidir.xml styr.blif common 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21888 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2324 21 2.43e+06 2.01e+06 -1 -1 0.25 2262 45 1271 3738 304440 42218 8.37849 -101.759 -8.37849 0 0 -1 -1 0.07 -k4_n4_v7_l1_bidir.xml styr.blif common 1.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22404 10 10 253 263 1 169 87 11 11 121 clb auto 0.04 1227 0.12 6.05408 -74.8187 -6.05408 10 1522 37 2.43e+06 2.01e+06 -1 -1 1.07 1214 16 1112 3531 274215 52624 7.44659 -87.7658 -7.44659 0 0 -1 -1 0.05 -k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21504 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1236 0.33 5.30313 -63.535 -5.30313 16 2042 28 2.43e+06 2.01e+06 -1 -1 0.59 1979 19 1142 3366 494089 68283 7.86978 -98.8292 -7.86978 0 0 -1 -1 0.07 +k4_n4_v7_bidir.xml styr.blif common 1.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22008 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1261 0.20 5.33383 -68.3994 -5.33383 17 1934 35 2.43e+06 2.01e+06 -1 -1 0.75 1937 20 1286 4168 328994 46247 7.85307 -98.3305 -7.85307 0 0 -1 -1 0.11 +k4_n4_v7_longline_bidir.xml styr.blif common 1.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21856 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2206 22 2.43e+06 2.01e+06 -1 -1 0.59 2235 28 1635 4962 403273 51999 8.46175 -102.579 -8.46175 0 0 -1 -1 0.12 +k4_n4_v7_l1_bidir.xml styr.blif common 1.97 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22524 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1227 0.26 6.05408 -74.8187 -6.05408 10 1516 43 2.43e+06 2.01e+06 -1 -1 1.24 1193 18 1215 4020 298127 55249 7.03996 -86.5204 -7.03996 0 0 -1 -1 0.09 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21800 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1236 0.59 5.30313 -63.535 -5.30313 14 2242 44 2.43e+06 2.01e+06 -1 -1 0.93 2224 21 1592 5130 856330 113214 30.5003 -302.812 -30.5003 0 0 -1 -1 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 802eb7792dc..23c3bbba0e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 0.97 0.03 9344 4 0.11 -1 -1 33140 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25236 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.24 0.04 9336 4 0.16 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25204 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.25 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.51 0.04 9340 4 0.17 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.90 0.05 9312 4 0.14 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25696 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.55 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 34026948a96..3e8c896e8d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.03 9248 4 0.09 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25732 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 395 0.51 2.21922 -172.773 -2.21922 20 659 32 1.07788e+06 1.02399e+06 49980.0 1020.00 0.13 490 19 532 1247 59762 19337 2.76555 -183.23 -2.76555 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.48 0.05 9352 4 0.14 -1 -1 33052 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 395 0.95 2.21922 -172.773 -2.21922 20 670 41 1.07788e+06 1.02399e+06 49980.0 1020.00 0.26 548 21 878 2095 96841 30313 2.52691 -184.979 -2.52691 0 0 65453.8 1335.79 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt index ef4741413f3..de859d8d00d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.84 0.04 9256 4 0.10 -1 -1 33156 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25920 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 488 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.43079 -179.827 -2.43079 0 0 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.19 0.04 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25812 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 506 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.56012 -181.991 -2.56012 0 0 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index f8b490ba19f..368b2219414 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.76 0.00 5876 1 0.01 -1 -1 29900 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24584 9 8 71 66 1 37 20 5 5 25 clb auto 0.41 85 0.02 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.03 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.29 0.01 6252 1 0.00 -1 -1 30268 -1 -1 8 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26792 19 18 299 240 1 150 45 6 6 36 clb auto 1.68 513 0.07 3.94024 -72.8405 -3.94024 66 919 32 403230 201615 140689. 3908.03 0.13 788 16 603 878 36522 13558 4.8522 -103.597 -4.8522 0 0 172795. 4799.85 0.02 62 81 85 13 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5912 1 0.01 -1 -1 29788 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23852 9 8 71 66 1 37 20 5 5 25 clb auto 0.65 85 0.04 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.05 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.65 0.01 6104 1 0.01 -1 -1 30212 -1 -1 8 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26504 19 18 299 240 1 150 45 6 6 36 clb auto 2.60 513 0.13 3.94024 -72.8405 -3.94024 66 918 26 403230 201615 140689. 3908.03 0.27 783 17 611 899 37480 13874 4.75135 -103.522 -4.75135 0 0 172795. 4799.85 0.03 62 81 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index e6b840828dd..472c1c7a13d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.22 0.00 5380 1 0.00 -1 -1 29660 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18580 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.23 0.00 5380 1 0.01 -1 -1 29768 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18620 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 3.10 0.17 48060 2 0.92 -1 -1 51000 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27504 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.14 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.20 45 11 35 41 1194 592 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 2.96 0.19 48064 2 0.92 -1 -1 50868 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27624 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 25 0.16 1.079 -11.7073 -1.079 12 80 9 9.10809e+06 8.35357e+06 194400. 864.002 0.12 78 5 36 51 4226 1673 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.26 0.00 5736 1 0.01 -1 -1 29784 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22984 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.27 0.01 5744 1 0.00 -1 -1 29744 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22716 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 8.01 0.07 15940 2 0.07 -1 -1 33480 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 57868 311 156 972 1128 1 953 514 28 28 784 memory auto 0.36 7976 1.53 4.26612 -4292.66 -4.26612 40 13615 28 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.77 12850 18 2816 3295 4898763 1500574 4.29603 -4929.32 -4.29603 -20.3472 -0.298787 2.55406e+06 3257.73 0.94 15 938 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 7.96 0.10 15892 2 0.11 -1 -1 33504 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 58204 311 156 972 1128 1 953 514 28 28 784 memory auto 0.30 8142 1.46 3.96275 -2917.87 -3.96275 40 13931 23 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 3.81 12943 21 3274 3870 4601511 1352718 4.43746 -3526.24 -4.43746 -894.645 -2.58347 2.60581e+06 3323.74 0.90 14 939 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.28 0.00 5408 1 0.00 -1 -1 29736 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18644 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.28 0.00 5344 1 0.01 -1 -1 29656 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18612 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 4.79 0.27 47992 2 1.47 -1 -1 50904 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27108 5 156 191 347 1 163 316 15 15 225 clb auto 0.06 22 0.27 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.28 45 12 37 43 1274 630 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 4.67 0.25 48016 2 1.44 -1 -1 50872 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27236 5 156 191 347 1 163 316 15 15 225 clb auto 0.07 25 0.29 1.079 -11.7073 -1.079 12 81 10 9.10809e+06 8.35357e+06 194400. 864.002 0.21 78 5 36 51 4359 1735 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.34 0.01 5832 1 0.00 -1 -1 29732 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22900 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.32 0.01 5936 1 0.00 -1 -1 29852 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22796 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.01 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 10.02 0.12 15992 2 0.12 -1 -1 33496 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57752 311 156 972 1128 1 953 514 28 28 784 memory auto 0.52 7976 2.61 4.26612 -4292.66 -4.26612 40 13542 15 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.95 12829 18 2820 3287 4811709 1472844 4.29603 -4980.64 -4.29603 -21.7586 -0.298787 2.55406e+06 3257.73 0.93 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 10.30 0.11 15988 2 0.11 -1 -1 33640 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57728 311 156 972 1128 1 953 514 28 28 784 memory auto 0.55 8142 2.69 3.96275 -2917.87 -3.96275 40 13846 26 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 4.15 12969 19 3084 3659 4345349 1258957 4.30407 -3216.46 -4.30407 -770.89 -1.60451 2.60581e+06 3323.74 0.84 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index e3d8437a449..e88a5877964 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 22856 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.00 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.00 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22644 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.02 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 96218a45873..9fd514ba486 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -fixed_grid.xml raygentop.v common 24.91 0.35 29812 3 1.36 -1 -1 46744 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 111880 214 305 3028 2934 1 1505 639 25 25 625 -1 25x25 2.57 12605 2.19 4.41596 -2612.27 -4.41596 48 28432 36 3.19446e+07 9.20413e+06 1.97188e+06 3155.02 14.81 23059 24 7120 15025 4954028 1103896 4.89193 -3202.77 -4.89193 0 0 2.52596e+06 4041.53 0.66 -column_io.xml raygentop.v common 16.85 0.35 29556 3 1.41 -1 -1 46796 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 113028 214 305 3028 2934 1 1505 639 25 25 625 io auto 2.63 11829 2.17 4.3 -2616.5 -4.3 50 27225 43 2.82259e+07 9.20413e+06 1.88190e+06 3011.03 6.99 21196 20 6960 15110 4318307 929754 4.87311 -3076.36 -4.87311 0 0 2.49714e+06 3995.43 0.55 -multiwidth_blocks.xml raygentop.v common 15.89 0.35 29764 3 1.28 -1 -1 46772 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 113412 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.57 11338 2.14 4.29768 -2529.75 -4.29768 66 23937 41 1.65001e+07 9.20413e+06 1.25644e+06 3480.44 6.48 19907 18 5801 12392 3140521 809560 4.84591 -2938.92 -4.84591 0 0 1.57029e+06 4349.83 0.44 -non_column.xml raygentop.v common 28.72 0.35 30024 3 1.31 -1 -1 46612 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 115204 214 305 3028 2934 1 1505 639 33 33 1089 io auto 2.63 14616 2.58 4.29046 -2635.7 -4.29046 48 30109 32 5.44432e+07 9.20413e+06 3.01743e+06 2770.83 18.05 24186 19 7051 15889 4433148 1071530 4.85023 -3171.88 -4.85023 0 0 3.86350e+06 3547.75 0.60 -non_column_tall_aspect_ratio.xml raygentop.v common 18.45 0.35 30092 3 1.27 -1 -1 46752 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 126732 214 305 3028 2934 1 1505 639 23 46 1058 io auto 2.56 12529 2.48 4.43753 -2639.16 -4.43753 46 26860 43 5.05849e+07 9.20413e+06 2.90934e+06 2749.85 8.06 22146 18 6584 14208 3679631 917195 4.85524 -3103.91 -4.85524 0 0 3.73194e+06 3527.36 0.50 -non_column_wide_aspect_ratio.xml raygentop.v common 17.73 0.35 30204 3 1.35 -1 -1 46760 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 122820 214 305 3028 2934 1 1505 639 43 22 946 io auto 2.63 13897 2.44 4.78236 -2839.4 -4.78236 48 27697 40 4.55909e+07 9.20413e+06 2.64263e+06 2793.48 7.49 23142 16 5802 12647 3201587 806357 5.1351 -3189.92 -5.1351 0 0 3.38205e+06 3575.11 0.45 -custom_sbloc.xml raygentop.v common 13.16 0.34 29628 3 1.37 -1 -1 46616 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 108560 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.59 10900 2.23 4.30764 -2565.02 -4.30764 62 22962 48 1.65001e+07 9.20413e+06 1.15634e+06 3203.15 3.65 18983 18 5723 12136 3238340 813980 5.0112 -2991.61 -5.0112 0 0 1.43990e+06 3988.64 0.45 -multiple_io_types.xml raygentop.v common 54.11 0.35 29904 3 1.39 -1 -1 46736 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 421956 214 305 3028 2934 1 1505 639 67 67 4489 io_left auto 3.56 39959 9.71 6.08816 -4548.16 -6.08816 44 55781 49 2.48753e+08 9.20413e+06 1.09868e+07 2447.50 31.93 49814 16 7203 15231 8667353 2053508 6.36455 -5098.86 -6.36455 0 0 1.42904e+07 3183.43 1.15 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +fixed_grid.xml raygentop.v common 25.84 0.31 29664 3 1.52 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 72184 214 305 2964 2870 1 1438 634 25 25 625 -1 25x25 3.17 12875 3.64 4.4701 -2560.95 -4.4701 56 24974 27 3.19446e+07 8.93466e+06 2.27235e+06 3635.76 12.48 22306 18 5829 12928 3763475 891650 4.89048 -2985.86 -4.89048 0 0 2.89946e+06 4639.14 1.30 +column_io.xml raygentop.v common 30.79 0.30 29656 3 1.47 -1 -1 40420 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 75196 214 305 2964 2870 1 1438 634 25 25 625 io auto 3.12 11261 3.33 4.46107 -2506.79 -4.46107 50 26270 36 2.82259e+07 8.93466e+06 1.88190e+06 3011.03 17.84 20904 17 6177 13915 3771135 818422 4.87754 -2920.16 -4.87754 0 0 2.49714e+06 3995.43 1.34 +multiwidth_blocks.xml raygentop.v common 31.76 0.33 29788 3 1.78 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 67884 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.19 10446 3.78 4.42441 -2494.7 -4.42441 68 23181 35 1.65001e+07 8.93466e+06 1.28755e+06 3566.63 18.26 18866 14 5520 12874 4172039 1070780 4.77245 -2886.5 -4.77245 0 0 1.60474e+06 4445.26 1.39 +non_column.xml raygentop.v common 24.18 0.36 30204 3 1.60 -1 -1 40416 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 90400 214 305 2964 2870 1 1438 634 33 33 1089 io auto 3.14 13212 4.09 4.29383 -2619.77 -4.29383 50 28185 27 5.44432e+07 8.93466e+06 3.11799e+06 2863.17 9.53 22797 19 6862 15251 4449583 1089545 5.14569 -3069.09 -5.14569 0 0 4.13529e+06 3797.33 1.50 +non_column_tall_aspect_ratio.xml raygentop.v common 39.22 0.38 30152 3 1.55 -1 -1 40444 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 98128 214 305 2964 2870 1 1438 634 23 46 1058 io auto 3.13 13287 4.13 4.49581 -2567.26 -4.49581 50 25552 23 5.05849e+07 8.93466e+06 3.11839e+06 2947.44 24.98 21898 15 5590 12773 2718112 668692 5.25903 -2987.14 -5.25903 0 0 4.13508e+06 3908.40 1.05 +non_column_wide_aspect_ratio.xml raygentop.v common 41.31 0.38 30232 3 1.56 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 83160 214 305 2964 2870 1 1438 634 43 22 946 io auto 3.16 14109 3.90 4.53087 -2746.94 -4.53087 46 30005 40 4.55909e+07 8.93466e+06 2.54300e+06 2688.17 26.99 24419 24 7023 15864 4574615 1097967 4.99799 -3215.24 -4.99799 0 0 3.26968e+06 3456.32 1.68 +custom_sbloc.xml raygentop.v common 25.36 0.34 29672 3 1.45 -1 -1 40356 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 62944 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.31 10710 3.67 4.29215 -2514.15 -4.29215 62 23655 46 1.65001e+07 8.93466e+06 1.15634e+06 3203.15 12.04 19234 20 6084 13886 3597203 896399 4.84201 -2951.3 -4.84201 0 0 1.43990e+06 3988.64 1.35 +multiple_io_types.xml raygentop.v common 112.14 0.30 29536 3 1.42 -1 -1 40528 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 416268 214 305 2964 2870 1 1438 634 67 67 4489 io_left auto 3.94 37811 16.94 5.77645 -4658.65 -5.77645 50 52755 46 2.48753e+08 8.93466e+06 1.23326e+07 2747.29 82.43 48473 14 6877 15481 6627715 1528770 6.07015 -5121.09 -6.07015 0 0 1.63652e+07 3645.63 1.15 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index ea08b5de124..a02a8e7c371 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.52 0.04 8976 3 0.19 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30184 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 648 0.27 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.36 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.03 +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.10 0.03 9176 3 0.24 -1 -1 36308 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29860 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 648 0.49 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.43 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index 86bd5fae5cb..79184563f70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.18 0.03 8824 4 0.17 -1 -1 33880 -1 -1 75 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 33720 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 867 0.31 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.07 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.85 0.04 8880 4 0.28 -1 -1 33932 -1 -1 75 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 33336 99 130 378 508 1 307 305 15 15 225 memory auto 0.06 867 0.50 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index b9f71e69852..7308c682561 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 11.90 0.11 15932 2 0.12 -1 -1 41156 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 109624 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.62 8049 2.45 4.39014 -3508.77 -4.39014 40 14355 17 4.25198e+07 9.78293e+06 2.15488e+06 2748.57 5.94 13340 14 2575 2984 2890890 864023 4.47512 -4294.11 -4.47512 -229.075 -0.938948 2.69199e+06 3433.66 0.71 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 9.24 0.11 16104 2 0.13 -1 -1 40376 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 113492 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 7956 2.42 4.09743 -3819.07 -4.09743 40 14778 30 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 3.22 13612 18 3210 3663 3242196 933097 4.35038 -5481.7 -4.35038 -262.106 -1.75122 2.74222e+06 3497.72 0.78 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 12.06 0.11 16128 2 0.12 -1 -1 39644 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 110504 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 8049 2.60 4.39014 -3508.77 -4.39014 40 15248 20 4.25198e+07 9.78293e+06 2.15029e+06 2742.71 5.86 14194 13 2606 3050 2855904 921559 4.47512 -4375.09 -4.47512 -146.535 -0.790364 2.68740e+06 3427.80 0.78 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 12.79 0.11 16188 2 0.11 -1 -1 34240 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65912 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.69 3.71918 -3791.41 -3.71918 38 14664 22 4.25198e+07 9.78293e+06 2.06134e+06 2629.25 5.78 13215 12 2732 3118 2727378 877873 4.6565 -4338.38 -4.6565 -217.731 -0.937841 2.60756e+06 3325.97 1.23 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.71 0.10 16176 2 0.10 -1 -1 34268 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65764 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.79 7855 2.67 4.29577 -3815.97 -4.29577 40 14565 31 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 6.37 13336 16 3013 3384 3288699 970769 4.44197 -4744.42 -4.44197 -296.276 -1.26627 2.74222e+06 3497.72 1.46 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.25 0.11 16296 2 0.10 -1 -1 34304 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 66468 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.70 3.71918 -3791.41 -3.71918 38 15436 16 4.25198e+07 9.78293e+06 2.05675e+06 2623.40 6.15 14101 14 2682 3088 2566936 820999 4.6565 -4410.32 -4.6565 -156.683 -0.791471 2.60298e+06 3320.12 1.27 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 677e608df28..3e6f00a5572 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 6.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47932 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.29 10133 1.54 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 3.07 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 11.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47732 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.40 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.43 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.64 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 6bf3edd42e8..74a5f0d6399 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.66 0.18 29408 4 1.52 -1 -1 39844 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 71136 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.32 10711 2.51 4.0362 -2478.27 -4.0362 80 21050 36 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 6.52 19612 16 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.60 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 30.68 0.28 29452 4 2.32 -1 -1 39812 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 70264 193 205 2926 2852 1 1371 570 20 20 400 memory auto 2.06 10711 4.38 4.0362 -2478.27 -4.0362 76 23027 46 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 18.33 20051 16 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.56 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 0e654601b04..d6d715660c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 0.03 9016 3 0.18 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29808 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.42 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.35 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.37 0.04 9064 3 0.28 -1 -1 36168 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29732 99 130 363 493 1 251 295 12 12 144 clb auto 0.15 655 0.51 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.48 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index f801f4edbdd..b6c87f17e76 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml test_eblif.eblif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19196 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 -k6_frac_N10_40nm.xml conn_order.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19088 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml test_eblif.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19208 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml conn_order.eblif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index bd3931e8890..f2e465c68c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.17 0.06 9248 4 0.12 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25408 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 404 0.10 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.10 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.96 0.04 9312 4 0.14 -1 -1 32968 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25592 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.19 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 999794c9784..0518b8e3905 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.33 0.04 9276 4 0.10 -1 -1 33068 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25828 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.08 2.2252 -166.078 -2.2252 14 572 36 1.07788e+06 1.02399e+06 81563.3 1664.56 0.23 496 17 566 1248 92246 25162 2.83162 -197.755 -2.83162 0 0 98201.7 2004.12 0.04 +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.69 0.04 9412 4 0.13 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25564 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.13 2.2252 -166.078 -2.2252 18 543 24 1.07788e+06 1.02399e+06 98201.7 2004.12 0.44 452 22 829 1925 144634 31657 2.69784 -193.844 -2.69784 0 0 111547. 2276.47 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt index 8cf331b7341..8e6838e0dae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_40nm.xml stereovision3.v common 1.04 0.04 8832 4 0.13 -1 -1 33000 -1 -1 19 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21948 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 449 0.11 2.21945 -168.153 -2.21945 20 707 20 1.34735e+06 1.02399e+06 54591.7 1114.12 0.09 543 15 507 1173 62601 20949 2.36754 -182.136 -2.36754 0 0 71469.7 1458.57 0.04 +k6_N10_40nm.xml stereovision3.v common 1.78 0.04 8840 4 0.15 -1 -1 33152 -1 -1 19 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21668 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 449 0.18 2.21945 -168.153 -2.21945 20 700 27 1.34735e+06 1.02399e+06 54591.7 1114.12 0.22 592 27 884 2154 107177 33979 2.48822 -190.515 -2.48822 0 0 71469.7 1458.57 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index fea01e181d6..ef5f67f9390 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.13 0.03 9288 4 0.15 -1 -1 32996 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25796 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 478 0.10 2.23761 -174.252 -2.23761 20 719 19 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 614 18 539 1332 68243 22358 2.67002 -194.193 -2.67002 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.32 0.04 9360 4 0.15 -1 -1 33176 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25668 11 30 262 292 2 104 60 7 7 49 clb auto 0.13 478 0.17 2.23761 -174.252 -2.23761 22 729 34 1.07788e+06 1.02399e+06 54623.3 1114.76 0.57 706 32 955 2278 127150 37450 3.18721 -193.511 -3.18721 0 0 69322.2 1414.74 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 002da357c43..4635f896009 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -shorted_flyover_wires.xml raygentop.v common 13.95 0.29 29620 3 1.01 -1 -1 40424 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 62756 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.22 11388 2.11 4.27581 -2648.79 -4.27581 64 28724 29 1.65001e+07 9.20413e+06 1.11360e+06 3084.77 5.16 23851 15 6088 13507 4078200 1049123 5.27078 -3186.3 -5.27078 0 0 1.39747e+06 3871.11 0.84 -buffered_flyover_wires.xml raygentop.v common 16.04 0.26 29596 3 0.99 -1 -1 40432 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 63300 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.08 10724 2.11 4.42883 -2547.95 -4.42883 70 27239 49 1.65001e+07 9.20413e+06 1.25135e+06 3466.35 7.35 21887 21 5718 12377 4320243 1123061 4.86613 -3081.64 -4.86613 0 0 1.57792e+06 4370.98 0.97 +shorted_flyover_wires.xml raygentop.v common 30.04 0.29 29556 3 1.51 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 68244 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.25 11108 3.58 4.79392 -2540.18 -4.79392 66 27597 36 1.65001e+07 8.93466e+06 1.15238e+06 3192.19 16.05 23046 15 6018 13533 4245665 1060813 5.29045 -2968.52 -5.29045 0 0 1.43513e+06 3975.42 1.54 +buffered_flyover_wires.xml raygentop.v common 25.09 0.30 29760 3 1.50 -1 -1 40384 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 63188 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.16 10687 3.41 4.50659 -2437.12 -4.50659 70 26328 36 1.65001e+07 8.93466e+06 1.25135e+06 3466.35 11.46 20953 17 5222 11702 4411046 1119985 5.08067 -2980.08 -5.08067 0 0 1.57792e+06 4370.98 1.65 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index 65377a5c306..20d8adc93f1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -hard_fpu_arch_timing.xml mm3.v common 1.82 0.01 6520 1 0.02 -1 -1 30472 -1 -1 0 193 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 33644 193 32 545 422 1 289 227 21 21 441 io auto 0.78 3143 0.29 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.37 +hard_fpu_arch_timing.xml mm3.v common 3.04 0.02 6688 1 0.02 -1 -1 30484 -1 -1 0 193 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33224 193 32 545 422 1 289 227 21 21 441 io auto 1.30 3143 0.53 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.69 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 184eb3554ca..a4fbccd25c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 1.36 0.03 8936 3 0.18 -1 -1 36228 -1 -1 67 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30848 99 130 363 493 1 249 297 13 13 169 clb auto 0.38 558 0.18 36 1328 8 0 0 481804. 2850.91 0.15 +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.47 0.04 8992 3 0.27 -1 -1 36292 -1 -1 67 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 30520 99 130 363 493 1 249 297 13 13 169 clb auto 0.74 558 0.36 36 1328 8 0 0 481804. 2850.91 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 4c2acbdc699..cfab22fbd74 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.02 0.03 9304 4 0.11 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25512 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.04 9476 4 0.14 -1 -1 33008 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25868 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index 05380269819..4b348ee8b63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.23 -1 -1 0 0.01 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19016 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.20 -1 -1 0 0.00 -1 -1 29600 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19236 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.18 -1 -1 0 0.00 -1 -1 29712 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19160 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.23 -1 -1 0 0.00 -1 -1 29692 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19028 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and.blif common 0.22 -1 -1 1 0.00 -1 -1 29724 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18952 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.22 -1 -1 1 0.01 -1 -1 31460 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19292 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.27 -1 -1 1 0.03 -1 -1 31980 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and_latch.blif common 0.20 -1 -1 1 0.00 -1 -1 29772 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19388 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml false_path_mux.blif common 0.26 -1 -1 1 0.02 -1 -1 31604 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19204 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_2x2.blif common 0.25 -1 -1 1 0.02 -1 -1 31504 -1 -1 1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19328 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x3.blif common 0.25 -1 -1 1 0.02 -1 -1 32044 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19304 6 6 12 18 0 12 13 3 3 9 -1 auto 0.00 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x4.blif common 0.33 -1 -1 2 0.03 -1 -1 32640 -1 -1 3 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19676 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_4x4.blif common 0.32 -1 -1 4 0.03 -1 -1 32432 -1 -1 2 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19880 8 8 29 37 0 21 18 4 4 16 clb auto 0.01 54 0.01 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x5.blif common 0.33 -1 -1 4 0.04 -1 -1 32236 -1 -1 4 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20056 10 10 47 57 0 39 24 4 4 16 clb auto 0.02 126 0.02 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x6.blif common 0.52 -1 -1 5 0.07 -1 -1 32692 -1 -1 5 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20308 11 11 61 72 0 51 27 5 5 25 clb auto 0.03 176 0.03 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_1bit.blif common 0.29 -1 -1 1 0.03 -1 -1 30932 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19364 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_2bit.blif common 0.27 -1 -1 1 0.03 -1 -1 32292 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19312 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_3bit.blif common 0.31 -1 -1 2 0.03 -1 -1 32112 -1 -1 1 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19400 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_4bit.blif common 0.26 -1 -1 2 0.02 -1 -1 32148 -1 -1 1 9 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19348 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_5bit.blif common 0.29 -1 -1 3 0.02 -1 -1 31900 -1 -1 1 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19392 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.41 -1 -1 0 0.01 -1 -1 29724 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.59 -1 -1 0 0.01 -1 -1 29596 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18640 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.38 -1 -1 0 0.00 -1 -1 29720 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19040 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 -1 -1 0 0.00 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18780 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.23 -1 -1 1 0.00 -1 -1 29692 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 -1 -1 1 0.02 -1 -1 31376 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.37 -1 -1 1 0.03 -1 -1 31888 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18808 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.24 -1 -1 1 0.00 -1 -1 29708 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.31 -1 -1 1 0.02 -1 -1 31544 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19180 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.33 -1 -1 1 0.03 -1 -1 31564 -1 -1 1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18776 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.32 -1 -1 1 0.03 -1 -1 31928 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18756 6 6 12 18 0 12 13 3 3 9 -1 auto 0.01 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.36 -1 -1 2 0.04 -1 -1 32456 -1 -1 3 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19572 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.38 -1 -1 4 0.05 -1 -1 32444 -1 -1 2 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19596 8 8 29 37 0 21 18 4 4 16 clb auto 0.02 54 0.02 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.47 -1 -1 4 0.06 -1 -1 32056 -1 -1 4 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19884 10 10 47 57 0 39 24 4 4 16 clb auto 0.03 126 0.03 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.61 -1 -1 5 0.08 -1 -1 32484 -1 -1 5 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 20232 11 11 61 72 0 51 27 5 5 25 clb auto 0.04 176 0.04 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.32 -1 -1 1 0.03 -1 -1 30776 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19060 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.36 -1 -1 1 0.03 -1 -1 32372 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.34 -1 -1 2 0.03 -1 -1 32092 -1 -1 1 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.36 -1 -1 2 0.02 -1 -1 32136 -1 -1 1 9 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.33 -1 -1 3 0.03 -1 -1 31852 -1 -1 1 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18836 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index ddd64c08c03..74e4825ed33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18828 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19132 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18816 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19212 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19128 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19096 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18860 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18852 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19120 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19072 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18496 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index d304b6b230c..7142409fdae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -x_gaussian_y_uniform.xml stereovision3.v common 1.11 0.04 9284 4 0.12 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25832 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 367 0.08 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.12 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_gaussian.xml stereovision3.v common 1.15 0.04 9284 4 0.11 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25808 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 344 0.07 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.16 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_gaussian_y_gaussian.xml stereovision3.v common 1.13 0.04 9296 4 0.10 -1 -1 33064 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26008 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.09 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.15 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_uniform.xml stereovision3.v common 1.05 0.03 9264 4 0.13 -1 -1 33028 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26112 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 370 0.07 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.11 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_delta.xml stereovision3.v common 1.09 0.04 9200 4 0.15 -1 -1 33012 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25788 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.08 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.12 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_delta.xml stereovision3.v common 1.07 0.04 9272 4 0.14 -1 -1 33160 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26220 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.07 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.13 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_gaussian_y_uniform.xml stereovision3.v common 1.55 0.07 9364 4 0.15 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25968 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 367 0.12 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.16 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_uniform_y_gaussian.xml stereovision3.v common 1.68 0.05 9548 4 0.14 -1 -1 33140 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25988 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 344 0.11 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.27 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_gaussian_y_gaussian.xml stereovision3.v common 1.53 0.04 9372 4 0.15 -1 -1 33040 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26148 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.11 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.25 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_uniform.xml stereovision3.v common 1.53 0.05 9324 4 0.15 -1 -1 32996 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25704 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 370 0.13 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.19 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_delta.xml stereovision3.v common 1.52 0.05 9332 4 0.16 -1 -1 32980 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26332 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 365 0.14 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.21 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_uniform_y_delta.xml stereovision3.v common 1.42 0.04 9484 4 0.14 -1 -1 33052 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26116 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.12 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.16 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 4ea8edf62a9..aa93381d5b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.14 0.03 9272 4 0.10 -1 -1 33200 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.10 1.93141 -141.327 -1.93141 10 278 24 1.07788e+06 1.02399e+06 -1 -1 0.14 269 19 473 930 51635 19952 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 -nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.03 0.04 9284 4 0.14 -1 -1 33136 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 397 0.06 1.93141 -141.327 -1.93141 14 277 19 1.07788e+06 1.02399e+06 -1 -1 0.09 268 25 443 969 53893 20310 1.93141 -141.327 -1.93141 0 0 -1 -1 0.03 -nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.12 0.05 9304 4 0.13 -1 -1 33004 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25308 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 426 0.06 1.93141 -141.327 -1.93141 14 302 17 1.07788e+06 1.02399e+06 -1 -1 0.08 301 17 408 911 50388 19833 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.65 0.06 9332 4 0.15 -1 -1 32980 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25460 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.11 1.93141 -141.327 -1.93141 10 280 19 1.07788e+06 1.02399e+06 -1 -1 0.17 270 21 623 1237 68382 26000 1.93141 -141.327 -1.93141 0 0 -1 -1 0.05 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.66 0.04 9332 4 0.15 -1 -1 33028 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25276 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 397 0.12 1.93141 -141.327 -1.93141 14 275 26 1.07788e+06 1.02399e+06 -1 -1 0.18 268 31 572 1220 67739 25259 1.93141 -141.327 -1.93141 0 0 -1 -1 0.07 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.47 0.05 9320 4 0.14 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25376 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 426 0.10 1.93141 -141.327 -1.93141 14 307 16 1.07788e+06 1.02399e+06 -1 -1 0.14 304 17 558 1204 67109 26114 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 03592ae360c..9ad3391d09b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml stereovision3.v common 1.12 0.02 8736 4 0.13 -1 -1 33008 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22172 11 30 262 292 2 110 54 6 6 36 clb auto 0.11 381 0.05 2.26562 -157.07 -2.26562 34 760 33 862304 700622 62337.4 1731.59 0.19 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.02 +k6_frac_N10_40nm.xml stereovision3.v common 1.81 0.04 8876 4 0.14 -1 -1 33064 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22068 11 30 262 292 2 110 54 6 6 36 clb auto 0.12 381 0.06 2.26562 -157.07 -2.26562 34 764 40 862304 700622 62337.4 1731.59 0.29 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 2a0b67754bb..040866a427e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm.xml diffeq.blif common 5.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47684 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.24 10133 1.50 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 2.95 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 -k4_N4_90nm.xml ex5p.blif common 13.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 41056 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.23 11365 1.08 6.2011 -272.5 -6.2011 34 15486 43 804782 771343 910617. 2064.89 10.60 13214 20 7563 24669 4289697 1119035 6.2011 -285.89 -6.2011 0 0 1.15594e+06 2621.17 0.77 -k4_N4_90nm.xml s298.blif common 8.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 56600 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.27 12944 1.73 11.3412 -87.4002 -11.3412 26 16841 26 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 5.04 15969 19 7557 34543 4267407 813984 11.3825 -88.9401 -11.3825 0 0 1.43821e+06 2127.53 0.88 +k4_N4_90nm.xml diffeq.blif common 11.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47468 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.38 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.49 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.89 +k4_N4_90nm.xml ex5p.blif common 23.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 44112 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.27 11365 1.81 6.2011 -272.5 -6.2011 36 14690 30 804782 771343 957936. 2172.19 18.82 13031 20 7558 24835 4031744 1002168 6.5642 -288.81 -6.5642 0 0 1.20592e+06 2734.52 1.36 +k4_N4_90nm.xml s298.blif common 17.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 55720 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.41 12944 2.92 11.3412 -87.4002 -11.3412 26 18082 37 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 11.23 16266 19 8684 41436 5277893 987865 11.5285 -89.8977 -11.5285 0 0 1.43821e+06 2127.53 1.70 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index a2b03c74342..9032f461e98 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.20 0.04 9588 5 0.11 -1 -1 33396 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 29120 11 30 313 321 2 114 56 7 7 49 clb auto 0.31 384 0.06 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.44 0.04 9500 5 0.14 -1 -1 33300 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 29076 11 30 313 321 2 114 56 7 7 49 clb auto 0.35 384 0.11 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 52dbd9c3a7c..5c2edaa907f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.46003 0.595 0.782256 -1 -1 0.57 0.757256 -1 1.46003 -1 1.07141 -1 2.17449 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.66026 -1 -1 0.268 3.18526 -1 1.30866 -1 3.30941 -1 -1.19188 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.31564 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.31564 -1 1.07141 -1 1.7816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.16427 -1 3.30941 -1 -1.46477 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 87cdc7fbc8b..6440841a9dc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.19 0.03 8956 3 0.20 -1 -1 36196 -1 -1 64 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30468 99 130 363 493 1 251 294 12 12 144 clb auto 0.10 631 0.18 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.16 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.97 0.04 9212 3 0.27 -1 -1 36240 -1 -1 64 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29748 99 130 363 493 1 251 294 12 12 144 clb auto 0.17 631 0.39 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index db2e8480e78..3f4919acaf4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.78 0.04 9304 4 0.10 -1 -1 33076 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 24028 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 0.93 0.07 9336 4 0.14 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24268 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 539a74acf5d..707f2c9ba36 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.82 0.05 9344 4 0.13 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25056 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.09 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.06 0.04 9472 4 0.15 -1 -1 33032 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24400 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index cc2ed9cb61b..df9b581009d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765552 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 333 0.78 6.34392 -68.6483 -6.34392 18 769 24 0 0 66239.6 946.281 0.29 683 17 322 1139 141511 78590 7.01253 -76.014 -7.01253 0 0 84868.6 1212.41 0.04 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 19.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765500 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 338 0.78 6.37916 -68.7252 -6.37916 18 722 18 0 0 66239.6 946.281 0.54 641 16 284 987 122407 67992 6.83552 -76.2255 -6.83552 0 0 84868.6 1212.41 0.04 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 31.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765288 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.59 333 1.42 6.34392 -68.6483 -6.34392 16 953 45 0 0 60092.3 858.461 1.73 730 17 380 1479 176321 92346 7.14809 -77.4881 -7.14809 0 0 74567.7 1065.25 0.07 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 31.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765580 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.52 338 1.43 6.37916 -68.7252 -6.37916 16 890 49 0 0 60092.3 858.461 1.60 722 17 358 1194 144422 78787 6.91544 -77 -6.91544 0 0 74567.7 1065.25 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 657f785364b..ce1694b5e1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.74 0.03 8988 3 0.24 -1 -1 36284 -1 52468 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30424 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 654 0.27 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.24 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.02 0.008733 0.2181 0.07312 0.7088 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.91 0.02 8588 15 0.29 -1 -1 34384 -1 55128 36 162 0 5 v8.0.0-rc1-1092-gb22604c1a success 44428 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.24 5302 0.78 19.6083 -1810.12 -19.6083 48 13097 37 1.21132e+07 3.92018e+06 756778. 2956.16 4.28 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.37 0.007854 0.3502 0.01663 0.6332 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.91 0.04 9028 3 0.28 -1 -1 36172 -1 52332 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29764 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 654 0.51 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.50 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.10 0.008811 0.2233 0.07246 0.7042 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 12.66 0.04 8648 15 0.39 -1 -1 34380 -1 55136 36 162 0 5 v8.0.0-rc1-1194-g64d9b2790 success 44228 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.38 5302 1.33 19.6083 -1810.12 -19.6083 48 13061 34 1.21132e+07 3.92018e+06 756778. 2956.16 6.74 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.56 0.007854 0.3502 0.01663 0.6332 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index b6530c4a927..bf1fcf5440e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.07 0.04 9284 4 0.15 -1 -1 33024 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25936 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.18 0.03 9592 5 0.14 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27756 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.07 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.40 0.05 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25496 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.07 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.75 0.05 9532 5 0.13 -1 -1 33276 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.36 380 0.14 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index ed32602935a..ae53077a65f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 16.76 0.18 29384 4 1.49 -1 -1 39764 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 70844 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.27 10711 2.14 4.0362 -2478.27 -4.0362 80 21050 37 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 9.38 19612 17 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.46 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 19.82 0.29 29640 4 1.60 -1 -1 39856 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 71364 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.30 10711 2.36 4.0362 -2478.27 -4.0362 76 23027 51 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 11.51 20051 17 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.55 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 80e16928c1b..fd9f173e71d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37728 8 63 748 811 0 474 151 13 13 169 clb auto 0.25 4714 0.43 3.70871 -159.069 -3.70871 6562 3107 11690 976222 174155 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15429 -179.259 -4.15429 0 0 0.24 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37616 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4726 0.61 3.89144 -158.648 -3.89144 6642 3324 12982 1030781 185339 6.63067e+06 4.31152e+06 558096. 3302.35 22 4.59291 -186.559 -4.59291 0 0 0.29 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37700 8 63 748 811 0 474 151 13 13 169 clb auto 0.44 4714 0.79 3.70871 -159.069 -3.70871 6703 4263 15313 1252438 219655 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15304 -182.999 -4.15304 0 0 0.48 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37376 8 63 748 811 0 474 151 13 13 169 clb auto 0.43 4726 0.96 3.89144 -158.648 -3.89144 6985 4100 15083 1207360 214092 6.63067e+06 4.31152e+06 558096. 3302.35 26 4.16831 -189.499 -4.16831 0 0 0.49 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 2e34bd63c2b..bac71dd39b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -slicem.xml carry_chain.blif common 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19472 1 1 69 49 1 47 8 5 5 25 BLK_IG-SLICEM auto 0.15 102 0.01 0.764286 -10.588 -0.764286 25 401 35 133321 88880.4 -1 -1 0.34 409 22 194 196 56704 26791 3.01746 -35.9539 -3.01746 0 0 -1 -1 0.02 +slicem.xml carry_chain.blif common 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.15 65 0.02 0.55434 -5.54475 -0.55434 25 164 11 59253.6 59253.6 -1 -1 0.13 197 19 159 159 29188 17227 1.32558 -14.0361 -1.32558 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index d3cbcf7a149..efe434968ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -arch.xml ndff.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18404 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.01 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 +arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18452 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.02 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 25040fd3f74..7fe2eb3ff2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 0.96 0.03 9444 5 0.12 -1 -1 33316 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27692 11 30 313 321 2 114 56 7 7 49 clb auto 0.22 384 0.06 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.01 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.38 0.04 9548 5 0.13 -1 -1 33284 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27844 11 30 313 321 2 114 56 7 7 49 clb auto 0.34 384 0.13 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index b365cb947f3..64869255b58 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23308 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.738757 -2.61951 -0.738757 8 22 7 323364 161682 9037.03 361.481 0.02 17 7 20 20 554 322 0.756339 -2.63886 -0.756339 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23504 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 27 0.01 0.571 0 0 8 36 4 323364 161682 9037.03 361.481 0.02 45 3 12 12 990 624 0.571 0 0 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23260 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.02 0.570641 -1.88754 -0.570641 6 13 10 323364 161682 7009.75 280.390 0.01 19 1 8 8 231 149 0.592131 -2.24748 -0.592131 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23468 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.57064 -4.87629 -1.57064 8 35 26 323364 161682 9037.03 361.481 0.02 26 7 24 24 700 407 1.58926 -5.4843 -1.58926 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23420 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.37401 -2.68253 -1.37401 6 26 13 323364 161682 7009.75 280.390 0.01 30 2 13 13 598 378 1.3955 -2.70755 -1.3955 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23408 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 0.0706414 0 0 6 19 1 323364 161682 7009.75 280.390 0.01 21 1 8 8 286 184 0.0715255 0 0 0 0 9037.03 361.481 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23348 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.738757 -2.61951 -0.738757 8 23 8 107788 107788 4794.78 299.674 0.01 32 4 14 14 735 589 0.739641 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23268 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 19 0.01 0.571 0 0 8 30 6 107788 107788 4794.78 299.674 0.01 23 4 13 13 349 215 0.571 0 0 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23240 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.569757 -1.88754 -0.569757 8 26 4 107788 107788 4794.78 299.674 0.01 18 8 24 24 632 426 0.681776 -2.31791 -0.681776 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23096 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 1.56976 -4.87541 -1.56976 8 25 11 107788 107788 4794.78 299.674 0.01 17 4 11 11 300 189 1.57153 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23392 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 1.37313 -2.68253 -1.37313 6 24 4 107788 107788 3417.33 213.583 0.01 18 2 10 10 290 190 1.39454 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22904 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.0697572 0 0 8 22 3 107788 107788 4794.78 299.674 0.01 32 5 15 15 764 607 0.0724097 0 0 0 0 5401.54 337.596 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index e31b123c31a..10bc179e6ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.83 0.01 5868 1 0.00 -1 -1 29844 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24252 9 8 74 69 1 33 20 5 5 25 clb auto 0.45 71 0.02 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.03 141 10 97 117 3917 2091 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.00 13 16 19 7 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.18 0.00 5932 1 0.01 -1 -1 29864 -1 -1 2 11 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24476 11 10 107 96 1 44 23 4 4 16 clb auto 2.81 96 0.02 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.05 137 14 148 202 5606 3428 3.73364 -44.2193 -3.73364 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 2.43 0.00 6032 1 0.01 -1 -1 30192 -1 -1 2 13 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24616 13 12 148 128 1 59 27 4 4 16 clb auto 1.97 132 0.02 3.01831 -41.2936 -3.01831 36 280 46 50403.8 50403.8 22423.4 1401.47 0.06 189 14 189 223 6865 4126 3.49231 -57.8176 -3.49231 0 0 28178.5 1761.16 0.01 19 36 42 9 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 1.91 0.00 6148 1 0.01 -1 -1 29872 -1 -1 5 15 0 -1 v8.0.0-rc1-1092-gb22604c1a success 25536 15 14 195 164 1 87 34 5 5 25 clb auto 1.24 270 0.05 3.1163 -51.6217 -3.1163 44 573 24 151211 126010 54748.7 2189.95 0.17 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.22 0.00 6204 1 0.01 -1 -1 30020 -1 -1 7 17 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26060 17 16 250 205 1 114 40 6 6 36 clb auto 1.64 361 0.06 3.26818 -53.849 -3.26818 52 707 33 403230 176413 110337. 3064.92 0.12 578 17 549 859 33650 13481 4.24968 -85.1999 -4.24968 0 0 143382. 3982.83 0.02 52 64 75 13 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 2.82 0.00 6152 1 0.01 -1 -1 30212 -1 -1 7 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26408 19 18 307 248 1 141 44 6 6 36 clb auto 1.97 436 0.10 4.13322 -71.9714 -4.13322 60 926 18 403230 176413 127342. 3537.27 0.23 689 20 677 1075 39870 15591 5.49585 -110.351 -5.49585 0 0 157803. 4383.41 0.02 58 81 93 14 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5956 1 0.01 -1 -1 29680 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23860 9 8 74 69 1 33 20 5 5 25 clb auto 0.62 71 0.04 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.05 141 11 100 122 4102 2193 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.01 13 16 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.68 0.01 6032 1 0.01 -1 -1 29860 -1 -1 2 11 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23724 11 10 107 96 1 44 23 4 4 16 clb auto 4.08 96 0.04 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.08 156 18 168 232 6556 3975 3.32273 -45.5748 -3.32273 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.64 0.01 6012 1 0.01 -1 -1 30336 -1 -1 2 13 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24260 13 12 148 128 1 59 27 4 4 16 clb auto 2.98 132 0.05 3.01831 -41.2936 -3.01831 38 239 23 50403.8 50403.8 23356.0 1459.75 0.14 182 14 192 219 6796 4029 3.25531 -54.787 -3.25531 0 0 29887.0 1867.94 0.02 19 36 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.86 0.01 6184 1 0.01 -1 -1 29916 -1 -1 5 15 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24724 15 14 195 164 1 87 34 5 5 25 clb auto 2.08 270 0.08 3.1163 -51.6217 -3.1163 44 537 26 151211 126010 54748.7 2189.95 0.18 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 3.48 0.01 6120 1 0.01 -1 -1 29956 -1 -1 7 17 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 25948 17 16 250 205 1 114 40 6 6 36 clb auto 2.56 361 0.11 3.26818 -53.849 -3.26818 52 742 23 403230 176413 110337. 3064.92 0.22 590 21 594 946 37002 14662 4.43 -86.7352 -4.43 0 0 143382. 3982.83 0.03 52 64 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.26 0.01 6412 1 0.02 -1 -1 30328 -1 -1 7 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26428 19 18 307 248 1 141 44 6 6 36 clb auto 3.17 436 0.14 4.13322 -71.9714 -4.13322 60 1014 29 403230 176413 127342. 3537.27 0.32 692 21 740 1202 45108 17377 5.26938 -108.577 -5.26938 0 0 157803. 4383.41 0.04 58 81 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index a6acf55e9fb..08fe0f39203 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.07 0.04 8800 3 0.30 -1 -1 42064 -1 -1 14 99 1 0 v8.0.0-rc1-1400-ge1ff30c2f success 64320 99 74 307 381 1 199 188 8 8 64 io memory auto 0.07 648 0.38 1.95184 -194.143 -1.95184 42 1177 26 2.23746e+06 1.30252e+06 130676. 2041.82 0.52 1062 13 720 1013 147980 53129 2.28165 -213.94 -2.28165 0 0 165046. 2578.84 0.06 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.26 0.05 9016 3 0.29 -1 -1 36168 -1 -1 14 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 26796 99 74 307 381 1 199 188 8 8 64 io memory auto 0.08 647 0.30 1.9311 -196.847 -1.9311 34 1358 46 2.23746e+06 1.30252e+06 111309. 1739.21 0.67 1092 28 827 1194 140107 49979 2.25027 -229.924 -2.25027 0 0 136889. 2138.88 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 7d751a2b093..2e1804264a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -EArch.xml styr.blif common_--target_ext_pin_util_1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26940 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.78 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27172 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.09 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.15 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33272 10 10 168 178 1 162 110 14 14 196 clb auto 0.39 1408 0.18 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.22 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27648 10 10 168 178 1 73 33 7 7 49 clb auto 0.14 357 0.06 2.19476 -24.8471 -2.19476 28 1161 45 1.07788e+06 700622 79600.7 1624.51 0.29 876 17 434 1600 76377 28777 3.12807 -34.6232 -3.12807 0 0 95067.4 1940.15 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33424 10 10 168 178 1 163 121 14 14 196 clb auto 0.58 1381 0.20 2.72722 -32.4843 -2.72722 20 2827 12 9.20055e+06 5.44329e+06 295730. 1508.82 0.09 2752 15 536 2083 128119 32657 3.60179 -43.9525 -3.60179 0 0 387483. 1976.95 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26880 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.10 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26748 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 1.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33392 10 10 168 178 1 162 110 14 14 196 clb auto 0.50 1408 0.21 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.24 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26848 10 10 168 178 1 74 31 6 6 36 clb auto 0.12 375 0.06 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.13 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23284 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23536 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23704 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23408 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1 0.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26888 10 10 168 178 1 74 31 6 6 36 clb auto 0.22 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27080 10 10 168 178 1 74 31 6 6 36 clb auto 0.21 375 0.11 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.21 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33320 10 10 168 178 1 162 110 14 14 196 clb auto 0.67 1408 0.38 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.39 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27564 10 10 168 178 1 73 33 7 7 49 clb auto 0.20 357 0.09 2.19476 -24.8471 -2.19476 26 1076 29 1.07788e+06 700622 75813.7 1547.22 0.56 893 24 615 2230 111320 40005 2.71043 -34.388 -2.71043 0 0 91376.6 1864.83 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33408 10 10 168 178 1 163 121 14 14 196 clb auto 0.81 1381 0.41 2.72722 -32.4843 -2.72722 20 2801 19 9.20055e+06 5.44329e+06 295730. 1508.82 0.18 2742 15 598 2202 137075 34724 3.60179 -43.907 -3.60179 0 0 387483. 1976.95 0.06 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27236 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27208 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33072 10 10 168 178 1 162 110 14 14 196 clb auto 0.69 1408 0.39 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.42 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.08 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26956 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23764 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23680 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23584 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23892 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index ca2c1ef5b3e..9a3389c2249 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.34 0.03 8980 3 0.20 -1 -1 36172 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29976 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.27 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.27 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.03 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.25 0.04 9196 3 0.25 -1 -1 36188 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29304 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 655 0.50 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.46 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 6280904abf3..79087b62319 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24860 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24700 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24996 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24868 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24876 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24552 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index 8aa53db08b8..7d46687cffd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.05 42 753 0 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 1011288 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 9.57 80370 40.19 4.8494 -14201.6 -4.8494 83423 24866 32259 28860263 3251424 0 0 2.17765e+07 19254.2 13 4.97188 -15343.1 -4.97188 0 0 3.30 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 80.16 42 753 0 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 1011024 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 15.84 80370 38.02 4.8494 -14201.6 -4.8494 83215 26269 34662 30836512 3446780 0 0 2.17765e+07 19254.2 13 4.97188 -15454.7 -4.97188 0 0 3.51 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 2532b379d5b..835e38df2df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 8.59 0.01 8828 6 0.09 -1 -1 34012 -1 -1 15 66 0 -1 v8.0.0-rc1-1092-gb22604c1a success 53224 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.14 4812 0.76 14.7278 -819.907 -14.7278 62 11943 18 6.4517e+06 1.13409e+06 1.72337e+06 5319.03 5.17 10760 17 3483 7402 3135131 764282 16.6282 -1030.56 -16.6282 0 0 2.10074e+06 6483.76 0.52 135 200 146 33 66 33 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 15.76 0.02 8916 6 0.12 -1 -1 34112 -1 -1 15 66 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 46780 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.61 4812 1.39 14.7278 -819.907 -14.7278 60 12276 35 6.4517e+06 1.13409e+06 1.66893e+06 5151.03 9.76 10886 40 3329 7348 3578053 1134156 16.8599 -1041.74 -16.8599 0 0 2.06264e+06 6366.18 1.40 135 200 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 9afc4c5ccd7..580d216346d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 23148 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.00 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 22972 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.01 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23616 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 -1 734 954 51286 35882 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.02 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23468 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 138 734 954 51286 35882 323364 161682 9037.03 361.481 -1 1.57884 -20.2194 -1.57884 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22676 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.04 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23216 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.01 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23648 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 -1 761 989 53376 36845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.04 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23284 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 139 761 989 53376 36845 323364 161682 9037.03 361.481 -1 1.66401 -20.8061 -1.66401 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 5af3c158894..60b71a0b84b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N4_90nm.xml stereovision3.v common 4.92 0.03 8728 6 0.15 -1 -1 33160 -1 -1 66 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 23608 11 30 336 366 2 186 107 11 11 121 clb auto 0.04 1075 0.11 3.34892 -239.501 -3.34892 995 849 2411 331915 45511 180575 147135 597941. 4941.66 13 3.34892 -248.18 -3.34892 -0.21991 -0.0734 0.05 -k6_frac_N10_40nm.xml stereovision3.v common 2.21 0.02 8852 4 0.14 -1 -1 33044 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22544 11 30 262 292 2 110 54 6 6 36 clb auto 0.08 366 0.07 2.26563 -155.916 -2.26563 467 182 317 10207 3363 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.01 +k4_N4_90nm.xml stereovision3.v common 7.18 0.04 8836 6 0.17 -1 -1 33036 -1 -1 66 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 23748 11 30 336 366 2 186 107 11 11 121 clb auto 0.06 1075 0.19 3.34892 -239.501 -3.34892 1023 868 2391 322050 43514 180575 147135 597941. 4941.66 13 3.34892 -247.922 -3.34892 -0.21991 -0.0734 0.09 +k6_frac_N10_40nm.xml stereovision3.v common 3.08 0.03 8864 4 0.16 -1 -1 33036 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22576 11 30 262 292 2 110 54 6 6 36 clb auto 0.13 366 0.14 2.26563 -155.916 -2.26563 467 183 320 10273 3381 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 5f206f5e1fd..afa3dc97a2e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -53,3 +53,4 @@ regression_tests/vtr_reg_strong/strong_sdc regression_tests/vtr_reg_strong/strong_timing_report_detail regression_tests/vtr_reg_strong/strong_route_reconverge regression_tests/vtr_reg_strong/strong_equivalent_sites +regression_tests/vtr_reg_strong/strong_absorb_buffers