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Merge branches 'wip/add-issue-template', 'wip/lookahead_sampling2', 'wip/symbiflow-badger' and 'wip/update_golden' into new-master-wip
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‎.github/ISSUE_TEMPLATE/bug_report.md

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---
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name: Bug report
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about: Create a report to help us improve
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title: ''
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labels: ''
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assignees: ''
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---
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‎.github/ISSUE_TEMPLATE/feature_request.md

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---
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name: Feature request
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about: Suggest an idea for this project
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title: ''
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labels: ''
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assignees: ''
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‎.github/ISSUE_TEMPLATE/vtr-change.md

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---
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name: VTR change
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about: Describe purpose and lifecycle of a local change we made to VTR
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title: ''
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labels: ''
6+
assignees: ''
7+
8+
---
9+
10+
### Why did we need this? (what does this change enable us to do)
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<!--- i.e. what does this change enable us to do? -->
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13+
### What did it change?
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<!--- i.e. technical description what the change does -->
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### Should it be merged upstream - if not, when can we delete it?
17+
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### What is needed to get this merged / deleted?
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* [ ] is the implementation work to make suitable for merging / deletion completed?
21+
* [ ] Is there an associated test? <!--- i.e. how will we prevent it from regressing? -->
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* [ ] is this currently part of the Conda package?
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* [ ] is this properly cleaned up in our local repositories? <!--- add subtasks here if needed) -->
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25+
### Tracker / branch / PR & other useful links

‎README.md

Lines changed: 10 additions & 1 deletion
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@@ -1,5 +1,14 @@
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SymbiFlow WIP changes for Verilog to Routing (VTR)
3+
==================================================
4+
5+
This branch contains work in progress changes for using Verilog to Routing
6+
(VTR) as part of SymbiFlow.
7+
8+
---
9+
110
# Verilog to Routing (VTR)
2-
[![Build Status](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/)
11+
[![Build Status](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
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## Introduction
514
The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.

‎libs/libarchfpga/src/physical_types.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1438,6 +1438,7 @@ struct t_arch_switch_inf {
14381438
float Cin = 0.;
14391439
float Cout = 0.;
14401440
float Cinternal = 0.;
1441+
float penalty_cost = 0.;
14411442
float mux_trans_size = 1.;
14421443
BufferSize buf_size_type = BufferSize::AUTO;
14431444
float buf_size = 0.;
@@ -1502,6 +1503,7 @@ struct t_rr_switch_inf {
15021503
float Cout = 0.;
15031504
float Cinternal = 0.;
15041505
float Tdel = 0.;
1506+
float penalty_cost = 0.;
15051507
float mux_trans_size = 0.;
15061508
float buf_size = 0.;
15071509
const char* name = nullptr;

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3945,23 +3945,23 @@ static void ProcessSwitches(pugi::xml_node Parent,
39453945
SwitchType type = SwitchType::MUX;
39463946
if (0 == strcmp(type_name, "mux")) {
39473947
type = SwitchType::MUX;
3948-
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
3948+
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
39493949

39503950
} else if (0 == strcmp(type_name, "tristate")) {
39513951
type = SwitchType::TRISTATE;
3952-
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
3952+
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
39533953

39543954
} else if (0 == strcmp(type_name, "buffer")) {
39553955
type = SwitchType::BUFFER;
3956-
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
3956+
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
39573957

39583958
} else if (0 == strcmp(type_name, "pass_gate")) {
39593959
type = SwitchType::PASS_GATE;
3960-
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type '"s + type_name + "'"s, loc_data);
3960+
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type '"s + type_name + "'"s, loc_data);
39613961

39623962
} else if (0 == strcmp(type_name, "short")) {
39633963
type = SwitchType::SHORT;
3964-
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type "s + type_name + "'"s, loc_data);
3964+
expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type "s + type_name + "'"s, loc_data);
39653965
} else {
39663966
archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
39673967
"Invalid switch type '%s'.\n", type_name);
@@ -3984,6 +3984,7 @@ static void ProcessSwitches(pugi::xml_node Parent,
39843984
arch_switch.Cin = get_attribute(Node, "Cin", loc_data, CIN_REQD).as_float(0);
39853985
arch_switch.Cout = get_attribute(Node, "Cout", loc_data, COUT_REQD).as_float(0);
39863986
arch_switch.Cinternal = get_attribute(Node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0);
3987+
arch_switch.penalty_cost = get_attribute(Node, "penalty_cost", loc_data, ReqOpt::OPTIONAL).as_float(0);
39873988

39883989
if (arch_switch.type() == SwitchType::MUX) {
39893990
//Only muxes have mux transistors

‎libs/libvtrcapnproto/CMakeLists.txt

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@@ -19,6 +19,7 @@ endif()
1919
# Each schema used should appear here.
2020
set(CAPNP_DEFS
2121
place_delay_model.capnp
22+
connection_map.capnp
2223
matrix.capnp
2324
gen/rr_graph_uxsdcxx.capnp
2425
map_lookahead.capnp

‎libs/libvtrcapnproto/connection_map.capnp

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@@ -0,0 +1,25 @@
1+
@0x876ec83c2fea5a18;
2+
3+
using Matrix = import "matrix.capnp";
4+
5+
struct VprCostEntry {
6+
delay @0 :Float32;
7+
congestion @1 :Float32;
8+
fill @2 :Bool;
9+
}
10+
11+
struct VprVector2D {
12+
x @0 :Int64;
13+
y @1 :Int64;
14+
}
15+
16+
struct VprFloatEntry {
17+
value @0 :Float32;
18+
}
19+
20+
struct VprCostMap {
21+
costMap @0 :Matrix.Matrix((Matrix.Matrix(VprCostEntry)));
22+
offset @1 :Matrix.Matrix(VprVector2D);
23+
depField @2 :List(Int64);
24+
penalty @3 :Matrix.Matrix(VprFloatEntry);
25+
}

‎libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp

Lines changed: 35 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,11 @@
22
# https://github.com/duck2/uxsdcxx
33
# Modify only if your build process doesn't involve regenerating this file.
44
#
5-
# Cmdline: uxsdcxx/uxsdcap.py /home/kmurray/trees/vtr/vpr/src/route/rr_graph.xsd
6-
# Input file: /home/kmurray/trees/vtr/vpr/src/route/rr_graph.xsd
7-
# md5sum of input file: 40e83d2ea6556761d4e29f21324b1871
5+
# Cmdline: uxsdcxx/uxsdcap.py rr_graph.xsd
6+
# Input file: rr_graph.xsd
7+
# md5sum of input file: d9e439fa173fdf56b51feeed0ac48272
88

9-
@0xb803100e76d3342d;
9+
@0xa90e1cca7f71265c;
1010
using Cxx = import "/capnp/c++.capnp";
1111
$Cxx.namespace("ucap");
1212

@@ -81,6 +81,7 @@ struct Timing {
8181
cout @2 :Float32;
8282
r @3 :Float32;
8383
tdel @4 :Float32;
84+
penaltyCost @5 :Float32;
8485
}
8586

8687
struct Sizing {
@@ -137,6 +138,18 @@ struct BlockTypes {
137138
blockTypes @0 :List(BlockType);
138139
}
139140

141+
struct ConnectionBoxDeclaration {
142+
id @0 :UInt32;
143+
name @1 :Text;
144+
}
145+
146+
struct ConnectionBoxes {
147+
numBoxes @0 :UInt32;
148+
xDim @1 :UInt32;
149+
yDim @2 :UInt32;
150+
connectionBoxes @3 :List(ConnectionBoxDeclaration);
151+
}
152+
140153
struct GridLoc {
141154
blockTypeId @0 :Int32;
142155
heightOffset @1 :Int32;
@@ -176,6 +189,18 @@ struct Metadata {
176189
metas @0 :List(Meta);
177190
}
178191

192+
struct CanonicalLoc {
193+
x @0 :UInt32;
194+
y @1 :UInt32;
195+
}
196+
197+
struct ConnectionBoxAnnotation {
198+
id @0 :UInt32;
199+
sitePinDelay @1 :Float32;
200+
x @2 :UInt32;
201+
y @3 :UInt32;
202+
}
203+
179204
struct Node {
180205
capacity @0 :UInt32;
181206
direction @1 :NodeDirection;
@@ -185,6 +210,8 @@ struct Node {
185210
timing @5 :NodeTiming;
186211
segment @6 :NodeSegment;
187212
metadata @7 :Metadata;
213+
canonicalLoc @8 :CanonicalLoc;
214+
connectionBox @9 :ConnectionBoxAnnotation;
188215
}
189216

190217
struct RrNodes {
@@ -210,7 +237,8 @@ struct RrGraph {
210237
switches @4 :Switches;
211238
segments @5 :Segments;
212239
blockTypes @6 :BlockTypes;
213-
grid @7 :GridLocs;
214-
rrNodes @8 :RrNodes;
215-
rrEdges @9 :RrEdges;
240+
connectionBoxes @7 :ConnectionBoxes;
241+
grid @8 :GridLocs;
242+
rrNodes @9 :RrNodes;
243+
rrEdges @10 :RrEdges;
216244
}

‎vpr/src/base/SetupVPR.cpp

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Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ void SetupVPR(const t_options* Options,
156156
}
157157

158158
Segments = Arch->Segments;
159+
device_ctx.segment_inf = Arch->Segments;
159160

160161
SetupSwitches(*Arch, RoutingArch, Arch->Switches, Arch->num_switches);
161162
SetupRoutingArch(*Arch, RoutingArch);
@@ -281,6 +282,7 @@ static void SetupSwitches(const t_arch& Arch,
281282
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].R = 0.;
282283
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cin = 0.;
283284
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cout = 0.;
285+
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].penalty_cost = 0.;
284286
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.);
285287
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE;
286288
device_ctx.arch_switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.;

‎vpr/src/base/echo_files.cpp

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Original file line numberDiff line numberDiff line change
@@ -114,6 +114,8 @@ void alloc_and_load_echo_file_info() {
114114
setEchoFileName(E_ECHO_CHAN_DETAILS, "chan_details.txt");
115115
setEchoFileName(E_ECHO_SBLOCK_PATTERN, "sblock_pattern.txt");
116116
setEchoFileName(E_ECHO_ENDPOINT_TIMING, "endpoint_timing.echo.json");
117+
118+
setEchoFileName(E_ECHO_LOOKAHEAD_MAP, "lookahead_map.echo");
117119
}
118120

119121
void free_echo_file_info() {

‎vpr/src/base/echo_files.h

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Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ enum e_echo_files {
4646
E_ECHO_CHAN_DETAILS,
4747
E_ECHO_SBLOCK_PATTERN,
4848
E_ECHO_ENDPOINT_TIMING,
49+
E_ECHO_LOOKAHEAD_MAP,
4950

5051
//Timing Graphs
5152
E_ECHO_PRE_PACKING_TIMING_GRAPH,

‎vpr/src/base/read_options.cpp

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -692,6 +692,8 @@ struct ParseRouterLookahead {
692692
conv_value.set_value(e_router_lookahead::CLASSIC);
693693
else if (str == "map")
694694
conv_value.set_value(e_router_lookahead::MAP);
695+
else if (str == "connection_box_map")
696+
conv_value.set_value(e_router_lookahead::CONNECTION_BOX_MAP);
695697
else {
696698
std::stringstream msg;
697699
msg << "Invalid conversion from '"
@@ -705,17 +707,22 @@ struct ParseRouterLookahead {
705707

706708
ConvertedValue<std::string> to_str(e_router_lookahead val) {
707709
ConvertedValue<std::string> conv_value;
708-
if (val == e_router_lookahead::CLASSIC)
710+
if (val == e_router_lookahead::CLASSIC) {
709711
conv_value.set_value("classic");
710-
else {
711-
VTR_ASSERT(val == e_router_lookahead::MAP);
712+
} else if (val == e_router_lookahead::MAP) {
712713
conv_value.set_value("map");
714+
} else if (val == e_router_lookahead::CONNECTION_BOX_MAP) {
715+
conv_value.set_value("connection_box_map");
716+
} else {
717+
std::stringstream msg;
718+
msg << "Unrecognized e_router_lookahead";
719+
conv_value.set_error(msg.str());
713720
}
714721
return conv_value;
715722
}
716723

717724
std::vector<std::string> default_choices() {
718-
return {"classic", "map"};
725+
return {"classic", "map", "connection_box_map"};
719726
}
720727
};
721728

‎vpr/src/base/vpr_context.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@
2424
#include "place_macro.h"
2525
#include "compressed_grid.h"
2626
#include "metadata_storage.h"
27+
#include "connection_box.h"
2728

2829
//A Context is collection of state relating to a particular part of VPR
2930
//
@@ -160,6 +161,7 @@ struct DeviceContext : public Context {
160161
t_rr_node_indices rr_node_indices; //[0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1]
161162

162163
std::vector<t_rr_switch_inf> rr_switch_inf; /* autogenerated in build_rr_graph based on switch fan-in. [0..(num_rr_switches-1)] */
164+
std::vector<t_segment_inf> segment_inf;
163165

164166
//Wire segment types in RR graph
165167
std::vector<t_segment_inf> rr_segments;
@@ -212,6 +214,8 @@ struct DeviceContext : public Context {
212214
// Name of rrgraph file read (if any).
213215
// Used to determine when reading rrgraph if file is already loaded.
214216
std::string read_rr_graph_filename;
217+
218+
ConnectionBoxes connection_boxes;
215219
};
216220

217221
//State relating to power analysis

‎vpr/src/base/vpr_types.h

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,10 @@ constexpr const char* EMPTY_BLOCK_NAME = "EMPTY";
108108
enum class e_router_lookahead {
109109
CLASSIC, //VPR's classic lookahead (assumes uniform wire types)
110110
MAP, //Lookahead considering different wire types (see Oleg Petelin's MASc Thesis)
111-
NO_OP //A no-operation lookahead which always returns zero
111+
NO_OP, //A no-operation lookahead which always returns zero
112+
CONNECTION_BOX_MAP,
113+
// Lookahead considering different wire types and IPIN
114+
// connection box.
112115
};
113116

114117
enum class e_route_bb_update {

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