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Enable faster rr graph reading
 - Add option to disable checking the rr graph. This check is relatively expensive (~12 seconds), and generates MB's of warnings that we ignore. - Disable loading edge metadata when running normal VPR flows. - Avoid copying rr node side string. Signed-off-by: Keith Rothman <[email protected]>
1 parent c26370e commit 8fa2b49

13 files changed

+61
-27
lines changed

‎utils/fasm/src/main.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ int main(int argc, const char **argv) {
7272
vpr_setup.PackerOpts.doPacking = STAGE_LOAD;
7373
vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD;
7474
vpr_setup.RouterOpts.doRouting = STAGE_LOAD;
75+
vpr_setup.RouterOpts.read_edge_metadata = true;
7576
vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP;
7677

7778
bool flow_succeeded = false;

‎vpr/src/base/SetupVPR.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -322,6 +322,7 @@ static void SetupRoutingArch(const t_arch& Arch,
322322
}
323323

324324
static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {
325+
RouterOpts->do_check_rr_graph = !Options.disable_check_rr_graph;
325326
RouterOpts->astar_fac = Options.astar_fac;
326327
RouterOpts->bb_factor = Options.bb_factor;
327328
RouterOpts->criticality_exp = Options.criticality_exp;

‎vpr/src/base/place_and_route.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,9 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref,
357357
router_opts.trim_obs_channels,
358358
router_opts.clock_modeling,
359359
arch->Directs, arch->num_directs,
360-
&warnings);
360+
&warnings,
361+
router_opts.read_edge_metadata,
362+
router_opts.do_check_rr_graph);
361363

362364
init_draw_coords(final);
363365
restore_routing(best_routing, route_ctx.clb_opins_used_locally, saved_clb_opins_used_locally);

‎vpr/src/base/read_options.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1642,6 +1642,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
16421642
.default_value("-2")
16431643
.show_in(argparse::ShowIn::HELP_ONLY);
16441644

1645+
route_timing_grp.add_argument<bool, ParseOnOff>(args.disable_check_rr_graph, "--disable_check_rr_graph")
1646+
.help("Disables checking rr graph when reading from disk.")
1647+
.default_value("off")
1648+
.show_in(argparse::ShowIn::HELP_ONLY);
1649+
16451650
auto& analysis_grp = parser.add_argument_group("analysis options");
16461651

16471652
analysis_grp.add_argument<bool, ParseOnOff>(args.full_stats, "--full_stats")

‎vpr/src/base/read_options.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,7 @@ struct t_options {
119119
argparse::ArgValue<std::string> allowed_tiles_for_delay_model;
120120

121121
/* Router Options */
122+
argparse::ArgValue<bool> disable_check_rr_graph;
122123
argparse::ArgValue<int> max_router_iterations;
123124
argparse::ArgValue<float> first_iter_pres_fac;
124125
argparse::ArgValue<float> initial_pres_fac;

‎vpr/src/base/vpr_api.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -849,7 +849,9 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
849849
router_opts.trim_obs_channels,
850850
router_opts.clock_modeling,
851851
arch.Directs, arch.num_directs,
852-
&warnings);
852+
&warnings,
853+
router_opts.read_edge_metadata,
854+
router_opts.do_check_rr_graph);
853855
//Initialize drawing, now that we have an RR graph
854856
init_draw_coords(chan_width_fac);
855857
}

‎vpr/src/base/vpr_types.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -905,6 +905,8 @@ enum class e_incr_reroute_delay_ripup {
905905
constexpr int NO_FIXED_CHANNEL_WIDTH = -1;
906906

907907
struct t_router_opts {
908+
bool read_edge_metadata = false;
909+
bool do_check_rr_graph = true;
908910
float first_iter_pres_fac;
909911
float initial_pres_fac;
910912
float pres_fac_mult;

‎vpr/src/route/route_common.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,9 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar
238238
router_opts.trim_obs_channels,
239239
router_opts.clock_modeling,
240240
directs, num_directs,
241-
&warning_count);
241+
&warning_count,
242+
router_opts.read_edge_metadata,
243+
router_opts.do_check_rr_graph);
242244
}
243245

244246
bool try_route(int width_fac,
@@ -288,7 +290,9 @@ bool try_route(int width_fac,
288290
router_opts.trim_obs_channels,
289291
router_opts.clock_modeling,
290292
directs, num_directs,
291-
&warning_count);
293+
&warning_count,
294+
router_opts.read_edge_metadata,
295+
router_opts.do_check_rr_graph);
292296

293297
//Initialize drawing, now that we have an RR graph
294298
init_draw_coords(width_fac);

‎vpr/src/route/router_delay_profiling.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,9 @@ void alloc_routing_structs(t_chan_width chan_width,
197197
router_opts.trim_obs_channels,
198198
router_opts.clock_modeling,
199199
directs, num_directs,
200-
&warnings);
200+
&warnings,
201+
router_opts.read_edge_metadata,
202+
router_opts.do_check_rr_graph);
201203

202204
alloc_and_load_rr_node_route_structs();
203205

‎vpr/src/route/rr_graph.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,9 @@ void create_rr_graph(const t_graph_type graph_type,
318318
const enum e_clock_modeling clock_modeling,
319319
const t_direct_inf* directs,
320320
const int num_directs,
321-
int* Warnings) {
321+
int* Warnings,
322+
bool read_edge_metadata,
323+
bool do_check_rr_graph) {
322324
const auto& device_ctx = g_vpr_ctx.device();
323325

324326
if (!det_routing_arch->read_rr_graph_filename.empty()) {
@@ -330,7 +332,9 @@ void create_rr_graph(const t_graph_type graph_type,
330332
segment_inf,
331333
base_cost_type,
332334
&det_routing_arch->wire_to_rr_ipin_switch,
333-
det_routing_arch->read_rr_graph_filename.c_str());
335+
det_routing_arch->read_rr_graph_filename.c_str(),
336+
read_edge_metadata,
337+
do_check_rr_graph);
334338
}
335339
} else {
336340
if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) {

‎vpr/src/route/rr_graph.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,9 @@ void create_rr_graph(const t_graph_type graph_type,
3838
const enum e_clock_modeling clock_modeling,
3939
const t_direct_inf* directs,
4040
const int num_directs,
41-
int* Warnings);
41+
int* Warnings,
42+
bool read_edge_metadata,
43+
bool do_check_rr_graph);
4244

4345
void free_rr_graph();
4446

‎vpr/src/route/rr_graph_reader.cpp

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5353
void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5454
void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid);
5555
void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
56-
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches);
56+
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata);
5757
void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5858
void process_rr_node_indices(const DeviceGrid& grid);
5959
void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
@@ -69,7 +69,9 @@ void load_rr_file(const t_graph_type graph_type,
6969
const std::vector<t_segment_inf>& segment_inf,
7070
const enum e_base_cost_type base_cost_type,
7171
int* wire_to_rr_ipin_switch,
72-
const char* read_rr_graph_name) {
72+
const char* read_rr_graph_name,
73+
bool read_edge_metadata,
74+
bool do_check_rr_graph) {
7375
vtr::ScopedStartFinishTimer timer("Loading routing resource graph");
7476

7577
const char* Prop;
@@ -154,7 +156,7 @@ void load_rr_file(const t_graph_type graph_type,
154156
process_switches(next_component, loc_data);
155157

156158
next_component = get_single_child(rr_graph, "rr_edges", loc_data);
157-
process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches);
159+
process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches, read_edge_metadata);
158160

159161
//Partition the rr graph edges for efficient access to configurable/non-configurable
160162
//edge subsets. Must be done after RR switches have been allocated
@@ -176,7 +178,9 @@ void load_rr_file(const t_graph_type graph_type,
176178
device_ctx.chan_width = nodes_per_chan;
177179
device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
178180

179-
check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
181+
if (do_check_rr_graph) {
182+
check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
183+
}
180184

181185
} catch (pugiutil::XmlError& e) {
182186
vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what());
@@ -336,15 +340,15 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
336340

337341
if (node.type() == IPIN || node.type() == OPIN) {
338342
e_side side;
339-
std::string side_str = get_attribute(locSubnode, "side", loc_data).as_string();
340-
if (side_str == "LEFT") {
343+
const char* side_str = get_attribute(locSubnode, "side", loc_data).as_string();
344+
if (strcmp(side_str, "LEFT") == 0) {
341345
side = LEFT;
342-
} else if (side_str == "RIGHT") {
346+
} else if (strcmp(side_str, "RIGHT") == 0) {
343347
side = RIGHT;
344-
} else if (side_str == "TOP") {
348+
} else if (strcmp(side_str, "TOP") == 0) {
345349
side = TOP;
346350
} else {
347-
VTR_ASSERT(side_str == "BOTTOM");
351+
VTR_ASSERT(strcmp(side_str, "BOTTOM") == 0);
348352
side = BOTTOM;
349353
}
350354
node.set_side(side);
@@ -388,7 +392,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
388392

389393
/*Loads the edges information from file into vpr. Nodes and switches must be loaded
390394
* before calling this function*/
391-
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches) {
395+
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata) {
392396
auto& device_ctx = g_vpr_ctx.mutable_device();
393397
pugi::xml_node edges;
394398

@@ -462,16 +466,18 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
462466
device_ctx.rr_nodes[source_node].set_edge_switch(num_edges_for_node[source_node], switch_id);
463467

464468
// Read the metadata for the edge
465-
auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL);
466-
if (metadata) {
467-
auto edges_meta = get_first_child(metadata, "meta", loc_data);
468-
while (edges_meta) {
469-
auto key = get_attribute(edges_meta, "name", loc_data).as_string();
469+
if (read_edge_metadata) {
470+
auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL);
471+
if (metadata) {
472+
auto edges_meta = get_first_child(metadata, "meta", loc_data);
473+
while (edges_meta) {
474+
auto key = get_attribute(edges_meta, "name", loc_data).as_string();
470475

471-
vpr::add_rr_edge_metadata(source_node, sink_node, switch_id,
472-
key, edges_meta.child_value());
476+
vpr::add_rr_edge_metadata(source_node, sink_node, switch_id,
477+
key, edges_meta.child_value());
473478

474-
edges_meta = edges_meta.next_sibling(edges_meta.name());
479+
edges_meta = edges_meta.next_sibling(edges_meta.name());
480+
}
475481
}
476482
}
477483
num_edges_for_node[source_node]++;

‎vpr/src/route/rr_graph_reader.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ void load_rr_file(const t_graph_type graph_type,
99
const std::vector<t_segment_inf>& segment_inf,
1010
const enum e_base_cost_type base_cost_type,
1111
int* wire_to_rr_ipin_switch,
12-
const char* read_rr_graph_name);
12+
const char* read_rr_graph_name,
13+
bool read_edge_metadata,
14+
bool do_check_rr_graph);
1315

1416
#endif /* RR_GRAPH_READER_H */

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