Merge branches 'add-c-internal', 'add-issue-template', 'avoid-criticality-issue', 'connection_box_cleanup', 'disable-check-route-option', 'symbiflow-badger', 'timing-graph-builder-fix' and 'rr-graph-binary-read-write' into master+wip

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,6 +1,9 @@
 ---
 name: Bug report
 about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
 
 ---
 

.github/ISSUE_TEMPLATE/feature_request.md

@@ -1,6 +1,9 @@
 ---
 name: Feature request
 about: Suggest an idea for this project
+title: ''
+labels: ''
+assignees: ''
 
 ---
 

.github/ISSUE_TEMPLATE/vtr-change.md

@@ -0,0 +1,25 @@
+---
+name: VTR change
+about: Describe purpose and lifecycle of a local change we made to VTR
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+### Why did we need this? (what does this change enable us to do)
+<!--- i.e. what does this change enable us to do? -->
+
+### What did it change?
+<!--- i.e. technical description what the change does -->
+
+### Should it be merged upstream - if not, when can we delete it?
+
+### What is needed to get this merged / deleted? 
+
+* [ ] is the implementation work to make suitable for merging / deletion completed?
+* [ ] Is there an associated test? <!--- i.e. how will we prevent it from regressing? -->
+* [ ] is this currently part of the Conda package?
+* [ ] is this properly cleaned up in our local repositories? <!--- add subtasks here if needed) -->
+
+### Tracker / branch / PR & other useful links

README.md

@@ -1,5 +1,14 @@
+
+SymbiFlow WIP changes for Verilog to Routing (VTR)
+==================================================
+
+This branch contains work in progress changes for using Verilog to Routing
+(VTR) as part of SymbiFlow.
+
+---
+
 # Verilog to Routing (VTR)
-[![Build Status](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
+[![Build Status](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
 
 ## Introduction
 The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.

vpr/src/base/SetupVPR.cpp

@@ -347,8 +347,8 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts)
     RouterOpts->max_convergence_count = Options.router_max_convergence_count;
     RouterOpts->reconvergence_cpd_threshold = Options.router_reconvergence_cpd_threshold;
     RouterOpts->first_iteration_timing_report_file = Options.router_first_iteration_timing_report_file;
-
     RouterOpts->strict_checks = Options.strict_checks;
+    RouterOpts->disable_check_route = Options.disable_check_route;
 }
 
 static void SetupAnnealSched(const t_options& Options,

vpr/src/base/echo_files.cpp

@@ -112,6 +112,8 @@ void alloc_and_load_echo_file_info() {
     setEchoFileName(E_ECHO_CHAN_DETAILS, "chan_details.txt");
     setEchoFileName(E_ECHO_SBLOCK_PATTERN, "sblock_pattern.txt");
     setEchoFileName(E_ECHO_ENDPOINT_TIMING, "endpoint_timing.echo.json");
+
+    setEchoFileName(E_ECHO_LOOKAHEAD_MAP, "lookahead_map.echo");
 }
 
 void free_echo_file_info() {

vpr/src/base/echo_files.h

@@ -43,6 +43,7 @@ enum e_echo_files {
     E_ECHO_CHAN_DETAILS,
     E_ECHO_SBLOCK_PATTERN,
     E_ECHO_ENDPOINT_TIMING,
+    E_ECHO_LOOKAHEAD_MAP,
 
     //Timing Graphs
     E_ECHO_PRE_PACKING_TIMING_GRAPH,

vpr/src/base/read_options.cpp

@@ -648,6 +648,8 @@ struct ParseRouterLookahead {
             conv_value.set_value(e_router_lookahead::CLASSIC);
         else if (str == "map")
             conv_value.set_value(e_router_lookahead::MAP);
+        else if (str == "connection_box_map")
+            conv_value.set_value(e_router_lookahead::CONNECTION_BOX_MAP);
         else {
             std::stringstream msg;
             msg << "Invalid conversion from '"
@@ -661,17 +663,22 @@ struct ParseRouterLookahead {
 
     ConvertedValue<std::string> to_str(e_router_lookahead val) {
         ConvertedValue<std::string> conv_value;
-        if (val == e_router_lookahead::CLASSIC)
+        if (val == e_router_lookahead::CLASSIC) {
             conv_value.set_value("classic");
-        else {
-            VTR_ASSERT(val == e_router_lookahead::MAP);
+        } else if (val == e_router_lookahead::MAP) {
             conv_value.set_value("map");
+        } else if (val == e_router_lookahead::CONNECTION_BOX_MAP) {
+            conv_value.set_value("connection_box_map");
+        } else {
+            std::stringstream msg;
+            msg << "Unrecognized e_router_lookahead";
+            conv_value.set_error(msg.str());
         }
         return conv_value;
     }
 
     std::vector<std::string> default_choices() {
-        return {"classic", "map"};
+        return {"classic", "map", "connection_box_map"};
     }
 };
 
@@ -949,6 +956,16 @@ static argparse::ArgumentParser create_arg_parser(std::string prog_name, t_optio
             "This option should be only used for development purposes.")
         .default_value("");
 
+    gen_grp.add_argument<bool, ParseOnOff>(args.allow_dangling_combinational_nodes, "--allow_dangling_combinational_nodes")
+        .help(
+            "Option to allow dangling combinational nodes in the timing graph.\n"
+            "This option should normally be off, as dangling combinational nodes are unusual\n"
+            "in the timing graph and may indicate a problem in the circuit or architecture.\n"
+            "Unless you understand why your architecture/circuit can have valid dangling combinational nodes, this option should be off.\n"
+            "In general this is a dev-only option and should not be turned on by the end-user.")
+        .default_value("off")
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     auto& file_grp = parser.add_argument_group("file options");
 
     file_grp.add_argument(args.BlifFile, "--circuit_file")
@@ -1551,6 +1568,11 @@ static argparse::ArgumentParser create_arg_parser(std::string prog_name, t_optio
         .default_value("")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
+    route_timing_grp.add_argument<bool, ParseOnOff>(args.disable_check_route, "--disable_check_route")
+        .help("Disables check_route once routing step has finished or when routing file is loaded")
+        .default_value("off")
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     route_timing_grp.add_argument(args.router_debug_net, "--router_debug_net")
         .help(
             "Controls when router debugging is enabled.\n"

vpr/src/base/read_options.h

@@ -52,6 +52,7 @@ struct t_options {
     argparse::ArgValue<bool> strict_checks;
     argparse::ArgValue<std::string> disable_errors;
     argparse::ArgValue<std::string> suppress_warnings;
+    argparse::ArgValue<bool> allow_dangling_combinational_nodes;
 
     /* Atom netlist options */
     argparse::ArgValue<bool> absorb_buffer_luts;
@@ -120,6 +121,7 @@ struct t_options {
     argparse::ArgValue<bool> verify_binary_search;
     argparse::ArgValue<e_router_algorithm> RouterAlgorithm;
     argparse::ArgValue<int> min_incremental_reroute_fanout;
+    argparse::ArgValue<bool> disable_check_route;
 
     /* Timing-driven router options only */
     argparse::ArgValue<float> astar_fac;

vpr/src/base/vpr_api.cpp

@@ -304,7 +304,7 @@ void vpr_init(const int argc, const char** argv, t_options* options, t_vpr_setup
         auto& timing_ctx = g_vpr_ctx.mutable_timing();
         {
             vtr::ScopedStartFinishTimer t("Build Timing Graph");
-            timing_ctx.graph = TimingGraphBuilder(atom_ctx.nlist, atom_ctx.lookup).timing_graph();
+            timing_ctx.graph = TimingGraphBuilder(atom_ctx.nlist, atom_ctx.lookup).timing_graph(options->allow_dangling_combinational_nodes);
             VTR_LOG("  Timing Graph Nodes: %zu\n", timing_ctx.graph->nodes().size());
             VTR_LOG("  Timing Graph Edges: %zu\n", timing_ctx.graph->edges().size());
             VTR_LOG("  Timing Graph Levels: %zu\n", timing_ctx.graph->levels().size());
@@ -666,7 +666,9 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) {
         std::string graphics_msg;
         if (route_status.success()) {
             //Sanity check the routing
-            check_route(router_opts.route_type);
+            if (!router_opts.disable_check_route) {
+                check_route(router_opts.route_type);
+            }
             get_serial_num();
 
             //Update status

vpr/src/base/vpr_context.h

@@ -20,6 +20,7 @@
 #include "clock_connection_builders.h"
 #include "route_traceback.h"
 #include "place_macro.h"
+#include "connection_box.h"
 
 //A Context is collection of state relating to a particular part of VPR
 //
@@ -194,6 +195,8 @@ struct DeviceContext : public Context {
      * Clock Network
      ********************************************************************/
     t_clock_arch* clock_arch;
+
+    ConnectionBoxes connection_boxes;
 };
 
 //State relating to power analysis

vpr/src/base/vpr_types.h

@@ -103,7 +103,10 @@ constexpr const char* EMPTY_BLOCK_NAME = "EMPTY";
 enum class e_router_lookahead {
     CLASSIC, //VPR's classic lookahead (assumes uniform wire types)
     MAP,     //Lookahead considering different wire types (see Oleg Petelin's MASc Thesis)
-    NO_OP    //A no-operation lookahead which always returns zero
+    NO_OP,   //A no-operation lookahead which always returns zero
+    CONNECTION_BOX_MAP,
+    // Lookahead considering different wire types and IPIN
+    // connection box.
 };
 
 enum class e_route_bb_update {
@@ -947,6 +950,7 @@ struct t_router_opts {
     float reconvergence_cpd_threshold;
     std::string first_iteration_timing_report_file;
     bool strict_checks;
+    bool disable_check_route;
 };
 
 struct t_analysis_opts {

vpr/src/place/timing_place_lookup.cpp

@@ -264,9 +264,11 @@ static float route_connection_delay(int source_x, int source_y, int sink_x, int
 
             VTR_ASSERT(sink_rr_node != OPEN);
 
-            successfully_routed = calculate_delay(source_rr_node, sink_rr_node,
-                                                  router_opts,
-                                                  &net_delay_value);
+            {
+                successfully_routed = calculate_delay(source_rr_node, sink_rr_node,
+                                                      router_opts,
+                                                      &net_delay_value);
+            }
 
             if (successfully_routed) break;
         }

vpr/src/route/connection_box.cpp

@@ -0,0 +1,127 @@
+#include "connection_box.h"
+#include "vtr_assert.h"
+#include "globals.h"
+
+ConnectionBoxes::ConnectionBoxes()
+    : size_(std::make_pair(0, 0)) {
+}
+
+size_t ConnectionBoxes::num_connection_box_types() const {
+    return boxes_.size();
+}
+
+std::pair<size_t, size_t> ConnectionBoxes::connection_box_grid_size() const {
+    return size_;
+}
+
+const ConnectionBox* ConnectionBoxes::get_connection_box(ConnectionBoxId box) const {
+    if (bool(box)) {
+        return nullptr;
+    }
+
+    size_t index = size_t(box);
+    if (index >= boxes_.size()) {
+        return nullptr;
+    }
+
+    return &boxes_.at(index);
+}
+
+bool ConnectionBoxes::find_connection_box(int inode,
+                                          ConnectionBoxId* box_id,
+                                          std::pair<size_t, size_t>* box_location) const {
+    VTR_ASSERT(box_id != nullptr);
+    VTR_ASSERT(box_location != nullptr);
+
+    const auto& conn_box_loc = ipin_map_[inode];
+    if (conn_box_loc.box_id == ConnectionBoxId::INVALID()) {
+        return false;
+    }
+
+    *box_id = conn_box_loc.box_id;
+    *box_location = conn_box_loc.box_location;
+    return true;
+}
+
+// Clear IPIN map and set connection box grid size and box ids.
+void ConnectionBoxes::reset_boxes(std::pair<size_t, size_t> size,
+                                  const std::vector<ConnectionBox> boxes) {
+    clear();
+
+    size_ = size;
+    boxes_ = boxes;
+}
+
+void ConnectionBoxes::resize_nodes(size_t rr_node_size) {
+    ipin_map_.resize(rr_node_size);
+    canonical_loc_map_.resize(rr_node_size,
+                              std::make_pair(-1, -1));
+}
+
+void ConnectionBoxes::clear() {
+    ipin_map_.clear();
+    size_ = std::make_pair(0, 0);
+    boxes_.clear();
+    canonical_loc_map_.clear();
+    sink_to_ipin_.clear();
+}
+
+void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std::pair<size_t, size_t> box_location) {
+    // Ensure that box location is in bounds
+    VTR_ASSERT(box_location.first < size_.first);
+    VTR_ASSERT(box_location.second < size_.second);
+
+    // Bounds check box_id
+    VTR_ASSERT(bool(box_id));
+    VTR_ASSERT(size_t(box_id) < boxes_.size());
+
+    // Make sure sink map will not be invalidated upon insertion.
+    VTR_ASSERT(sink_to_ipin_.size() == 0);
+
+    ipin_map_[inode] = ConnBoxLoc(box_location, box_id);
+}
+
+void ConnectionBoxes::add_canonical_loc(int inode, std::pair<size_t, size_t> loc) {
+    VTR_ASSERT(loc.first < size_.first);
+    VTR_ASSERT(loc.second < size_.second);
+    canonical_loc_map_[inode] = loc;
+}
+
+const std::pair<size_t, size_t>* ConnectionBoxes::find_canonical_loc(int inode) const {
+    const auto& canon_loc = canonical_loc_map_[inode];
+    if (canon_loc.first == size_t(-1)) {
+        return nullptr;
+    }
+
+    return &canon_loc;
+}
+
+void ConnectionBoxes::create_sink_back_ref() {
+    const auto& device_ctx = g_vpr_ctx.device();
+
+    sink_to_ipin_.resize(device_ctx.rr_nodes.size(), {{0, 0, 0, 0}, 0});
+
+    for (size_t i = 0; i < device_ctx.rr_nodes.size(); ++i) {
+        const auto& ipin_node = device_ctx.rr_nodes[i];
+        if (ipin_node.type() != IPIN) {
+            continue;
+        }
+
+        if (ipin_map_[i].box_id == ConnectionBoxId::INVALID()) {
+            continue;
+        }
+
+        for (auto edge : ipin_node.edges()) {
+            int sink_inode = ipin_node.edge_sink_node(edge);
+            VTR_ASSERT(device_ctx.rr_nodes[sink_inode].type() == SINK);
+            VTR_ASSERT(sink_to_ipin_[sink_inode].ipin_count < 4);
+            auto& sink_to_ipin = sink_to_ipin_[sink_inode];
+            sink_to_ipin.ipin_nodes[sink_to_ipin.ipin_count++] = i;
+        }
+    }
+}
+
+const SinkToIpin& ConnectionBoxes::find_sink_connection_boxes(
+    int inode) const {
+    return sink_to_ipin_[inode];
+}