Update Documentation to reflect latest changes

Author: jeanlego

doc/src/odin/index.rst

@@ -232,9 +232,9 @@ Verilog Synthesizable Keyword Support:
 +-------------------+------------------+---------------------+--------------------+
 | Supported Keyword | NOT Sup. Keyword | Supported Operators | NOT Sup. Operators |
 +-------------------+------------------+---------------------+--------------------+
-| @()               | automatic        | !=                  | -:                 |
+| @()               | automatic        | !=                  |                    |
 +-------------------+------------------+---------------------+--------------------+
-| @*                | deassign         | !==                 | +:                 |
+| @*                | deassign         | !==                 |                    |
 +-------------------+------------------+---------------------+--------------------+
 | `define           | disable          | ==                  | \>\>\>             |
 +-------------------+------------------+---------------------+--------------------+
@@ -252,9 +252,9 @@ Verilog Synthesizable Keyword Support:
 +-------------------+------------------+---------------------+--------------------+
 | endfunction       | task             | ||                  |                    |
 +-------------------+------------------+---------------------+--------------------+
-| endmodule         |                  | ~&                  |                    |
+| endmodule         | generate         | ~&                  |                    |
 +-------------------+------------------+---------------------+--------------------+
-| begin             |                  | &&                  |                    |
+| begin             | genvar           | &&                  |                    |
 +-------------------+------------------+---------------------+--------------------+
 | default           |                  | <<                  |                    |
 +-------------------+------------------+---------------------+--------------------+
@@ -266,11 +266,11 @@ Verilog Synthesizable Keyword Support:
 +-------------------+------------------+---------------------+--------------------+
 | for               |                  | ~|                  |                    |
 +-------------------+------------------+---------------------+--------------------+
-| function          |                  |                     |                    |
+| function          |                  | $clog()             |                    |
 +-------------------+------------------+---------------------+--------------------+
-| if                |                  |                     |                    |
+| if                |                  | -:                  |                    |
 +-------------------+------------------+---------------------+--------------------+
-| inout             |                  |                     |                    |
+| inout             |                  | +:                  |                    |
 +-------------------+------------------+---------------------+--------------------+
 | input             |                  |                     |                    |
 +-------------------+------------------+---------------------+--------------------+
@@ -310,10 +310,19 @@ Verilog Synthesizable Keyword Support:
 +-------------------+------------------+---------------------+--------------------+
 | macromodule       |                  |                     |                    |
 +-------------------+------------------+---------------------+--------------------+
-| +:                |                  |                     |                    |
-+-------------------+------------------+---------------------+--------------------+
-| -:                |                  |                     |                    |
-+-------------------+------------------+---------------------+--------------------+
+
+Verilog Syntax support:
+*********************************
+
+inline port declaration in the module declaration
+i.e:
+
+.. code-block:: verilog
+
+	module a(input clk)
+	...
+	endmodule
+
 
 Verilog NON-Synthesizable Keyword Support:
 *********************************