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acomodiacomodi
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vtr_flow: added script to add tiles to architecture xml
I have also changes travis.yml to install the lxml python package needed by the script Signed-off-by: Alessandro Comodi <[email protected]>
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‎.travis.yml

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@@ -36,6 +36,7 @@ addons:
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- libxml++2.6-dev
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- perl
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- python
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- python-lxml
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- texinfo
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- time
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- valgrind

‎vtr_flow/scripts/add_tiles.py

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#!/usr/bin/env python
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"""
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This script is intended to modify the architecture description file to be compliant with
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the new format.
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It moves the top level pb_types attributes and tags to the tiles high-level tag.
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BEFORE:
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<complexblocklist>
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<pb_type name="BRAM" area="2" height="4" width="1" capacity="1">
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<input ... />
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<input ... />
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<input ... />
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<output ... />
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<output ... />
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<output ... />
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<interconnect ... />
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<fc ... />
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<pinlocations ... />
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<switchblock_locations ... />
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</pb_type>
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</complexblocklist>
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AFTER:
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<tiles>
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<tile name="BRAM" area="2" height="4" width="1" capacity="1">
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<interconnect ... />
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<fc ... />
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<pinlocations ... />
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<switchblock_locations ... />
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</tile>
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</tiles>
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<complexblocklist
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<pb_type name="BRAM">
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<input ... />
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<input ... />
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<input ... />
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<output ... />
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<output ... />
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<output ... />
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</pb_type>
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</complexblocklist>
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"""
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"""
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This script is intended to modify the architecture description file to be compliant with
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the new format.
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It moves the top level pb_types attributes and tags to the tiles high-level tag.
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BEFORE:
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<complexblocklist>
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<pb_type name="BRAM" area="2" height="4" width="1" capacity="1">
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<input ... />
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<input ... />
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<input ... />
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<output ... />
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<output ... />
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<output ... />
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<interconnect ... />
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<fc ... />
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<pinlocations ... />
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<switchblock_locations ... />
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</pb_type>
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</complexblocklist>
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AFTER:
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<tiles>
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<tile name="BRAM" area="2" height="4" width="1" capacity="1">
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<interconnect ... />
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<fc ... />
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<pinlocations ... />
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<switchblock_locations ... />
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</tile>
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</tiles>
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<complexblocklist
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<pb_type name="BRAM">
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<input ... />
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<input ... />
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<input ... />
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<output ... />
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<output ... />
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<output ... />
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</pb_type>
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</complexblocklist>
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"""
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from lxml import etree as ET
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import argparse
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TAGS_TO_SWAP = ['fc', 'pinlocations', 'switchblock_locations']
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ATTR_TO_REMOVE = ['area', 'height', 'width', 'capacity']
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def swap_tags(tile, pb_type):
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# Moving tags from top level pb_type to tile
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for child in pb_type:
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if child.tag in TAGS_TO_SWAP:
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pb_type.remove(child)
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tile.append(child)
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def main():
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parser = argparse.ArgumentParser(
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description="Moves top level pb_types to tiles tag."
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)
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parser.add_argument(
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'--arch_xml',
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required=True,
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help="Input arch.xml that needs to be modified to move the top level pb_types to the `tiles` tag."
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)
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args = parser.parse_args()
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arch_xml = ET.ElementTree()
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root_element = arch_xml.parse(args.arch_xml)
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tiles = ET.SubElement(root_element, 'tiles')
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top_pb_types = []
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for pb_type in root_element.iter('pb_type'):
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if pb_type.getparent().tag == 'complexblocklist':
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top_pb_types.append(pb_type)
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for pb_type in top_pb_types:
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tile = ET.SubElement(tiles, 'tile')
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attrs = pb_type.attrib
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for attr in attrs:
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tile.set(attr, pb_type.get(attr))
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# Remove attributes of top level pb_types only
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for attr in ATTR_TO_REMOVE:
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pb_type.attrib.pop(attr, None)
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swap_tags(tile, pb_type)
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print(ET.tostring(arch_xml, pretty_print=True).decode('utf-8'))
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if __name__ == '__main__':
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main()

‎vtr_flow/scripts/run_vtr_flow.pl

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# Read arch XML
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my $tpp = XML::TreePP->new();
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my $xml_tree = $tpp->parsefile($architecture_file_path);
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my $xml_tree = $tpp->parsefile("$architecture_file_path");
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# Get lut size if undefined
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if (!defined $lut_size) {
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#system "cp $odin2_base_config"
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my $architecture_file_path_new = "$temp_dir$architecture_file_name";
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copy( $architecture_file_path, $architecture_file_path_new );
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my $ret = `$vtr_flow_path/scripts/add_tiles.py --arch_xml $architecture_file_path > $architecture_file_path_new`;
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#copy( "$architecture_file_path", $architecture_file_path_new );
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$architecture_file_path = $architecture_file_path_new;
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my $circuit_file_path_new = "$temp_dir$benchmark_name" . file_ext_for_stage($starting_stage - 1, $circuit_suffix);

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