Merge branches 'wip/add-issue-template', 'wip/add_explicit_ports', 'wip/avoid-criticality-issue', 'wip/avoid_unordered_set', 'wip/disable-check-route-option', 'wip/faster_rr_graph_read', 'wip/inline_main_loop', 'wip/length_bounded', 'wip/lookahead_sampling2', 'wip/place-constraints', 'wip/refactor_heap2', 'wip/revert_clock_propigation', 'wip/rr-graph-binary-read-write', 'wip/symbiflow-badger' and 'wip/use_expansion_for_place_delay' into add_explicit_ports

Author: litghost

.github/ISSUE_TEMPLATE/bug_report.md

@@ -1,6 +1,9 @@
 ---
 name: Bug report
 about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
 
 ---
 

.github/ISSUE_TEMPLATE/feature_request.md

@@ -1,6 +1,9 @@
 ---
 name: Feature request
 about: Suggest an idea for this project
+title: ''
+labels: ''
+assignees: ''
 
 ---
 

.github/ISSUE_TEMPLATE/vtr-change.md

@@ -0,0 +1,25 @@
+---
+name: VTR change
+about: Describe purpose and lifecycle of a local change we made to VTR
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+### Why did we need this? (what does this change enable us to do)
+<!--- i.e. what does this change enable us to do? -->
+
+### What did it change?
+<!--- i.e. technical description what the change does -->
+
+### Should it be merged upstream - if not, when can we delete it?
+
+### What is needed to get this merged / deleted? 
+
+* [ ] is the implementation work to make suitable for merging / deletion completed?
+* [ ] Is there an associated test? <!--- i.e. how will we prevent it from regressing? -->
+* [ ] is this currently part of the Conda package?
+* [ ] is this properly cleaned up in our local repositories? <!--- add subtasks here if needed) -->
+
+### Tracker / branch / PR & other useful links

README.md

@@ -1,5 +1,14 @@
+
+SymbiFlow WIP changes for Verilog to Routing (VTR)
+==================================================
+
+This branch contains work in progress changes for using Verilog to Routing
+(VTR) as part of SymbiFlow.
+
+---
+
 # Verilog to Routing (VTR)
-[![Build Status](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
+[![Build Status](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest)
 
 ## Introduction
 The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.

libs/EXTERNAL/CMakeLists.txt

@@ -8,7 +8,7 @@ add_subdirectory(libsdcparse)
 add_subdirectory(libblifparse)
 add_subdirectory(libtatum)
 
-#VPR_USE_EZGL is initialized in the root CMakeLists. 
+#VPR_USE_EZGL is initialized in the root CMakeLists.
 #compile libezgl only if the user asks for or has its dependencies installed.
 if(VPR_USE_EZGL STREQUAL "on")
     add_subdirectory(libezgl)

libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp

@@ -731,9 +731,8 @@ bool TimingGraph::validate_structure() const {
 
             } else if (src_type == NodeType::CPIN) {
                 if(   sink_type != NodeType::SOURCE
-                   && sink_type != NodeType::SINK 
-                   && sink_type != NodeType::OPIN) {
-                    throw tatum::Error("CPIN nodes should only drive SOURCE, OPIN or SINK nodes", src_node, out_edge);
+                   && sink_type != NodeType::SINK) {
+                    throw tatum::Error("CPIN nodes should only drive SOURCE or SINK nodes", src_node, out_edge);
                 }
 
                 if(sink_type == NodeType::SOURCE && out_edge_type != EdgeType::PRIMITIVE_CLOCK_LAUNCH) {

libs/libarchfpga/src/physical_types.cpp

@@ -110,7 +110,12 @@ std::vector<int> t_physical_tile_type::get_clock_pins_indices() const {
     int clock_pins_start_idx = 0;
     int clock_pins_stop_idx = 0;
 
-    for (int capacity_num = 0; capacity_num < this->capacity; capacity_num++) {
+    int num_capacity = 1;
+    if (capacity_type == e_capacity_type::DUPLICATE) {
+        num_capacity = this->capacity;
+    }
+
+    for (int capacity_num = 0; capacity_num < num_capacity; capacity_num++) {
         // Ranges are picked on the basis that pins are ordered: inputs, outputs, then clock pins
         // This is because ProcessPb_type assigns pb_type port indices in that order and
         // SetupPinLocationsAndPinClasses assigns t_logical_block_type_ptr pin indices in the order of port indices

libs/libarchfpga/src/physical_types.h

@@ -523,6 +523,12 @@ enum class e_sb_type {
 
 };
 
+enum class e_capacity_type {
+    DUPLICATE, // Capacity duplicates ports.
+    EXPLICIT   // Capacity increases the number of logical tiles, but does not
+               // modify the physical ports.
+};
+
 constexpr int NO_SWITCH = -1;
 constexpr int DEFAULT_SWITCH = -2;
 
@@ -577,6 +583,7 @@ struct t_physical_tile_type {
     int num_clock_pins = 0;
 
     int capacity = 0;
+    e_capacity_type capacity_type = e_capacity_type::DUPLICATE;
 
     int width = 0;
     int height = 0;
@@ -625,18 +632,20 @@ struct t_physical_tile_type {
  *  vtr::bimap container.
  */
 struct t_logical_pin {
+    int z_index = -1;
     int pin = -1;
 
-    t_logical_pin(int value) {
+    t_logical_pin(int z_index_value, int value) {
+        z_index = z_index_value;
         pin = value;
     }
 
     bool operator==(const t_logical_pin o) const {
-        return pin == o.pin;
+        return z_index == o.z_index && pin == o.pin;
     }
 
     bool operator<(const t_logical_pin o) const {
-        return pin < o.pin;
+        return std::make_pair(z_index, pin) < std::make_pair(o.z_index, o.pin);
     }
 };