archfpga: Improve error reporting for tile/block pin mismatches

We now include the relevant block/tile names to aid debugging.

Author: kmurray

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -4711,7 +4711,8 @@ static void check_port_equivalence(t_physical_tile_type& physical_tile, t_logica
 
     if (pb_type->num_ports != (int)physical_tile.ports.size()) {
         archfpga_throw(__FILE__, __LINE__,
-                       "Logical and Physical types have a different number of ports.\n");
+                       "Logical block (%s) and Physical tile (%s) have a different number of ports.\n",
+                       logical_block.name, physical_tile.name);
     }
 
     for (auto& tile_port : physical_tile.ports) {
@@ -4722,7 +4723,8 @@ static void check_port_equivalence(t_physical_tile_type& physical_tile, t_logica
             || tile_port.num_pins != block_port.num_pins
             || tile_port.equivalent != block_port.equivalent) {
             archfpga_throw(__FILE__, __LINE__,
-                           "Logical and Physical types do not have equivalent port specifications.\n");
+                           "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications.\n",
+                           logical_block.name, physical_tile.name);
         }
     }
 }