route: added penalty cost to switches

acomodi · acomodi · commit 31cf9d691f45 · 2020-06-17T10:32:52.000+02:00
Signed-off-by: Alessandro Comodi &lt;acomodi@antmicro.com&gt;
diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -1457,6 +1457,7 @@ struct t_arch_switch_inf {
     float Cin = 0.;
     float Cout = 0.;
     float Cinternal = 0.;
+    float penalty_cost = 0.;
     float mux_trans_size = 1.;
     BufferSize buf_size_type = BufferSize::AUTO;
     float buf_size = 0.;
@@ -1521,6 +1522,7 @@ struct t_rr_switch_inf {
     float Cout = 0.;
     float Cinternal = 0.;
     float Tdel = 0.;
+    float penalty_cost = 0.;
     float mux_trans_size = 0.;
     float buf_size = 0.;
     const char* name = nullptr;
diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -3978,23 +3978,23 @@ static void ProcessSwitches(pugi::xml_node Parent,
         SwitchType type = SwitchType::MUX;
         if (0 == strcmp(type_name, "mux")) {
             type = SwitchType::MUX;
-            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
+            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size", "mux_trans_size"}, " with type '"s + type_name + "'"s, loc_data);
 
         } else if (0 == strcmp(type_name, "tristate")) {
             type = SwitchType::TRISTATE;
-            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
+            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Cinternal", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
 
         } else if (0 == strcmp(type_name, "buffer")) {
             type = SwitchType::BUFFER;
-            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
+            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost", "buf_size", "power_buf_size"}, " with type '"s + type_name + "'"s, loc_data);
 
         } else if (0 == strcmp(type_name, "pass_gate")) {
             type = SwitchType::PASS_GATE;
-            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type '"s + type_name + "'"s, loc_data);
+            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type '"s + type_name + "'"s, loc_data);
 
         } else if (0 == strcmp(type_name, "short")) {
             type = SwitchType::SHORT;
-            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel"}, " with type "s + type_name + "'"s, loc_data);
+            expect_only_attributes(Node, {"type", "name", "R", "Cin", "Cout", "Tdel", "penalty_cost"}, " with type "s + type_name + "'"s, loc_data);
         } else {
             archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
                            "Invalid switch type '%s'.\n", type_name);
@@ -4017,6 +4017,7 @@ static void ProcessSwitches(pugi::xml_node Parent,
         arch_switch.Cin = get_attribute(Node, "Cin", loc_data, CIN_REQD).as_float(0);
         arch_switch.Cout = get_attribute(Node, "Cout", loc_data, COUT_REQD).as_float(0);
         arch_switch.Cinternal = get_attribute(Node, "Cinternal", loc_data, CINTERNAL_REQD).as_float(0);
+        arch_switch.penalty_cost = get_attribute(Node, "penalty_cost", loc_data, ReqOpt::OPTIONAL).as_float(0);
 
         if (arch_switch.type() == SwitchType::MUX) {
             //Only muxes have mux transistors
diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
@@ -2,11 +2,11 @@
 # https://github.com/duck2/uxsdcxx
 # Modify only if your build process doesn't involve regenerating this file.
 #
-# Cmdline: uxsdcxx/uxsdcap.py /home/kmurray/trees/vtr/vpr/src/route/rr_graph.xsd
-# Input file: /home/kmurray/trees/vtr/vpr/src/route/rr_graph.xsd
-# md5sum of input file: 40e83d2ea6556761d4e29f21324b1871
+# Cmdline: uxsdcxx/uxsdcap.py rr_graph.xsd
+# Input file: rr_graph.xsd
+# md5sum of input file: c4f47394efd27f5819c943829c111204
 
-@0xb803100e76d3342d;
+@0x9e90feddf132e6a8;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 
@@ -81,6 +81,7 @@ struct Timing {
 	cout @2 :Float32;
 	r @3 :Float32;
 	tdel @4 :Float32;
+	penaltyCost @5 :Float32;
 }
 
 struct Sizing {
diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp
@@ -282,6 +282,7 @@ static void SetupSwitches(const t_arch& Arch,
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].R = 0.;
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cin = 0.;
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].Cout = 0.;
+    device_ctx.arch_switch_inf[RoutingArch->delayless_switch].penalty_cost = 0.;
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].set_Tdel(t_arch_switch_inf::UNDEFINED_FANIN, 0.);
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].power_buffer_type = POWER_BUFFER_TYPE_NONE;
     device_ctx.arch_switch_inf[RoutingArch->delayless_switch].mux_trans_size = 0.;
diff --git a/vpr/src/route/gen/rr_graph_uxsdcxx.h b/vpr/src/route/gen/rr_graph_uxsdcxx.h
diff --git a/vpr/src/route/gen/rr_graph_uxsdcxx_capnp.h b/vpr/src/route/gen/rr_graph_uxsdcxx_capnp.h
diff --git a/vpr/src/route/gen/rr_graph_uxsdcxx_interface.h b/vpr/src/route/gen/rr_graph_uxsdcxx_interface.h
diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp
@@ -76,14 +76,19 @@ float ClassicLookahead::classic_wire_lookahead_cost(int inode, int target_node,
                       + ipin_data.base_cost
                       + sink_data.base_cost;
 
+    float penalty_cost = num_segs_same_dir * same_data.penalty_cost
+                         + num_segs_ortho_dir * ortho_data.penalty_cost
+                         + ipin_data.penalty_cost
+                         + sink_data.penalty_cost;
+
     float Tdel = num_segs_same_dir * same_data.T_linear
                  + num_segs_ortho_dir * ortho_data.T_linear
                  + num_segs_same_dir * num_segs_same_dir * same_data.T_quadratic
                  + num_segs_ortho_dir * num_segs_ortho_dir * ortho_data.T_quadratic
                  + R_upstream * (num_segs_same_dir * same_data.C_load + num_segs_ortho_dir * ortho_data.C_load)
                  + ipin_data.T_linear;
 
-    float expected_cost = criticality * Tdel + (1. - criticality) * cong_cost;
+    float expected_cost = criticality * penalty_cost + criticality * Tdel + (1. - criticality) * cong_cost;
     return (expected_cost);
 }
 
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
@@ -884,6 +884,7 @@ void load_rr_switch_from_arch_switch(int arch_switch_idx,
     device_ctx.rr_switch_inf[rr_switch_idx].Cin = device_ctx.arch_switch_inf[arch_switch_idx].Cin;
     device_ctx.rr_switch_inf[rr_switch_idx].Cinternal = device_ctx.arch_switch_inf[arch_switch_idx].Cinternal;
     device_ctx.rr_switch_inf[rr_switch_idx].Cout = device_ctx.arch_switch_inf[arch_switch_idx].Cout;
+    device_ctx.rr_switch_inf[rr_switch_idx].penalty_cost = device_ctx.arch_switch_inf[arch_switch_idx].penalty_cost;
     device_ctx.rr_switch_inf[rr_switch_idx].Tdel = rr_switch_Tdel;
     device_ctx.rr_switch_inf[rr_switch_idx].mux_trans_size = device_ctx.arch_switch_inf[arch_switch_idx].mux_trans_size;
     if (device_ctx.arch_switch_inf[arch_switch_idx].buf_size_type == BufferSize::AUTO) {
diff --git a/vpr/src/route/rr_graph.xsd b/vpr/src/route/rr_graph.xsd
@@ -101,6 +101,7 @@
     <xs:attribute name="Cinternal" type="xs:float"/>
     <xs:attribute name="Cout" type="xs:float"/>
     <xs:attribute name="Tdel" type="xs:float"/>
+    <xs:attribute name="penalty_cost" type="xs:float"/>
   </xs:complexType>
 
   <xs:complexType name="sizing">
diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp
@@ -77,9 +77,13 @@ void alloc_and_load_rr_indexed_data(const std::vector<t_segment_inf>& segment_in
         device_ctx.rr_indexed_data[i].T_linear = 0.;
         device_ctx.rr_indexed_data[i].T_quadratic = 0.;
         device_ctx.rr_indexed_data[i].C_load = 0.;
+        device_ctx.rr_indexed_data[i].penalty_cost = 0.;
     }
+
     device_ctx.rr_indexed_data[IPIN_COST_INDEX].T_linear = device_ctx.rr_switch_inf[wire_to_ipin_switch].Tdel;
 
+    device_ctx.rr_indexed_data[IPIN_COST_INDEX].penalty_cost = device_ctx.rr_switch_inf[wire_to_ipin_switch].penalty_cost;
+
     /* X-directed segments. */
     for (iseg = 0; iseg < num_segment; iseg++) {
         index = CHANX_COST_INDEX_START + iseg;
@@ -319,8 +323,8 @@ static void load_rr_indexed_data_T_values(int index_start,
      * segment. */
 
     int itrack, cost_index;
-    float *C_total, *R_total;                                         /* [0..device_ctx.rr_indexed_data.size() - 1] */
-    double *switch_R_total, *switch_T_total, *switch_Cinternal_total; /* [0..device_ctx.rr_indexed_data.size() - 1] */
+    float *C_total, *R_total;                                                                     /* [0..device_ctx.rr_indexed_data.size() - 1] */
+    double *switch_R_total, *switch_T_total, *switch_Cinternal_total, *switch_penalty_cost_total; /* [0..device_ctx.rr_indexed_data.size() - 1] */
     short* switches_buffered;
     int* num_nodes_of_index; /* [0..device_ctx.rr_indexed_data.size() - 1] */
     float Rnode, Cnode, Rsw, Tsw, Cinternalsw;
@@ -340,6 +344,7 @@ static void load_rr_indexed_data_T_values(int index_start,
     switch_R_total = (double*)vtr::calloc(device_ctx.rr_indexed_data.size(), sizeof(double));
     switch_T_total = (double*)vtr::calloc(device_ctx.rr_indexed_data.size(), sizeof(double));
     switch_Cinternal_total = (double*)vtr::calloc(device_ctx.rr_indexed_data.size(), sizeof(double));
+    switch_penalty_cost_total = (double*)vtr::calloc(device_ctx.rr_indexed_data.size(), sizeof(double));
     switches_buffered = (short*)vtr::calloc(device_ctx.rr_indexed_data.size(), sizeof(short));
 
     /* initialize switches_buffered array */
@@ -364,9 +369,23 @@ static void load_rr_indexed_data_T_values(int index_start,
         double avg_switch_R = 0;
         double avg_switch_T = 0;
         double avg_switch_Cinternal = 0;
+        double avg_switch_penalty_cost = 0;
+        int num_edges = device_ctx.rr_nodes[inode].num_edges();
         int num_switches = 0;
         short buffered = UNDEFINED;
-        calculate_average_switch(inode, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, buffered);
+        for (int iedge = 0; iedge < num_edges; iedge++) {
+            int to_node_index = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
+            /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
+            if (device_ctx.rr_nodes[to_node_index].type() == CHANX || device_ctx.rr_nodes[to_node_index].type() == CHANY) {
+                int switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
+                avg_switch_R += device_ctx.rr_switch_inf[switch_index].R;
+                avg_switch_T += device_ctx.rr_switch_inf[switch_index].Tdel;
+                avg_switch_Cinternal += device_ctx.rr_switch_inf[switch_index].Cinternal;
+                avg_switch_penalty_cost += device_ctx.rr_switch_inf[switch_index].penalty_cost;
+
+                num_switches++;
+            }
+        }
 
         if (num_switches == 0) {
             VTR_LOG_WARN("Track %d had no out-going switches\n", itrack);
@@ -377,6 +396,7 @@ static void load_rr_indexed_data_T_values(int index_start,
         switch_R_total[cost_index] += avg_switch_R;
         switch_T_total[cost_index] += avg_switch_T;
         switch_Cinternal_total[cost_index] += avg_switch_Cinternal;
+        switch_penalty_cost_total[cost_index] += avg_switch_penalty_cost;
         if (buffered == UNDEFINED) {
             /* this segment does not have any outgoing edges to other general routing wires */
             continue;
@@ -461,6 +481,8 @@ static void load_rr_indexed_data_T_values(int index_start,
                 device_ctx.rr_indexed_data[cost_index].T_quadratic = (Rsw + Rnode) * 0.5
                                                                      * Cnode;
             }
+
+            device_ctx.rr_indexed_data[cost_index].penalty_cost = (float)switch_penalty_cost_total[cost_index] / num_nodes_of_index[cost_index];
         }
     }
 
@@ -470,6 +492,7 @@ static void load_rr_indexed_data_T_values(int index_start,
     free(switch_R_total);
     free(switch_T_total);
     free(switch_Cinternal_total);
+    free(switch_penalty_cost_total);
     free(switches_buffered);
 }
 
diff --git a/vpr/src/route/rr_graph_uxsdcxx_serializer.h b/vpr/src/route/rr_graph_uxsdcxx_serializer.h
@@ -355,6 +355,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
         return sw->Tdel;
     }
 
+    inline void set_timing_penalty_cost(float penalty_cost, t_rr_switch_inf*& sw) final {
+        sw->penalty_cost = penalty_cost;
+    }
+    inline float get_timing_penalty_cost(const t_rr_switch_inf*& sw) final {
+        return sw->penalty_cost;
+    }
+
     /** Generated for complex type "switch":
      * <xs:complexType name="switch">
      *   <xs:all>
diff --git a/vpr/src/route/rr_node.h b/vpr/src/route/rr_node.h
@@ -185,6 +185,7 @@ struct t_rr_indexed_data {
     float T_linear = std::numeric_limits<float>::quiet_NaN();
     float T_quadratic = std::numeric_limits<float>::quiet_NaN();
     float C_load = std::numeric_limits<float>::quiet_NaN();
+    float penalty_cost;
 };
 
 #include "rr_node_impl.h"
