Merge branch 'rr-graph-binary-read-write' into master+wip

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

vpr/src/route/rr_graph.cpp

@@ -2514,6 +2514,54 @@ static vtr::NdMatrix<std::vector<int>, 4> alloc_and_load_track_to_pin_lookup(vtr
     return track_to_pin_lookup;
 }
 
+/* Writes out data (excludes fasm metadata) about node inode to binary in file fp *
+ * Writes data in the following order: int inode, t_rr_type type, e_direction     *
+ * direction (if CHANX or CHANY), uint16_t capacity, length 5 uint16_t array pos, *
+ * e_side side (if IPIN or OPIN), float R, float C, uint16_t num_edges.Then loops *
+ * through every edge writing out int edge_sink node and uint16_t edge_switch.    */
+void write_rr_node(FILE* fp, const std::vector<t_rr_node>& L_rr_node, int inode) {
+    const auto& rr_node = L_rr_node[inode];
+    t_rr_type type = rr_node.type();
+    uint16_t num_edges = rr_node.num_edges();
+    int edge_sink_node;
+    uint16_t edge_switch;
+    uint16_t capacity = (uint16_t)rr_node.capacity();
+    float R = rr_node.R();
+    float C = rr_node.C();
+    uint16_t pos[5];
+
+    pos[0] = rr_node.xlow();
+    pos[1] = rr_node.ylow();
+    pos[2] = rr_node.xhigh();
+    pos[3] = rr_node.yhigh();
+    pos[4] = rr_node.ptc_num();
+
+    fwrite(&inode, sizeof(inode), 1, fp);
+    fwrite(&type, sizeof(type), 1, fp);
+    if (rr_node.type() == CHANX || rr_node.type() == CHANY) {
+        e_direction direction = rr_node.direction();
+        fwrite(&direction, sizeof(direction), 1, fp);
+    }
+    fwrite(&capacity, sizeof(capacity), 1, fp);
+    fwrite(pos, sizeof(*pos), 5, fp);
+
+    if (rr_node.type() == IPIN || rr_node.type() == OPIN) {
+        e_side side = rr_node.side();
+        fwrite(&side, sizeof(side), 1, fp);
+    }
+
+    fwrite(&R, sizeof(R), 1, fp);
+    fwrite(&C, sizeof(C), 1, fp);
+    fwrite(&num_edges, sizeof(num_edges), 1, fp);
+
+    for (int iedge = 0; iedge < rr_node.num_edges(); ++iedge) {
+        edge_sink_node = rr_node.edge_sink_node(iedge);
+        edge_switch = rr_node.edge_switch(iedge);
+        fwrite(&edge_sink_node, sizeof(edge_sink_node), 1, fp);
+        fwrite(&edge_switch, sizeof(edge_switch), 1, fp);
+    }
+}
+
 std::string describe_rr_node(int inode) {
     auto& device_ctx = g_vpr_ctx.device();
 

vpr/src/route/rr_graph.h

@@ -6,6 +6,9 @@
  * and so are not currently used in commercial architectures. */
 #define INCLUDE_TRACK_BUFFERS false
 
+#define BINARY_MAGIC_NUM 0x42525247
+#define BINARY_FILE_VERSION 1
+
 #include "device_grid.h"
 
 enum e_graph_type {
@@ -45,6 +48,9 @@ void free_rr_graph();
 //Returns a brief one-line summary of an RR node
 std::string describe_rr_node(int inode);
 
+void print_rr_node(FILE* fp, const std::vector<t_rr_node>& L_rr_node, int inode);
+void write_rr_node(FILE* fp, const std::vector<t_rr_node>& L_rr_node, int inode);
+
 void init_fan_in(std::vector<t_rr_node>& L_rr_node, const int num_rr_nodes);
 
 // Sets the spec for the rr_switch based on the arch switch

vpr/src/route/rr_graph_reader.cpp

@@ -55,13 +55,15 @@ void verify_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data,
 void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid);
+void process_nodes_and_switches_bin(FILE* fp, int* wire_to_rr_ipin_switch, bool is_global_graph, const std::vector<t_segment_inf>& segment_inf, int numSwitches);
 void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches);
 void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void process_rr_node_indices(const DeviceGrid& grid);
 void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
 void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const bool is_global_graph, const int num_seg_types);
+void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id);
 
 /************************ Subroutine definitions ****************************/
 
@@ -148,42 +150,61 @@ void load_rr_file(const t_graph_type graph_type,
         int max_chan_width = (is_global_graph ? 1 : nodes_per_chan.max);
         VTR_ASSERT(max_chan_width > 0);
 
-        /* Alloc rr nodes and count count nodes */
-        next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
-
-        int num_rr_nodes = count_children(next_component, "node", loc_data);
-
-        device_ctx.rr_nodes.resize(num_rr_nodes);
-        device_ctx.connection_boxes.resize_nodes(num_rr_nodes);
-        process_nodes(next_component, loc_data);
-
         /* Loads edges, switches, and node look up tables*/
         next_component = get_single_child(rr_graph, "switches", loc_data);
 
         int numSwitches = count_children(next_component, "switch", loc_data);
         device_ctx.rr_switch_inf.resize(numSwitches);
 
         process_switches(next_component, loc_data);
+        /* Branches to binary format */
+        next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL);
+        if (next_component) {
+            auto filename = get_attribute(next_component, "file", loc_data).as_string("");
+            VTR_LOG("Using Binary File: %s\n", filename);
+            FILE* fp = fopen(filename, "rb");
+            if (fp == NULL) {
+                VPR_THROW(VPR_ERROR_OTHER, "Binary File %s Does Not Exist\n", filename);
+            }
 
-        next_component = get_single_child(rr_graph, "rr_edges", loc_data);
-        process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches);
+            process_nodes_and_switches_bin(fp, wire_to_rr_ipin_switch, is_global_graph, segment_inf, numSwitches);
+
+            partition_rr_graph_edges(device_ctx);
+            process_rr_node_indices(grid);
+            init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
+            alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
+                                           max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
+
+        } else {
+            /* Alloc rr nodes and count count nodes */
+            next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
 
-        //Partition the rr graph edges for efficient access to configurable/non-configurable
-        //edge subsets. Must be done after RR switches have been allocated
-        partition_rr_graph_edges(device_ctx);
+            int num_rr_nodes = count_children(next_component, "node", loc_data);
 
-        process_rr_node_indices(grid);
+            device_ctx.rr_nodes.resize(num_rr_nodes);
+            device_ctx.connection_boxes.resize_nodes(num_rr_nodes);
+            process_nodes(next_component, loc_data);
 
-        init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
+            next_component = get_single_child(rr_graph, "rr_edges", loc_data);
+            process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches);
 
-        //sets the cost index and seg id information
-        next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
-        set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
+            //Partition the rr graph edges for efficient access to configurable/non-configurable
+            //edge subsets. Must be done after RR switches have been allocated
+            partition_rr_graph_edges(device_ctx);
 
-        alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
-                                       max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
+            process_rr_node_indices(grid);
 
-        process_seg_id(next_component, loc_data);
+            init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
+
+            //sets the cost index and seg id information
+            next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
+            set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
+
+            alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
+                                           max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
+
+            process_seg_id(next_component, loc_data);
+        }
 
         device_ctx.chan_width = nodes_per_chan;
         device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
@@ -196,6 +217,103 @@ void load_rr_file(const t_graph_type graph_type,
     }
 }
 
+void process_nodes_and_switches_bin(FILE* fp,
+                                    int* wire_to_rr_ipin_switch,
+                                    bool is_global_graph,
+                                    const std::vector<t_segment_inf>& segment_inf,
+                                    int numSwitches) {
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+    uint32_t magic_num;
+    uint16_t format_version;
+    uint16_t header_length;
+    uint64_t num_rr_nodes;
+    fread_secure(&magic_num, sizeof(magic_num), 1, fp);
+    fread_secure(&format_version, sizeof(format_version), 1, fp);
+    fread_secure(&header_length, sizeof(header_length), 1, fp);
+    char* header = new char[header_length + 1];
+    header[header_length] = '\0';
+    fread_secure(header, sizeof(char), header_length, fp);
+    fread_secure(&num_rr_nodes, sizeof(num_rr_nodes), 1, fp);
+    device_ctx.rr_nodes.resize(num_rr_nodes);
+
+    if (magic_num != BINARY_MAGIC_NUM) {
+        VTR_LOG_WARN("Not a VPR Binary rr_graph file\n");
+    }
+
+    if (format_version != BINARY_FILE_VERSION) {
+        VTR_LOG_WARN("Binary file format versions do not match\n");
+    }
+
+    int inode;
+    t_rr_type node_type;
+    uint16_t num_edges;
+    e_direction direction;
+    e_side side;
+    int edge_sink_node;
+    uint16_t edge_switch;
+    uint16_t capacity;
+    float R;
+    float C;
+    uint16_t pos[5];
+
+    for (uint64_t i = 0; i < num_rr_nodes; i++) {
+        fread_secure(&inode, sizeof(inode), 1, fp);
+        fread_secure(&node_type, sizeof(node_type), 1, fp);
+        auto& node = device_ctx.rr_nodes[inode];
+        node.set_type(node_type);
+        if (node.type() == CHANX || node.type() == CHANY) {
+            fread_secure(&direction, sizeof(direction), 1, fp);
+            node.set_direction(direction);
+        }
+
+        fread_secure(&capacity, sizeof(capacity), 1, fp);
+        if (capacity > 0)
+            node.set_capacity(capacity);
+        fread_secure(pos, sizeof(*pos), 5, fp);
+        node.set_coordinates(pos[0], pos[1], pos[2], pos[3]);
+        node.set_ptc_num(pos[4]);
+        if (node.type() == IPIN || node.type() == OPIN) {
+            fread_secure(&side, sizeof(side), 1, fp);
+            node.set_side(side);
+        }
+
+        fread_secure(&R, sizeof(R), 1, fp);
+        fread_secure(&C, sizeof(C), 1, fp);
+        node.set_rc_index(find_create_rr_rc_data(R, C));
+
+        fread_secure(&num_edges, sizeof(num_edges), 1, fp);
+
+        node.set_num_edges(num_edges);
+        for (int j = 0; j < num_edges; j++) {
+            fread_secure(&edge_sink_node, sizeof(edge_sink_node), 1, fp);
+            fread_secure(&edge_switch, sizeof(edge_switch), 1, fp);
+            node.set_edge_sink_node(j, edge_sink_node);
+            node.set_edge_switch(j, edge_switch);
+        }
+        set_cost_index_bin(inode, node_type, is_global_graph, segment_inf.size(), 0);
+    }
+    std::vector<int> count_for_wire_to_ipin_switches;
+    count_for_wire_to_ipin_switches.resize(numSwitches, 0);
+    for (uint64_t i = 0; i < num_rr_nodes; i++) {
+        auto& node = device_ctx.rr_nodes[i];
+        if (node.type() == CHANX || node.type() == CHANY) {
+            num_edges = node.num_edges();
+            for (int j = 0; j < num_edges; j++) {
+                if (device_ctx.rr_nodes[node.edge_sink_node(j)].type() == IPIN) {
+                    count_for_wire_to_ipin_switches[j]++;
+                }
+            }
+        }
+    }
+    int max = -1;
+    for (int j = 0; j < numSwitches; j++) {
+        if (count_for_wire_to_ipin_switches[j] > max) {
+            *wire_to_rr_ipin_switch = j;
+            max = count_for_wire_to_ipin_switches[j];
+        }
+    }
+}
+
 /* Reads in the switch information and adds it to device_ctx.rr_switch_inf as specified*/
 void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
@@ -940,3 +1058,30 @@ void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& l
 
     device_ctx.connection_boxes.reset_boxes(std::make_pair(x_dim, y_dim), boxes);
 }
+
+/* This function sets the Source pins, sink pins, ipin, and opin
+ * to their unique cost index identifier. CHANX and CHANY cost indicies are set after the
+ * seg_id is read in from the rr graph */
+void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id) {
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+    auto& node = device_ctx.rr_nodes[inode];
+    //set the cost index in order to load the segment information, rr nodes should be set already
+    if (node_type == SOURCE) {
+        node.set_cost_index(SOURCE_COST_INDEX);
+    } else if (node_type == SINK) {
+        node.set_cost_index(SINK_COST_INDEX);
+    } else if (node_type == IPIN) {
+        node.set_cost_index(IPIN_COST_INDEX);
+    } else if (node_type == OPIN) {
+        node.set_cost_index(OPIN_COST_INDEX);
+    } else if (node_type == CHANX || node_type == CHANY) {
+        /*CHANX and CHANY cost index is dependent on the segment id*/
+        if (is_global_graph) {
+            node.set_cost_index(0);
+        } else if (device_ctx.rr_nodes[inode].type() == CHANX) {
+            node.set_cost_index(CHANX_COST_INDEX_START + seg_id);
+        } else if (device_ctx.rr_nodes[inode].type() == CHANY) {
+            node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id);
+        }
+    }
+}

vpr/src/route/rr_graph_writer.cpp

@@ -5,6 +5,7 @@
  * children tags such as timing, location, or some general
  * details. Each tag has attributes to describe them */
 
+#include <cstdio>
 #include <fstream>
 #include <iostream>
 #include <string.h>
@@ -15,6 +16,7 @@
 #include "read_xml_arch_file.h"
 #include "vtr_version.h"
 #include "rr_graph_writer.h"
+#include "rr_graph.h"
 
 using namespace std;
 
@@ -37,6 +39,16 @@ void write_rr_segments(fstream& fp, const std::vector<t_segment_inf>& segment_in
 /* This function is used to write the rr_graph into xml format into a a file with name: file_name */
 void write_rr_graph(const char* file_name, const std::vector<t_segment_inf>& segment_inf) {
     fstream fp;
+    FILE* fb = nullptr;
+    std::stringstream header;
+    std::string filename_str(file_name);
+    bool binary_mode = (filename_str.substr(filename_str.length() - 7) == "bin.xml");
+    std::string bin_file_name;
+    if (binary_mode) {
+        bin_file_name = filename_str.substr(0, filename_str.length() - 4);
+        VTR_LOG("RR_Graph binary file %s\n", bin_file_name.c_str());
+        fb = vtr::fopen(bin_file_name.c_str(), "w");
+    }
     fp.open(file_name, fstream::out | fstream::trunc);
 
     /* Prints out general info for easy error checking*/
@@ -45,18 +57,41 @@ void write_rr_graph(const char* file_name, const std::vector<t_segment_inf>& seg
                         "couldn't open file \"%s\" for generating RR graph file\n", file_name);
     }
     cout << "Writing RR graph" << endl;
-    fp << "<rr_graph tool_name=\"vpr\" tool_version=\"" << vtr::VERSION << "\" tool_comment=\"Generated from arch file "
-       << get_arch_file_name() << "\">" << endl;
+    header << "<rr_graph tool_name=\"vpr\" tool_version=\"" << vtr::VERSION << "\" tool_comment=\"Generated from arch file "
+           << get_arch_file_name() << "\">" << endl;
+    fp << header.rdbuf();
 
     /* Write out each individual component*/
     write_rr_channel(fp);
     write_rr_switches(fp);
     write_rr_segments(fp, segment_inf);
     write_rr_block_types(fp);
     write_rr_grid(fp);
-    write_rr_node(fp);
-    write_rr_edges(fp);
-    fp << "</rr_graph>";
+    if (binary_mode) {
+        fp << "	<binary_nodes_and_edges file=\"" << bin_file_name << "\"/>\n";
+        auto& device_ctx = g_vpr_ctx.device();
+        const std::string header_s = header.str();
+        const char* header_c = header_s.c_str();
+        uint32_t magic_num = BINARY_MAGIC_NUM;
+        uint16_t format_version = BINARY_FILE_VERSION;
+        uint16_t header_length = header_s.length();
+        uint64_t num_rr_nodes = (uint64_t)device_ctx.rr_nodes.size();
+        VTR_LOG("RR_Graph binary mode\n");
+        printf("Header length: %d\n", header_length);
+        fwrite(&magic_num, sizeof(magic_num), 1, fb);
+        fwrite(&format_version, sizeof(format_version), 1, fb);
+        fwrite(&header_length, sizeof(header_length), 1, fb);
+        fwrite(&header_c, sizeof(char), header_length, fb);
+        fwrite(&num_rr_nodes, sizeof(num_rr_nodes), 1, fb);
+        for (size_t inode = 0; inode < num_rr_nodes; inode++) {
+            write_rr_node(fb, device_ctx.rr_nodes, inode);
+        }
+        fclose(fb);
+    } else {
+        write_rr_node(fp);
+        write_rr_edges(fp);
+    }
+    fp << "</rr_graph>\n";
 
     fp.close();