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Merge pull request #339 from litghost/faster_rr_graph_load
Faster rr graph load
2 parents 7b9b69d + a930800 commit 136ecda

15 files changed

+68
-29
lines changed

‎utils/fasm/src/main.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ int main(int argc, const char **argv) {
7272
vpr_setup.PackerOpts.doPacking = STAGE_LOAD;
7373
vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD;
7474
vpr_setup.RouterOpts.doRouting = STAGE_LOAD;
75+
vpr_setup.RouterOpts.read_edge_metadata = true;
7576
vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP;
7677

7778
bool flow_succeeded = false;

‎utils/fasm/test/test_fasm.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
182182
};
183183
vpr_init(sizeof(argv)/sizeof(argv[0]), argv,
184184
&options, &vpr_setup, &arch);
185+
vpr_setup.RouterOpts.read_edge_metadata = true;
185186
bool flow_succeeded = vpr_flow(vpr_setup, arch);
186187
REQUIRE(flow_succeeded == true);
187188

@@ -219,6 +220,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") {
219220
vpr_setup.PackerOpts.doPacking = STAGE_LOAD;
220221
vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD;
221222
vpr_setup.RouterOpts.doRouting = STAGE_LOAD;
223+
vpr_setup.RouterOpts.read_edge_metadata = true;
222224
vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP;
223225

224226
bool flow_succeeded = vpr_flow(vpr_setup, arch);

‎vpr/src/base/SetupVPR.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -323,6 +323,7 @@ static void SetupRoutingArch(const t_arch& Arch,
323323
}
324324

325325
static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) {
326+
RouterOpts->do_check_rr_graph = !Options.disable_check_rr_graph;
326327
RouterOpts->astar_fac = Options.astar_fac;
327328
RouterOpts->bb_factor = Options.bb_factor;
328329
RouterOpts->criticality_exp = Options.criticality_exp;

‎vpr/src/base/place_and_route.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,9 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref,
357357
router_opts.trim_obs_channels,
358358
router_opts.clock_modeling,
359359
arch->Directs, arch->num_directs,
360-
&warnings);
360+
&warnings,
361+
router_opts.read_edge_metadata,
362+
router_opts.do_check_rr_graph);
361363

362364
init_draw_coords(final);
363365
restore_routing(best_routing, route_ctx.clb_opins_used_locally, saved_clb_opins_used_locally);

‎vpr/src/base/read_options.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1658,6 +1658,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
16581658
.default_value("-2")
16591659
.show_in(argparse::ShowIn::HELP_ONLY);
16601660

1661+
route_timing_grp.add_argument<bool, ParseOnOff>(args.disable_check_rr_graph, "--disable_check_rr_graph")
1662+
.help("Disables checking rr graph when reading from disk.")
1663+
.default_value("off")
1664+
.show_in(argparse::ShowIn::HELP_ONLY);
1665+
16611666
auto& analysis_grp = parser.add_argument_group("analysis options");
16621667

16631668
analysis_grp.add_argument<bool, ParseOnOff>(args.full_stats, "--full_stats")

‎vpr/src/base/read_options.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ struct t_options {
118118
argparse::ArgValue<std::string> allowed_tiles_for_delay_model;
119119

120120
/* Router Options */
121+
argparse::ArgValue<bool> disable_check_rr_graph;
121122
argparse::ArgValue<int> max_router_iterations;
122123
argparse::ArgValue<float> first_iter_pres_fac;
123124
argparse::ArgValue<float> initial_pres_fac;

‎vpr/src/base/vpr_api.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -850,7 +850,9 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi
850850
router_opts.trim_obs_channels,
851851
router_opts.clock_modeling,
852852
arch.Directs, arch.num_directs,
853-
&warnings);
853+
&warnings,
854+
router_opts.read_edge_metadata,
855+
router_opts.do_check_rr_graph);
854856
//Initialize drawing, now that we have an RR graph
855857
init_draw_coords(chan_width_fac);
856858
}

‎vpr/src/base/vpr_types.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -911,6 +911,8 @@ enum class e_incr_reroute_delay_ripup {
911911
constexpr int NO_FIXED_CHANNEL_WIDTH = -1;
912912

913913
struct t_router_opts {
914+
bool read_edge_metadata = false;
915+
bool do_check_rr_graph = true;
914916
float first_iter_pres_fac;
915917
float initial_pres_fac;
916918
float pres_fac_mult;

‎vpr/src/route/route_common.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -228,7 +228,9 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar
228228
router_opts.trim_obs_channels,
229229
router_opts.clock_modeling,
230230
directs, num_directs,
231-
&warning_count);
231+
&warning_count,
232+
router_opts.read_edge_metadata,
233+
router_opts.do_check_rr_graph);
232234
}
233235

234236
bool try_route(int width_fac,
@@ -278,7 +280,9 @@ bool try_route(int width_fac,
278280
router_opts.trim_obs_channels,
279281
router_opts.clock_modeling,
280282
directs, num_directs,
281-
&warning_count);
283+
&warning_count,
284+
router_opts.read_edge_metadata,
285+
router_opts.do_check_rr_graph);
282286

283287
//Initialize drawing, now that we have an RR graph
284288
init_draw_coords(width_fac);

‎vpr/src/route/router_delay_profiling.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,9 @@ void alloc_routing_structs(t_chan_width chan_width,
197197
router_opts.trim_obs_channels,
198198
router_opts.clock_modeling,
199199
directs, num_directs,
200-
&warnings);
200+
&warnings,
201+
router_opts.read_edge_metadata,
202+
router_opts.do_check_rr_graph);
201203

202204
alloc_and_load_rr_node_route_structs();
203205

‎vpr/src/route/rr_graph.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,9 @@ void create_rr_graph(const t_graph_type graph_type,
319319
const enum e_clock_modeling clock_modeling,
320320
const t_direct_inf* directs,
321321
const int num_directs,
322-
int* Warnings) {
322+
int* Warnings,
323+
bool read_edge_metadata,
324+
bool do_check_rr_graph) {
323325
const auto& device_ctx = g_vpr_ctx.device();
324326

325327
if (!det_routing_arch->read_rr_graph_filename.empty()) {
@@ -331,7 +333,9 @@ void create_rr_graph(const t_graph_type graph_type,
331333
segment_inf,
332334
base_cost_type,
333335
&det_routing_arch->wire_to_rr_ipin_switch,
334-
det_routing_arch->read_rr_graph_filename.c_str());
336+
det_routing_arch->read_rr_graph_filename.c_str(),
337+
read_edge_metadata,
338+
do_check_rr_graph);
335339
}
336340
} else {
337341
if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) {

‎vpr/src/route/rr_graph.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,9 @@ void create_rr_graph(const t_graph_type graph_type,
4141
const enum e_clock_modeling clock_modeling,
4242
const t_direct_inf* directs,
4343
const int num_directs,
44-
int* Warnings);
44+
int* Warnings,
45+
bool read_edge_metadata,
46+
bool do_check_rr_graph);
4547

4648
void free_rr_graph();
4749

‎vpr/src/route/rr_graph_reader.cpp

Lines changed: 27 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -47,15 +47,15 @@
4747
#include "rr_graph_reader.h"
4848

4949
/*********************** Subroutines local to this module *******************/
50+
void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5051
void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5152
void verify_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const std::vector<t_segment_inf>& segment_inf);
5253
void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5354
void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
5455
void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid);
5556
void process_nodes_and_switches_bin(FILE* fp, int* wire_to_rr_ipin_switch, bool is_global_graph, const std::vector<t_segment_inf>& segment_inf, int numSwitches);
5657
void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
57-
void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
58-
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches);
58+
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata);
5959
void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data);
6060
void process_rr_node_indices(const DeviceGrid& grid);
6161
void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data);
@@ -72,7 +72,9 @@ void load_rr_file(const t_graph_type graph_type,
7272
const std::vector<t_segment_inf>& segment_inf,
7373
const enum e_base_cost_type base_cost_type,
7474
int* wire_to_rr_ipin_switch,
75-
const char* read_rr_graph_name) {
75+
const char* read_rr_graph_name,
76+
bool read_edge_metadata,
77+
bool do_check_rr_graph) {
7678
vtr::ScopedStartFinishTimer timer("Loading routing resource graph");
7779

7880
const char* Prop;
@@ -200,7 +202,7 @@ void load_rr_file(const t_graph_type graph_type,
200202
process_switches(next_component, loc_data);
201203

202204
next_component = get_single_child(rr_graph, "rr_edges", loc_data);
203-
process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches);
205+
process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches, read_edge_metadata);
204206

205207
//Partition the rr graph edges for efficient access to configurable/non-configurable
206208
//edge subsets. Must be done after RR switches have been allocated
@@ -219,11 +221,14 @@ void load_rr_file(const t_graph_type graph_type,
219221

220222
process_seg_id(next_component, loc_data);
221223

224+
device_ctx.connection_boxes.create_sink_back_ref();
225+
222226
device_ctx.chan_width = nodes_per_chan;
223227
device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
224228

225-
check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
226-
device_ctx.connection_boxes.create_sink_back_ref();
229+
if (do_check_rr_graph) {
230+
check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
231+
}
227232

228233
} catch (pugiutil::XmlError& e) {
229234
vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what());
@@ -530,15 +535,15 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
530535

531536
if (node.type() == IPIN || node.type() == OPIN) {
532537
e_side side;
533-
std::string side_str = get_attribute(locSubnode, "side", loc_data).as_string();
534-
if (side_str == "LEFT") {
538+
const char* side_str = get_attribute(locSubnode, "side", loc_data).as_string();
539+
if (strcmp(side_str, "LEFT") == 0) {
535540
side = LEFT;
536-
} else if (side_str == "RIGHT") {
541+
} else if (strcmp(side_str, "RIGHT") == 0) {
537542
side = RIGHT;
538-
} else if (side_str == "TOP") {
543+
} else if (strcmp(side_str, "TOP") == 0) {
539544
side = TOP;
540545
} else {
541-
VTR_ASSERT(side_str == "BOTTOM");
546+
VTR_ASSERT(strcmp(side_str, "BOTTOM") == 0);
542547
side = BOTTOM;
543548
}
544549
node.set_side(side);
@@ -582,7 +587,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
582587

583588
/*Loads the edges information from file into vpr. Nodes and switches must be loaded
584589
* before calling this function*/
585-
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches) {
590+
void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata) {
586591
auto& device_ctx = g_vpr_ctx.mutable_device();
587592
pugi::xml_node edges;
588593

@@ -656,16 +661,18 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in
656661
device_ctx.rr_nodes[source_node].set_edge_switch(num_edges_for_node[source_node], switch_id);
657662

658663
// Read the metadata for the edge
659-
auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL);
660-
if (metadata) {
661-
auto edges_meta = get_first_child(metadata, "meta", loc_data);
662-
while (edges_meta) {
663-
auto key = get_attribute(edges_meta, "name", loc_data).as_string();
664+
if (read_edge_metadata) {
665+
auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL);
666+
if (metadata) {
667+
auto edges_meta = get_first_child(metadata, "meta", loc_data);
668+
while (edges_meta) {
669+
auto key = get_attribute(edges_meta, "name", loc_data).as_string();
664670

665-
vpr::add_rr_edge_metadata(source_node, sink_node, switch_id,
666-
key, edges_meta.child_value());
671+
vpr::add_rr_edge_metadata(source_node, sink_node, switch_id,
672+
key, edges_meta.child_value());
667673

668-
edges_meta = edges_meta.next_sibling(edges_meta.name());
674+
edges_meta = edges_meta.next_sibling(edges_meta.name());
675+
}
669676
}
670677
}
671678
num_edges_for_node[source_node]++;

‎vpr/src/route/rr_graph_reader.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ void load_rr_file(const t_graph_type graph_type,
99
const std::vector<t_segment_inf>& segment_inf,
1010
const enum e_base_cost_type base_cost_type,
1111
int* wire_to_rr_ipin_switch,
12-
const char* read_rr_graph_name);
12+
const char* read_rr_graph_name,
13+
bool read_edge_metadata,
14+
bool do_check_rr_graph);
1315

1416
#endif /* RR_GRAPH_READER_H */

‎vpr/test/test_vpr.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") {
123123
};
124124
vpr_init(sizeof(argv) / sizeof(argv[0]), argv,
125125
&options, &vpr_setup, &arch);
126+
vpr_setup.RouterOpts.read_edge_metadata = true;
126127
vpr_create_device(vpr_setup, arch);
127128

128129
const auto& device_ctx = g_vpr_ctx.device();
@@ -164,6 +165,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") {
164165

165166
vpr_init(sizeof(argv) / sizeof(argv[0]), argv,
166167
&options, &vpr_setup, &arch);
168+
vpr_setup.RouterOpts.read_edge_metadata = true;
167169
vpr_create_device(vpr_setup, arch);
168170

169171
const auto& device_ctx = g_vpr_ctx.device();

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