Skip to content

Commit 07e0dc4

Browse files
committed
Merge remote-tracking branch 'vtr/master' into merge-upstream
Signed-off-by: Alessandro Comodi <[email protected]>
2 parents b2256cc + b65e201 commit 07e0dc4

22 files changed

+913
-505
lines changed

README.md

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -104,8 +104,10 @@ Professors: Kenneth Kent, Vaughn Betz, Jonathan Rose, Jason Anderson, Peter Jami
104104

105105
Research Assistants: Aaron Graham
106106

107-
Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson, Panagiotis (Panos) Patros
107+
Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Mohamed Eldafrawy, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson, Panagiotis (Panos) Patros
108108

109109
Summer Students: Opal Densmore, Ted Campbell, Cong Wang, Peter Milankov, Scott Whitty, Michael Wainberg, Suya Liu, Miad Nasr, Nooruddin Ahmed, Thien Yu, Long Yu Wang, Matthew J.P. Walker, Amer Hesson, Sheng Zhong, Hanqing Zeng, Vidya Sankaranarayanan, Jia Min Wang, Eugene Sha, Jean-Philippe Legault, Richard Ren, Dingyu Yang
110110

111-
Companies: Altera Corporation, Texas Instruments
111+
Companies: Intel, Huawei, Lattice, Altera Corporation, Texas Instruments, Google
112+
113+
Funding Agencies: NSERC, Semiconductor Research Corporation

doc/src/dev/tutorial.md

Lines changed: 41 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -7,59 +7,75 @@ Welcome to the Verilog-to-Routing (VTR) Project. This project is an open-source,
77
While you are going through this tutorial, please record down things that should be changed. Whether it is the tutorial itself, documentation, or other parts of the VTR project. Your thoughts are valuable and welcome because fresh eyes help evaluate whether or not our work is clearly presented.
88

99

10-
## Task #1 - Environment Setup ##
10+
## Environment Setup ##
1111

12-
1. Log into your workstation/personal computer. Check your account for general features such as internet, printing, git, etc. If there are problems at this stage, talk to your advisor to get this setup.
12+
Log into your workstation/personal computer. Check your account for general features such as internet, printing, git, etc. If there are problems at this stage, talk to your advisor to get this setup.
1313

14-
2. If you are not familiar with development on Linux, this is the time to get up to speed. Look up online tutorials on general commands, basic development using Makefiles, etc.
14+
If you are not familiar with development on Linux, this is the time to get up to speed. Look up online tutorials on general commands, basic development using Makefiles, etc.
1515

16-
## Task #2 - Background Reading ##
16+
## Background Reading ##
1717

18-
1. Read the first two chapters of "Architecture and CAD for deep-submicron FPGAs" by Vaughn Betz, et al. This is a great introduction to the topic of FPGA CAD and architecture. Note though that this book is old so it only covers a small core of what the VTR project is currently capable of.
18+
Read the first two chapters of "Architecture and CAD for deep-submicron FPGAs" by Vaughn Betz, et al. This is a great introduction to the topic of FPGA CAD and architecture. Note though that this book is old so it only covers a small core of what the VTR project is currently capable of.
1919

20-
2. Read chapters 1 to 5 of "FPGA Architecture: Survey and Challenges" by Ian Kuon et al.
20+
Read chapters 1 to 5 of "FPGA Architecture: Survey and Challenges" by Ian Kuon et al.
2121

22-
3. Review material learned with fellow colleagues.
22+
Review material learned with fellow colleagues.
2323

24-
## Task #3 - Setup VTR ##
24+
## Setup VTR ##
2525

26-
1. Use git to clone a copy of VTR from the [GitHub repository](https://github.com/verilog-to-routing/vtr-verilog-to-routing)
26+
Use git to clone a copy of VTR from the [GitHub repository](https://github.com/verilog-to-routing/vtr-verilog-to-routing)
2727

28-
2. Build the project
28+
Build the project by running the `make` command
2929

30-
3. Run "./run_quick_test.pl" to check that the build worked
30+
Run `./run_quick_test.pl` to check that the build worked
3131

32-
4. Follow the Basic Design Flow Tutorial found in the Tutorials section of the [documentation](https://vtr.readthedocs.io/en/latest). This tutorial will allow you to run a circuit through the entire flow and read the statistics gathered from that run.
32+
Follow the Basic Design Flow Tutorial found in the Tutorials section of the [Welcome to Verilog-to-Routing's documentation!](https://vtr.readthedocs.io/en/latest). This tutorial will allow you to run a circuit through the entire flow and read the statistics gathered from that run.
3333

34-
## Task #4 - Use VTR ##
34+
## Use VTR ##
3535

36-
1. Create your own custom Verilog file. Create your own custom architecture file using one of the existing architecture files as a template. Use VTR to map that circuit that you created to that architecture that you created. The VTR documentation, to be found at [Welcome to Verilog-to-Routing's documention!](https://vtr.readthedocs.io/en/latest/) will prove useful. You may also wish to look at the following links for descriptions of the language used inside the architecture files:
36+
Create your own custom Verilog file. Create your own custom architecture file using one of the existing architecture files as a template. Use VTR to map that circuit that you created to that architecture that you created. The VTR documentation, to be found at the [Welcome to Verilog-to-Routing's documentation!](https://vtr.readthedocs.io/en/latest/) will prove useful. You may also wish to look at the following links for descriptions of the language used inside the architecture files:
3737
* [Architecture Description and Packing](http://www.eecg.utoronto.ca/~jluu/publications/luu_vpr_fpga2011.pdf)
3838
* [Classical Soft Logic Block Example](http://www.eecg.utoronto.ca/vpr/utfal_ex1.html)
3939

40-
2. Perform a simple architecture experiment. Run an experiment that varies Fc_in from 0.01 to 1.00 on the benchmarks ch_intrinsics, or1200, and sha. Use tasks/timing as your template. Graph the geometric average of minimum channel width and critical path delay for these three benchmarks across your different values of Fc_in. Review the results with your colleagues and/or advisor.
40+
Perform a simple architecture experiment. Run an experiment that varies Fc_in from 0.01 to 1.00 on the benchmarks ch_intrinsics, or1200, and sha. Use `tasks/timing` as your template. Graph the geometric average of minimum channel width and critical path delay for these three benchmarks across your different values of Fc_in. Review the results with your colleagues and/or advisor.
4141

42-
## Task #5 - Open the Black Box ##
42+
## Open the Black Box ##
4343

44-
At this stage, you have gotten a taste of how an FPGA architect would go about using VTR. As a developer though, you need a much deeper understanding of how this tool works. The purpose of this section is to have you to learn the details of the VTR CAD flow by having you manually do what the scripts do.
44+
At this stage, you have gotten a taste of how an FPGA architect would go about using VTR. As a developer though, you need a much deeper understanding of how this tool works. The purpose of this section is to have you to learn the details of the VTR CAD flow by having you manually do what the scripts do.
4545

46-
1. Using the custom Verilog circuit and architecture created in Task #4, directly run Odin II on it to generate a blif netlist. You may need to skim the Odin II readme file and the vtr_flow/scripts/run_vtr_flow.pl.
46+
Using the custom Verilog circuit and architecture created in the previous step, directly run Odin II on it to generate a blif netlist. You may need to skim the `ODIN_II/README.rst` and the `vtr_flow/scripts/run_vtr_flow.pl`.
4747

48-
2. Using the output netlist of Odin II, run ABC to generate a technology-mapped blif file. You may need to skim vtr_flow/scripts/run_vtr_flow.pl.
4948

50-
3. Using the output of ABC, run VPR to complete the mapping of a user circuit to a target architecture. You may need to consult the VPR User Manual and skim vtr_flow/scripts/run_vtr_flow.pl.
49+
Using the output netlist of Odin II, run ABC to generate a technology-mapped blif file. You may need to skim the [ABC homepage](http://www.eecs.berkeley.edu/~alanmi/abc/).
50+
```shell
51+
# Run the ABC program from regular terminal (bash shell)
52+
$VTR_ROOT/abc abc
5153

52-
4. Read the VPR section of the online documentation.
54+
# Using the ABC shell to read and write blif file
55+
abc 01> read_blif Odin_II_output.blif
56+
abc 01> write_blif abc_output.blif
57+
```
5358

54-
## Task #6 - Submitting Changes and Regression Testing ##
59+
Using the output of ABC and your architecture file, run VPR to complete the mapping of a user circuit to a target architecture. You may need to consult the VPR User Manual.
5560

56-
1. Read README.developers.md in the base directory of VTR. Code changes rapidly so please help keep this up to date if you see something that is out of date.
61+
```shell
62+
# Run the VPR program
63+
$VTR_ROOT/vpr vpr architecture.xml abc_output.blif
64+
```
5765

58-
2. Make your first change to git by modifying README.txt and pushing it. I recommend adding your name to the list of contributors. If you have nothing to modify, just add/remove a line of whitespace at the bottom of the file.
66+
Read the VPR section of the online documentation.
67+
68+
## Submitting Changes and Regression Testing ##
69+
70+
Read `README.developers.md` in the base directory of VTR. Code changes rapidly so please help keep this up to date if you see something that is out of date.
71+
72+
Make your first change to git by modifying `README.txt` and pushing it. I recommend adding your name to the list of contributors. If you have nothing to modify, just add/remove a line of whitespace at the bottom of the file.
5973

6074

6175
Now that you have completed the tutorial, you should have a general sense of what the VTR project is about and how the different parts work together. It's time to talk to your advisor to get your first assignment.
6276

6377

64-
#### Good luck! ####
78+
79+
80+
6581

doc/src/vpr/graphics.rst

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -86,3 +86,67 @@ Each stage between primitive pins is shown in a different colour.
8686
Cliking the **Crit. Path** button again will toggle through the various visualizations:
8787
* During placement the critical path is shown only as flylines.
8888
* During routing the critical path can be shown as both flylines and routed net connections.
89+
90+
Button Description Table
91+
------------------------
92+
+-------------------+-------------------+------------------------------+------------------------------+
93+
| Buttons | Stages | Functionalities | Detailed Descriptions |
94+
+-------------------+-------------------+------------------------------+------------------------------+
95+
| Blk Internal | Placement/Routing | Controls depth of sub-blocks | Click multiple times to show |
96+
| | | shown | more details; Click to reset |
97+
| | | | when reached maximum level |
98+
| | | | of detail |
99+
+-------------------+-------------------+------------------------------+------------------------------+
100+
| Blk Pin Util | Placement/Routing | Visualizes block pin | Click multiple times to |
101+
| | | utilization | visualize all block pin |
102+
| | | | utilization, input block pin |
103+
| | | | utilization, or output block |
104+
| | | | pin utilization |
105+
+-------------------+-------------------+------------------------------+------------------------------+
106+
| Cong. Cost | Routing | Visualizes the congestion | |
107+
| | | costs of routing resouces | |
108+
| | | | |
109+
| | | | |
110+
+-------------------+-------------------+------------------------------+------------------------------+
111+
| Congestion | Routing | Visualizes a heat map of | |
112+
| | | overused routing resources | |
113+
| | | | |
114+
| | | | |
115+
+-------------------+-------------------+------------------------------+------------------------------+
116+
| Crit. Path | Placement/Routing | Visualizes the critical path | |
117+
| | | of the circuit | |
118+
| | | | |
119+
| | | | |
120+
+-------------------+-------------------+------------------------------+------------------------------+
121+
| Place Macros | Placement/Routing | Visualizes placement macros | |
122+
| | | | |
123+
| | | | |
124+
| | | | |
125+
+-------------------+-------------------+------------------------------+------------------------------+
126+
| Route BB | Routing | Visualizes net bounding | Click multiple times to |
127+
| | | boxes one by one | sequence through the net |
128+
| | | | being shown |
129+
| | | | |
130+
+-------------------+-------------------+------------------------------+------------------------------+
131+
| Router Cost | Routing | Visualizes the router costs | |
132+
| | | of different routing | |
133+
| | | resources | |
134+
| | | | |
135+
+-------------------+-------------------+------------------------------+------------------------------+
136+
| Routing Util | Routing | Visualizes routing channel | |
137+
| | | utilization with colors | |
138+
| | | indicating the fraction of | |
139+
| | | wires used within a channel | |
140+
+-------------------+-------------------+------------------------------+------------------------------+
141+
| Toggle Nets | Placement/Routing | Visualizes the nets in the | Click multiple times to |
142+
| | | circuit | set the nets to be visible / |
143+
| | | | invisible |
144+
| | | | |
145+
+-------------------+-------------------+------------------------------+------------------------------+
146+
| Toggle RR | Placement/Routing | Visualizes different views | Click multiple times to |
147+
| | | of the routing resources | switch between routing |
148+
| | | | resources available in the |
149+
| | | | FPGA |
150+
+-------------------+-------------------+------------------------------+------------------------------+
151+
152+

libs/libarchfpga/src/physical_types.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -874,12 +874,13 @@ struct t_pin_to_pin_annotation {
874874
* accessible from each position may be different).
875875
*
876876
* Data members:
877-
* pb_type: Pointer to the type of pb graph node this belongs to
878-
* mode: parent mode of operation
879-
* placement_index: there are a certain number of pbs available, this gives the index of the node
880-
* illegal_modes: vector containing illigal modes that result in conflicts during routing
881-
* child_pb_graph_nodes: array of children pb graph nodes organized into modes
882-
* parent_pb_graph_node: parent pb graph node
877+
* pb_type : Pointer to the type of pb graph node this belongs to
878+
* placement_index : there are a certain number of pbs available, this gives the index of the node
879+
* child_pb_graph_nodes : array of children pb graph nodes organized into modes
880+
* parent_pb_graph_node : parent pb graph node
881+
* total_primitive_count : Total number of this primitive type in the cluster. If there are 10 ALMs per cluster
882+
* and 2 FFs per ALM (given the mode of the parent of this primitive) then the total is 20.
883+
* illegal_modes : vector containing illigal modes that result in conflicts during routing.
883884
*/
884885
class t_pb_graph_node {
885886
public:
@@ -914,6 +915,8 @@ class t_pb_graph_node {
914915
int *output_pin_class_size; /* Stores the number of pins that belong to a particular output pin class */
915916
int num_output_pin_class; /* number of output pin classes that this pb_graph_node has */
916917

918+
int total_primitive_count; /* total number of this primitive type in the cluster */
919+
917920
/* Interconnect instances for this pb
918921
* Only used for power
919922
*/

utils/fasm/src/fasm.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,9 @@ void FasmWriterVisitor::visit_clb_impl(ClusterBlockId blk_id, const t_pb* clb) {
5050

5151
root_clb_ = clb->pb_graph_node;
5252

53-
int x = place_ctx.block_locs[blk_id].x;
54-
int y = place_ctx.block_locs[blk_id].y;
55-
int z = place_ctx.block_locs[blk_id].z;
53+
int x = place_ctx.block_locs[blk_id].loc.x;
54+
int y = place_ctx.block_locs[blk_id].loc.y;
55+
int z = place_ctx.block_locs[blk_id].loc.z;
5656
auto &grid_loc = device_ctx.grid[x][y];
5757
blk_type_ = grid_loc.type;
5858

0 commit comments

Comments
 (0)