vsimd: simd128: tests

Nugine · Nugine · commit f6ea65131aff · 2022-10-06T23:26:07.000+08:00
diff --git a/crates/vsimd/src/simd128.rs b/crates/vsimd/src/simd128.rs
@@ -1818,12 +1818,15 @@ mod tests {
     fn u8x16_any_zero() {
         fn test(a: [u8; 16], expected: bool) {
             let a = V128::from_bytes(a);
+            #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
             if let Some(s) = SSE41::detect() {
                 assert_eq!(s.u8x16_any_zero(a), expected);
             }
+            #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
             if let Some(s) = NEON::detect() {
                 assert_eq!(s.u8x16_any_zero(a), expected);
             }
+            #[cfg(target_arch = "wasm32")]
             if let Some(s) = WASM128::detect() {
                 assert_eq!(s.u8x16_any_zero(a), expected);
             }

Original file line number	Diff line number	Diff line change
`@@ -1818,12 +1818,15 @@ mod tests {`
`1818`	`1818`	`fn u8x16_any_zero() {`
`1819`	`1819`	`fn test(a: [u8; 16], expected: bool) {`
`1820`	`1820`	`let a = V128::from_bytes(a);`
	`1821`	`+ #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]`
`1821`	`1822`	`if let Some(s) = SSE41::detect() {`
`1822`	`1823`	`assert_eq!(s.u8x16_any_zero(a), expected);`
`1823`	`1824`	`}`
	`1825`	`+ #[cfg(any(target_arch = "arm", target_arch = "aarch64"))]`
`1824`	`1826`	`if let Some(s) = NEON::detect() {`
`1825`	`1827`	`assert_eq!(s.u8x16_any_zero(a), expected);`
`1826`	`1828`	`}`
	`1829`	`+ #[cfg(target_arch = "wasm32")]`
`1827`	`1830`	`if let Some(s) = WASM128::detect() {`
`1828`	`1831`	`assert_eq!(s.u8x16_any_zero(a), expected);`
`1829`	`1832`	`}`