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| 1 | + |
| 2 | +./sketch_sep18a.ino.elf: file format elf32-avr |
| 3 | + |
| 4 | + |
| 5 | +Disassembly of section .text: |
| 6 | + |
| 7 | +00000000 <__vectors>: |
| 8 | + 0: 0c 94 35 00 jmp 0x6a ; 0x6a <__ctors_end> |
| 9 | + 4: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 10 | + 8: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 11 | + c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 12 | + 10: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 13 | + 14: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 14 | + 18: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 15 | + 1c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 16 | + 20: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 17 | + 24: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 18 | + 28: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 19 | + 2c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 20 | + 30: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 21 | + 34: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 22 | + 38: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 23 | + 3c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 24 | + 40: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 25 | + 44: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 26 | + 48: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 27 | + 4c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 28 | + 50: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 29 | + 54: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 30 | + 58: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 31 | + 5c: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 32 | + 60: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 33 | + 64: 0c 94 52 00 jmp 0xa4 ; 0xa4 <__bad_interrupt> |
| 34 | + |
| 35 | +00000068 <__ctors_start>: |
| 36 | + 68: ba 00 .word 0x00ba ; ???? |
| 37 | + |
| 38 | +0000006a <__ctors_end>: |
| 39 | + 6a: 11 24 eor r1, r1 |
| 40 | + 6c: 1f be out 0x3f, r1 ; 63 |
| 41 | + 6e: cf ef ldi r28, 0xFF ; 255 |
| 42 | + 70: d8 e0 ldi r29, 0x08 ; 8 |
| 43 | + 72: de bf out 0x3e, r29 ; 62 |
| 44 | + 74: cd bf out 0x3d, r28 ; 61 |
| 45 | + |
| 46 | +00000076 <__do_clear_bss>: |
| 47 | + 76: 21 e0 ldi r18, 0x01 ; 1 |
| 48 | + 78: a0 e0 ldi r26, 0x00 ; 0 |
| 49 | + 7a: b1 e0 ldi r27, 0x01 ; 1 |
| 50 | + 7c: 01 c0 rjmp .+2 ; 0x80 <.do_clear_bss_start> |
| 51 | + |
| 52 | +0000007e <.do_clear_bss_loop>: |
| 53 | + 7e: 1d 92 st X+, r1 |
| 54 | + |
| 55 | +00000080 <.do_clear_bss_start>: |
| 56 | + 80: a8 34 cpi r26, 0x48 ; 72 |
| 57 | + 82: b2 07 cpc r27, r18 |
| 58 | + 84: e1 f7 brne .-8 ; 0x7e <.do_clear_bss_loop> |
| 59 | + |
| 60 | +00000086 <__do_global_ctors>: |
| 61 | + 86: 10 e0 ldi r17, 0x00 ; 0 |
| 62 | + 88: ca e6 ldi r28, 0x6A ; 106 |
| 63 | + 8a: d0 e0 ldi r29, 0x00 ; 0 |
| 64 | + 8c: 04 c0 rjmp .+8 ; 0x96 <__do_global_ctors+0x10> |
| 65 | + 8e: 22 97 sbiw r28, 0x02 ; 2 |
| 66 | + 90: fe 01 movw r30, r28 |
| 67 | + 92: 0e 94 d8 00 call 0x1b0 ; 0x1b0 <__tablejump__> |
| 68 | + 96: c8 36 cpi r28, 0x68 ; 104 |
| 69 | + 98: d1 07 cpc r29, r17 |
| 70 | + 9a: c9 f7 brne .-14 ; 0x8e <__do_global_ctors+0x8> |
| 71 | + 9c: 0e 94 d1 00 call 0x1a2 ; 0x1a2 <main> |
| 72 | + a0: 0c 94 dc 00 jmp 0x1b8 ; 0x1b8 <_exit> |
| 73 | + |
| 74 | +000000a4 <__bad_interrupt>: |
| 75 | + a4: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> |
| 76 | + |
| 77 | +000000a8 <setup>: |
| 78 | + a8: 61 e6 ldi r22, 0x61 ; 97 |
| 79 | + aa: 80 e0 ldi r24, 0x00 ; 0 |
| 80 | + ac: 91 e0 ldi r25, 0x01 ; 1 |
| 81 | + ae: 0c 94 61 00 jmp 0xc2 ; 0xc2 <_ZN14HardwareSerial5writeEh> |
| 82 | + |
| 83 | +000000b2 <loop>: |
| 84 | + b2: 08 95 ret |
| 85 | + |
| 86 | +000000b4 <_ZN14HardwareSerial17_tx_udr_empty_irqEv>: |
| 87 | + |
| 88 | +// Actual interrupt handlers ////////////////////////////////////////////////////////////// |
| 89 | + |
| 90 | +void HardwareSerial::_tx_udr_empty_irq(void) |
| 91 | +{ |
| 92 | + sbi(*_ucsra, TXC0); |
| 93 | + b4: dc 01 movw r26, r24 |
| 94 | + b6: ed 91 ld r30, X+ |
| 95 | + b8: fc 91 ld r31, X |
| 96 | + ba: 80 81 ld r24, Z |
| 97 | + bc: 80 64 ori r24, 0x40 ; 64 |
| 98 | + be: 80 83 st Z, r24 |
| 99 | + c0: 08 95 ret |
| 100 | + |
| 101 | +000000c2 <_ZN14HardwareSerial5writeEh>: |
| 102 | +} |
| 103 | + |
| 104 | +size_t HardwareSerial::write(uint8_t c) |
| 105 | +{ |
| 106 | + c2: cf 92 push r12 |
| 107 | + c4: df 92 push r13 |
| 108 | + c6: ff 92 push r15 |
| 109 | + c8: 0f 93 push r16 |
| 110 | + ca: 1f 93 push r17 |
| 111 | + cc: cf 93 push r28 |
| 112 | + ce: df 93 push r29 |
| 113 | + d0: 1f 92 push r1 |
| 114 | + d2: cd b7 in r28, 0x3d ; 61 |
| 115 | + d4: de b7 in r29, 0x3e ; 62 |
| 116 | + d6: 6c 01 movw r12, r24 |
| 117 | + // If the buffer and the data register is empty, just write the byte |
| 118 | + // to the data register and be done. This shortcut helps |
| 119 | + // significantly improve the effective datarate at high (> |
| 120 | + // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. |
| 121 | + if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { |
| 122 | + d8: dc 01 movw r26, r24 |
| 123 | + da: 16 96 adiw r26, 0x06 ; 6 |
| 124 | + dc: 9c 91 ld r25, X |
| 125 | + de: 16 97 sbiw r26, 0x06 ; 6 |
| 126 | + e0: 17 96 adiw r26, 0x07 ; 7 |
| 127 | + e2: 8c 91 ld r24, X |
| 128 | + e4: 17 97 sbiw r26, 0x07 ; 7 |
| 129 | + e6: 98 13 cpse r25, r24 |
| 130 | + e8: 05 c0 rjmp .+10 ; 0xf4 <_ZN14HardwareSerial5writeEh+0x32> |
| 131 | + ea: ed 91 ld r30, X+ |
| 132 | + ec: fc 91 ld r31, X |
| 133 | + ee: 80 81 ld r24, Z |
| 134 | + f0: 85 fd sbrc r24, 5 |
| 135 | + f2: 2a c0 rjmp .+84 ; 0x148 <_ZN14HardwareSerial5writeEh+0x86> |
| 136 | + *_udr = c; |
| 137 | + sbi(*_ucsra, TXC0); |
| 138 | + return 1; |
| 139 | + } |
| 140 | + |
| 141 | + tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE; |
| 142 | + f4: f6 01 movw r30, r12 |
| 143 | + f6: 06 81 ldd r16, Z+6 ; 0x06 |
| 144 | + f8: 10 e0 ldi r17, 0x00 ; 0 |
| 145 | + fa: 0f 5f subi r16, 0xFF ; 255 |
| 146 | + fc: 1f 4f sbci r17, 0xFF ; 255 |
| 147 | + fe: 0f 73 andi r16, 0x3F ; 63 |
| 148 | + 100: 11 27 eor r17, r17 |
| 149 | + 102: f0 2e mov r15, r16 |
| 150 | + |
| 151 | + // If the output buffer is full, there's nothing for it other than to |
| 152 | + // wait for the interrupt handler to empty it a bit |
| 153 | + while (i == _tx_buffer_tail) { |
| 154 | + 104: f6 01 movw r30, r12 |
| 155 | + 106: 87 81 ldd r24, Z+7 ; 0x07 |
| 156 | + 108: f8 12 cpse r15, r24 |
| 157 | + 10a: 0f c0 rjmp .+30 ; 0x12a <_ZN14HardwareSerial5writeEh+0x68> |
| 158 | + if (bit_is_clear(SREG, SREG_I)) { |
| 159 | + 10c: 0f b6 in r0, 0x3f ; 63 |
| 160 | + 10e: 07 fc sbrc r0, 7 |
| 161 | + 110: f9 cf rjmp .-14 ; 0x104 <_ZN14HardwareSerial5writeEh+0x42> |
| 162 | + // Interrupts are disabled, so we'll have to poll the data |
| 163 | + // register empty flag ourselves. If it is set, pretend an |
| 164 | + // interrupt has happened and call the handler to free up |
| 165 | + // space for us. |
| 166 | + if(bit_is_set(*_ucsra, UDRE0)) |
| 167 | + 112: d6 01 movw r26, r12 |
| 168 | + 114: ed 91 ld r30, X+ |
| 169 | + 116: fc 91 ld r31, X |
| 170 | + 118: 80 81 ld r24, Z |
| 171 | + 11a: 85 ff sbrs r24, 5 |
| 172 | + 11c: f3 cf rjmp .-26 ; 0x104 <_ZN14HardwareSerial5writeEh+0x42> |
| 173 | + _tx_udr_empty_irq(); |
| 174 | + 11e: c6 01 movw r24, r12 |
| 175 | + 120: 69 83 std Y+1, r22 ; 0x01 |
| 176 | + 122: 0e 94 5a 00 call 0xb4 ; 0xb4 <_ZN14HardwareSerial17_tx_udr_empty_irqEv> |
| 177 | + 126: 69 81 ldd r22, Y+1 ; 0x01 |
| 178 | + 128: ed cf rjmp .-38 ; 0x104 <_ZN14HardwareSerial5writeEh+0x42> |
| 179 | + } else { |
| 180 | + // nop, the interrupt handler will free up space for us |
| 181 | + } |
| 182 | + } |
| 183 | + |
| 184 | + _tx_buffer[_tx_buffer_head] = c; |
| 185 | + 12a: 86 81 ldd r24, Z+6 ; 0x06 |
| 186 | + 12c: e8 0f add r30, r24 |
| 187 | + 12e: f1 1d adc r31, r1 |
| 188 | + 130: 60 87 std Z+8, r22 ; 0x08 |
| 189 | + _tx_buffer_head = i; |
| 190 | + 132: d6 01 movw r26, r12 |
| 191 | + 134: 16 96 adiw r26, 0x06 ; 6 |
| 192 | + 136: 0c 93 st X, r16 |
| 193 | + 138: 16 97 sbiw r26, 0x06 ; 6 |
| 194 | + |
| 195 | + sbi(*_ucsrb, UDRIE0); |
| 196 | + 13a: 12 96 adiw r26, 0x02 ; 2 |
| 197 | + 13c: ed 91 ld r30, X+ |
| 198 | + 13e: fc 91 ld r31, X |
| 199 | + 140: 13 97 sbiw r26, 0x03 ; 3 |
| 200 | + 142: 80 81 ld r24, Z |
| 201 | + 144: 80 62 ori r24, 0x20 ; 32 |
| 202 | + 146: 0a c0 rjmp .+20 ; 0x15c <_ZN14HardwareSerial5writeEh+0x9a> |
| 203 | + // If the buffer and the data register is empty, just write the byte |
| 204 | + // to the data register and be done. This shortcut helps |
| 205 | + // significantly improve the effective datarate at high (> |
| 206 | + // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown. |
| 207 | + if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) { |
| 208 | + *_udr = c; |
| 209 | + 148: d6 01 movw r26, r12 |
| 210 | + 14a: 14 96 adiw r26, 0x04 ; 4 |
| 211 | + 14c: ed 91 ld r30, X+ |
| 212 | + 14e: fc 91 ld r31, X |
| 213 | + 150: 15 97 sbiw r26, 0x05 ; 5 |
| 214 | + 152: 60 83 st Z, r22 |
| 215 | + sbi(*_ucsra, TXC0); |
| 216 | + 154: ed 91 ld r30, X+ |
| 217 | + 156: fc 91 ld r31, X |
| 218 | + 158: 80 81 ld r24, Z |
| 219 | + 15a: 80 64 ori r24, 0x40 ; 64 |
| 220 | + 15c: 80 83 st Z, r24 |
| 221 | + _tx_buffer_head = i; |
| 222 | + |
| 223 | + sbi(*_ucsrb, UDRIE0); |
| 224 | + |
| 225 | + return 1; |
| 226 | +} |
| 227 | + 15e: 81 e0 ldi r24, 0x01 ; 1 |
| 228 | + 160: 90 e0 ldi r25, 0x00 ; 0 |
| 229 | + 162: 0f 90 pop r0 |
| 230 | + 164: df 91 pop r29 |
| 231 | + 166: cf 91 pop r28 |
| 232 | + 168: 1f 91 pop r17 |
| 233 | + 16a: 0f 91 pop r16 |
| 234 | + 16c: ff 90 pop r15 |
| 235 | + 16e: df 90 pop r13 |
| 236 | + 170: cf 90 pop r12 |
| 237 | + 172: 08 95 ret |
| 238 | + |
| 239 | +00000174 <_GLOBAL__sub_I__ZN14HardwareSerial17_tx_udr_empty_irqEv>: |
| 240 | + volatile uint8_t *udr): |
| 241 | + _ucsra(ucsra), _ucsrb(ucsrb), |
| 242 | + _udr(udr), |
| 243 | + _tx_buffer_head(0), _tx_buffer_tail(0) |
| 244 | +{ |
| 245 | +} |
| 246 | + 174: 80 ec ldi r24, 0xC0 ; 192 |
| 247 | + 176: 90 e0 ldi r25, 0x00 ; 0 |
| 248 | + 178: 90 93 01 01 sts 0x0101, r25 |
| 249 | + 17c: 80 93 00 01 sts 0x0100, r24 |
| 250 | + 180: 81 ec ldi r24, 0xC1 ; 193 |
| 251 | + 182: 90 e0 ldi r25, 0x00 ; 0 |
| 252 | + 184: 90 93 03 01 sts 0x0103, r25 |
| 253 | + 188: 80 93 02 01 sts 0x0102, r24 |
| 254 | + 18c: 86 ec ldi r24, 0xC6 ; 198 |
| 255 | + 18e: 90 e0 ldi r25, 0x00 ; 0 |
| 256 | + 190: 90 93 05 01 sts 0x0105, r25 |
| 257 | + 194: 80 93 04 01 sts 0x0104, r24 |
| 258 | + 198: 10 92 06 01 sts 0x0106, r1 |
| 259 | + 19c: 10 92 07 01 sts 0x0107, r1 |
| 260 | + 1a0: 08 95 ret |
| 261 | + |
| 262 | +000001a2 <main>: |
| 263 | +#include <Arduino.h> |
| 264 | +int main(void) |
| 265 | +{ |
| 266 | + setup(); |
| 267 | + 1a2: 0e 94 54 00 call 0xa8 ; 0xa8 <setup> |
| 268 | + for (;;) { |
| 269 | + loop(); |
| 270 | + 1a6: 0e 94 59 00 call 0xb2 ; 0xb2 <loop> |
| 271 | + 1aa: fd cf rjmp .-6 ; 0x1a6 <main+0x4> |
| 272 | + |
| 273 | +000001ac <__tablejump2__>: |
| 274 | + 1ac: ee 0f add r30, r30 |
| 275 | + 1ae: ff 1f adc r31, r31 |
| 276 | + |
| 277 | +000001b0 <__tablejump__>: |
| 278 | + 1b0: 05 90 lpm r0, Z+ |
| 279 | + 1b2: f4 91 lpm r31, Z |
| 280 | + 1b4: e0 2d mov r30, r0 |
| 281 | + 1b6: 09 94 ijmp |
| 282 | + |
| 283 | +000001b8 <_exit>: |
| 284 | + 1b8: f8 94 cli |
| 285 | + |
| 286 | +000001ba <__stop_program>: |
| 287 | + 1ba: ff cf rjmp .-2 ; 0x1ba <__stop_program> |
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