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Jamie Smith
authored
More fixes for sleep and clocking stuff on MIMXRT105x (ARMmbed#158)
* More fixes for sleep and clocking stuff on MIMXRT105x * Fix a couple of inadvertent changes
1 parent 04a76b3 commit b9c0481

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11 files changed

+135
-106
lines changed

11 files changed

+135
-106
lines changed

‎drivers/tests/TESTS/mbed_drivers/ticker/main.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,7 @@ void test_multi_ticker(void)
185185
}
186186

187187
ThisThread::sleep_for(MULTI_TICKER_TIME + extra_wait);
188+
188189
TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
189190

190191
for (int i = 0; i < TICKER_COUNT; i++) {

‎hal/tests/TESTS/mbed_hal/sleep/main.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@
2020

2121
#include "mbed.h"
2222

23+
#include <cinttypes>
24+
2325
#include "utest/utest.h"
2426
#include "unity/unity.h"
2527
#include "greentea-client/test_env.h"
@@ -146,7 +148,7 @@ void deepsleep_lpticker_test()
146148

147149
const timestamp_t wakeup_timestamp = lp_ticker_read();
148150

149-
sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d, delay ticks: %d, wake up after ticks: %d",
151+
sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %" PRIu32 ", delay ticks: %d, wake up after ticks: %" PRIu32 "\n",
150152
us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width, next_match_timestamp, wakeup_timestamp, us_to_ticks(i, ticker_freq), wakeup_timestamp - start_timestamp);
151153

152154
TEST_ASSERT_MESSAGE(compare_timestamps(us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width,
@@ -196,7 +198,7 @@ void deepsleep_high_speed_clocks_turned_off_test()
196198

197199
TEST_ASSERT_UINT32_WITHIN(1000, 0, ticks_to_us(us_ticks_diff, us_ticker_freq));
198200

199-
sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d",
201+
sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %d\n",
200202
us_to_ticks(deepsleep_mode_delta_us, lp_ticker_freq), lp_ticker_width, wakeup_time, lp_ticks_after_sleep);
201203

202204
/* Check if we have woken-up after expected time. */

‎hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,12 @@
2828
#error [NOT_SUPPORTED] test not supported
2929
#else
3030

31-
#define SLEEP_DURATION_US 20000ULL
31+
#define SLEEP_DURATION_US 50000ULL
32+
33+
// Tolerance for extra sleep time in the deep sleep test.
34+
// Current leader is the MIMXRT105x, which takes almost 5ms to enter/exit deep sleep.
35+
#define DEEP_SLEEP_TOLERANCE_US 5000ULL
36+
3237
#define DEEP_SLEEP_TEST_CHECK_WAIT_US 2000
3338
// As sleep_manager_can_deep_sleep_test_check() is based on wait_ns
3439
// and wait_ns can be up to 40% slower, use a 50% delta here.
@@ -217,9 +222,12 @@ void test_sleep_auto()
217222
// 1. current lp_ticker increment,
218223
// 2. previous us_ticker increment (locked sleep test above)
219224

225+
const unsigned int deepsleep_tolerance_lp_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, lp_ticker_info->frequency);
226+
const unsigned int deepsleep_tolerance_us_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, us_ticker_info->frequency);
227+
220228
// us ticker should not have incremented during deep sleep. It should be zero, plus some tolerance for the time to enter deep sleep.
221-
TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_us_ticks / 10ULL, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
222-
TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_lp_ticks / 10ULL, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
229+
TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_us_ticks, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
230+
TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_lp_ticks, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
223231

224232
set_us_ticker_irq_handler(us_ticker_irq_handler_org);
225233
set_lp_ticker_irq_handler(lp_ticker_irq_handler_org);

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c

Lines changed: 52 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,13 @@
2020
*
2121
*/
2222

23-
2423
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
2524
!!GlobalInfo
2625
product: Clocks v11.0
2726
processor: MIMXRT1052xxxxB
2827
package_id: MIMXRT1052DVL6B
2928
mcu_data: ksdk2_0
30-
processor_version: 13.0.1
29+
processor_version: 13.0.2
3130
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
3231

3332
#include "clock_config.h"
@@ -46,6 +45,7 @@ processor_version: 13.0.1
4645
******************************************************************************/
4746
void BOARD_InitBootClocks(void)
4847
{
48+
BOARD_ClockOverdrive();
4949
}
5050

5151
/*******************************************************************************
@@ -66,15 +66,15 @@ name: BOARD_ClockFullSpeed
6666
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
6767
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
6868
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
69-
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
70-
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
69+
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
70+
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
7171
- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
7272
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
73-
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74-
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
73+
- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
74+
- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
7575
- {id: LVDS1_CLK.outFreq, value: 1.056 GHz}
7676
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
77-
- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
77+
- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
7878
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
7979
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
8080
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -89,18 +89,22 @@ name: BOARD_ClockFullSpeed
8989
- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
9090
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
9191
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
92-
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
92+
- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
9393
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
9494
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
9595
settings:
9696
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
9797
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
9898
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
9999
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
100-
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
101-
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
100+
- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
101+
- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
102+
- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
103+
- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
104+
- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
102105
- {id: CCM.SEMC_PODF.scale, value: '8'}
103106
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
107+
- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
104108
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
105109
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
106110
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '44', locked: true}
@@ -194,7 +198,7 @@ void BOARD_ClockFullSpeed(void)
194198
CLOCK_DisableClock(kCLOCK_Gpt2S);
195199
CLOCK_DisableClock(kCLOCK_Pit);
196200
/* Set PERCLK_PODF. */
197-
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
201+
CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
198202
/* Disable USDHC1 clock gate. */
199203
CLOCK_DisableClock(kCLOCK_Usdhc1);
200204
/* Set USDHC1_PODF. */
@@ -243,9 +247,9 @@ void BOARD_ClockFullSpeed(void)
243247
CLOCK_DisableClock(kCLOCK_Lpspi3);
244248
CLOCK_DisableClock(kCLOCK_Lpspi4);
245249
/* Set LPSPI_PODF. */
246-
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
250+
CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
247251
/* Set Lpspi clock source. */
248-
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
252+
CLOCK_SetMux(kCLOCK_LpspiMux, 1);
249253
/* Disable TRACE clock gate. */
250254
CLOCK_DisableClock(kCLOCK_Trace);
251255
/* Set TRACE_PODF. */
@@ -281,7 +285,7 @@ void BOARD_ClockFullSpeed(void)
281285
CLOCK_DisableClock(kCLOCK_Lpi2c2);
282286
CLOCK_DisableClock(kCLOCK_Lpi2c3);
283287
/* Set LPI2C_CLK_PODF. */
284-
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
288+
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
285289
/* Set Lpi2c clock source. */
286290
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
287291
/* Disable CAN clock gate. */
@@ -305,7 +309,7 @@ void BOARD_ClockFullSpeed(void)
305309
/* Set UART_CLK_PODF. */
306310
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
307311
/* Set Uart clock source. */
308-
CLOCK_SetMux(kCLOCK_UartMux, 0);
312+
CLOCK_SetMux(kCLOCK_UartMux, 1);
309313
/* Disable LCDIF clock gate. */
310314
CLOCK_DisableClock(kCLOCK_LcdPixel);
311315
/* Set LCDIF_PRED. */
@@ -417,7 +421,7 @@ void BOARD_ClockFullSpeed(void)
417421
/* Set periph clock2 clock source. */
418422
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
419423
/* Set per clock source. */
420-
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
424+
CLOCK_SetMux(kCLOCK_PerclkMux, 1);
421425
/* Set lvds1 clock source. */
422426
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
423427
/* Set clock out1 divider. */
@@ -469,6 +473,7 @@ void BOARD_ClockFullSpeed(void)
469473
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
470474
!!Configuration
471475
name: BOARD_ClockOverdrive
476+
called_from_default_init: true
472477
outputs:
473478
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
474479
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
@@ -481,15 +486,15 @@ name: BOARD_ClockOverdrive
481486
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
482487
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
483488
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
484-
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
485-
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
489+
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
490+
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
486491
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
487492
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
488-
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
489-
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
493+
- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
494+
- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
490495
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
491496
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
492-
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
497+
- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
493498
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
494499
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
495500
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -504,18 +509,22 @@ name: BOARD_ClockOverdrive
504509
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
505510
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
506511
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
507-
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
512+
- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
508513
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
509514
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
510515
settings:
511516
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
512517
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
513518
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
514519
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
515-
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
516-
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
520+
- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
521+
- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
522+
- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
523+
- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
524+
- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
517525
- {id: CCM.SEMC_PODF.scale, value: '8'}
518526
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
527+
- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
519528
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
520529
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
521530
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@@ -615,7 +624,7 @@ void BOARD_ClockOverdrive(void)
615624
CLOCK_DisableClock(kCLOCK_Gpt2S);
616625
CLOCK_DisableClock(kCLOCK_Pit);
617626
/* Set PERCLK_PODF. */
618-
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
627+
CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
619628
/* Disable USDHC1 clock gate. */
620629
CLOCK_DisableClock(kCLOCK_Usdhc1);
621630
/* Set USDHC1_PODF. */
@@ -664,9 +673,9 @@ void BOARD_ClockOverdrive(void)
664673
CLOCK_DisableClock(kCLOCK_Lpspi3);
665674
CLOCK_DisableClock(kCLOCK_Lpspi4);
666675
/* Set LPSPI_PODF. */
667-
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
676+
CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
668677
/* Set Lpspi clock source. */
669-
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
678+
CLOCK_SetMux(kCLOCK_LpspiMux, 1);
670679
/* Disable TRACE clock gate. */
671680
CLOCK_DisableClock(kCLOCK_Trace);
672681
/* Set TRACE_PODF. */
@@ -702,7 +711,7 @@ void BOARD_ClockOverdrive(void)
702711
CLOCK_DisableClock(kCLOCK_Lpi2c2);
703712
CLOCK_DisableClock(kCLOCK_Lpi2c3);
704713
/* Set LPI2C_CLK_PODF. */
705-
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
714+
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
706715
/* Set Lpi2c clock source. */
707716
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
708717
/* Disable CAN clock gate. */
@@ -726,7 +735,7 @@ void BOARD_ClockOverdrive(void)
726735
/* Set UART_CLK_PODF. */
727736
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
728737
/* Set Uart clock source. */
729-
CLOCK_SetMux(kCLOCK_UartMux, 0);
738+
CLOCK_SetMux(kCLOCK_UartMux, 1);
730739
/* Disable LCDIF clock gate. */
731740
CLOCK_DisableClock(kCLOCK_LcdPixel);
732741
/* Set LCDIF_PRED. */
@@ -838,7 +847,7 @@ void BOARD_ClockOverdrive(void)
838847
/* Set periph clock2 clock source. */
839848
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
840849
/* Set per clock source. */
841-
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
850+
CLOCK_SetMux(kCLOCK_PerclkMux, 1);
842851
/* Set lvds1 clock source. */
843852
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
844853
/* Set clock out1 divider. */
@@ -902,15 +911,15 @@ description: Clocks the MIMRT using the lowest possible power settings (core run
902911
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
903912
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
904913
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz}
905-
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 12 MHz}
906-
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 12 MHz}
914+
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
915+
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
907916
- {id: IPG_CLK_ROOT.outFreq, value: 12 MHz}
908917
- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
909918
- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
910-
- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
919+
- {id: LPSPI_CLK_ROOT.outFreq, value: 3 MHz}
911920
- {id: LVDS1_CLK.outFreq, value: 24 MHz}
912921
- {id: MQS_MCLK.outFreq, value: 3 MHz}
913-
- {id: PERCLK_CLK_ROOT.outFreq, value: 12 MHz}
922+
- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
914923
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
915924
- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
916925
- {id: SAI1_MCLK1.outFreq, value: 3 MHz}
@@ -925,15 +934,19 @@ description: Clocks the MIMRT using the lowest possible power settings (core run
925934
- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
926935
- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
927936
- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
928-
- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
937+
- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
929938
- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
930939
- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
931940
settings:
932941
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
933942
- {id: CCM.IPG_PODF.scale, value: '2', locked: true}
943+
- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
944+
- {id: CCM.LPSPI_PODF.scale, value: '8', locked: true}
945+
- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
934946
- {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
935947
- {id: CCM.PERIPH_CLK_SEL.sel, value: CCM.PERIPH_CLK2_PODF}
936948
- {id: CCM.SEMC_PODF.scale, value: '1', locked: true}
949+
- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
937950
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
938951
- {id: CCM_ANALOG.PLL2.num, value: '0'}
939952
- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'}
@@ -1036,9 +1049,9 @@ void BOARD_ClockLowPower(void)
10361049
CLOCK_DisableClock(kCLOCK_Lpspi3);
10371050
CLOCK_DisableClock(kCLOCK_Lpspi4);
10381051
/* Set LPSPI_PODF. */
1039-
CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
1052+
CLOCK_SetDiv(kCLOCK_LpspiDiv, 7);
10401053
/* Set Lpspi clock source. */
1041-
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
1054+
CLOCK_SetMux(kCLOCK_LpspiMux, 1);
10421055
/* Disable TRACE clock gate. */
10431056
CLOCK_DisableClock(kCLOCK_Trace);
10441057
/* Set TRACE_PODF. */
@@ -1098,7 +1111,7 @@ void BOARD_ClockLowPower(void)
10981111
/* Set UART_CLK_PODF. */
10991112
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
11001113
/* Set Uart clock source. */
1101-
CLOCK_SetMux(kCLOCK_UartMux, 0);
1114+
CLOCK_SetMux(kCLOCK_UartMux, 1);
11021115
/* Disable LCDIF clock gate. */
11031116
CLOCK_DisableClock(kCLOCK_LcdPixel);
11041117
/* Set LCDIF_PRED. */
@@ -1206,7 +1219,7 @@ void BOARD_ClockLowPower(void)
12061219
/* Set periph clock source. */
12071220
CLOCK_SetMux(kCLOCK_PeriphMux, 1);
12081221
/* Set per clock source. */
1209-
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
1222+
CLOCK_SetMux(kCLOCK_PerclkMux, 1);
12101223
/* Set lvds1 clock source. */
12111224
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
12121225
/* Set clock out1 divider. */

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