From 7cf9f6929d0af6a69c7b07e672f14eb2f1686f1e Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 10 Jul 2024 16:26:59 +0200
Subject: [PATCH 01/57] Create lwip_max_tcp_pcb.diff
---
patches/lwip_max_tcp_pcb.diff | 118 ++++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 patches/lwip_max_tcp_pcb.diff
diff --git a/patches/lwip_max_tcp_pcb.diff b/patches/lwip_max_tcp_pcb.diff
new file mode 100644
index 000000000..6b9e73cb6
--- /dev/null
+++ b/patches/lwip_max_tcp_pcb.diff
@@ -0,0 +1,118 @@
+diff --git a/components/lwip/lwip/src/core/memp.c b/components/lwip/lwip/src/core/memp.c
+index 352ce5a55127a658b6b3c9d8541298c42df332ff..39433cf476b3456b046e337e9b1f016299964a84 100644
+--- a/components/lwip/lwip/src/core/memp.c
++++ b/components/lwip/lwip/src/core/memp.c
+@@ -240,6 +240,10 @@ memp_init(void)
+ #endif /* MEMP_OVERFLOW_CHECK >= 2 */
+ }
+
++#if MEMP_MEM_MALLOC && ESP_LWIP && LWIP_TCP
++static u32_t num_tcp_pcb = 0;
++#endif
++
+ static void *
+ #if !MEMP_OVERFLOW_CHECK
+ do_memp_malloc_pool(const struct memp_desc *desc)
+@@ -251,6 +255,16 @@ do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int
+ SYS_ARCH_DECL_PROTECT(old_level);
+
+ #if MEMP_MEM_MALLOC
++#if ESP_LWIP
++#if LWIP_TCP
++ if(desc == memp_pools[MEMP_TCP_PCB]){
++ if(num_tcp_pcb >= MEMP_NUM_TCP_PCB){
++ return NULL;
++ }
++ }
++#endif
++#endif
++
+ memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
+ SYS_ARCH_PROTECT(old_level);
+ #else /* MEMP_MEM_MALLOC */
+@@ -260,6 +274,12 @@ do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int
+ #endif /* MEMP_MEM_MALLOC */
+
+ if (memp != NULL) {
++#if MEMP_MEM_MALLOC && ESP_LWIP && LWIP_TCP
++ if (desc == memp_pools[MEMP_TCP_PCB]) {
++ num_tcp_pcb++;
++ }
++#endif
++
+ #if !MEMP_MEM_MALLOC
+ #if MEMP_OVERFLOW_CHECK == 1
+ memp_overflow_check_element(memp, desc);
+@@ -369,6 +389,12 @@ do_memp_free_pool(const struct memp_desc *desc, void *mem)
+
+ SYS_ARCH_PROTECT(old_level);
+
++#if MEMP_MEM_MALLOC && ESP_LWIP && LWIP_TCP
++ if (desc == memp_pools[MEMP_TCP_PCB]) {
++ num_tcp_pcb--;
++ }
++#endif
++
+ #if MEMP_OVERFLOW_CHECK == 1
+ memp_overflow_check_element(memp, desc);
+ #endif /* MEMP_OVERFLOW_CHECK */
+diff --git a/components/lwip/lwip/src/core/tcp.c b/components/lwip/lwip/src/core/tcp.c
+index 3fbdd89ae07807208ff7466abb50f90b5e7727e4..fe6baaf250927cb4b89f8d1dbd41c73def88692b 100644
+--- a/components/lwip/lwip/src/core/tcp.c
++++ b/components/lwip/lwip/src/core/tcp.c
+@@ -1765,7 +1765,9 @@ tcp_kill_state(enum tcp_state state)
+ struct tcp_pcb *pcb, *inactive;
+ u32_t inactivity;
+
++#if !ESP_LWIP
+ LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
++#endif
+
+ inactivity = 0;
+ inactive = NULL;
+@@ -1870,17 +1872,41 @@ tcp_alloc(u8_t prio)
+ tcp_kill_state(CLOSING);
+ /* Try to allocate a tcp_pcb again. */
+ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
++#if ESP_LWIP
+ if (pcb == NULL) {
+- /* Try killing oldest active connection with lower priority than the new one. */
+- LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
+- tcp_kill_prio(prio);
+- /* Try to allocate a tcp_pcb again. */
++ /* Try killing oldest connection in FIN_WAIT_2. */
++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest FIN_WAIT_2 connection\n"));
++ tcp_kill_state(FIN_WAIT_2);
+ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
++ if (pcb == NULL) {
++ /* Try killing oldest connection in FIN_WAIT_1. */
++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest FIN_WAIT_1 connection\n"));
++ tcp_kill_state(FIN_WAIT_1);
++ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
++#endif
++ if (pcb == NULL) {
++ /* Try killing oldest active connection with lower priority than the new one. */
++ LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
++ tcp_kill_prio(prio);
++ /* Try to allocate a tcp_pcb again. */
++ pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
++ if (pcb != NULL) {
++ /* adjust err stats: memp_malloc failed multiple times before */
++ MEMP_STATS_DEC(err, MEMP_TCP_PCB);
++ }
++ }
++#if ESP_LWIP
++ if (pcb != NULL) {
++ /* adjust err stats: memp_malloc failed multiple times before */
++ MEMP_STATS_DEC(err, MEMP_TCP_PCB);
++ }
++ }
+ if (pcb != NULL) {
+ /* adjust err stats: memp_malloc failed multiple times before */
+ MEMP_STATS_DEC(err, MEMP_TCP_PCB);
+ }
+ }
++#endif
+ if (pcb != NULL) {
+ /* adjust err stats: memp_malloc failed multiple times before */
+ MEMP_STATS_DEC(err, MEMP_TCP_PCB);
From 24cf1c77013bd666bbf2a37198c1b5fe70920594 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 10 Jul 2024 16:31:31 +0200
Subject: [PATCH 02/57] Update install-esp-idf.sh
---
tools/install-esp-idf.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/install-esp-idf.sh b/tools/install-esp-idf.sh
index 68cfe6db2..3b43b2b7a 100755
--- a/tools/install-esp-idf.sh
+++ b/tools/install-esp-idf.sh
@@ -69,6 +69,7 @@ if [ ! -x $idf_was_installed ] || [ ! -x $commit_predefined ]; then
cd $IDF_PATH
patch -p1 -N -i ../patches/esp32s2_i2c_ll_master_init.diff
patch -p1 -N -i ../patches/mmu_map.diff
+ patch -p1 -N -i ../patches/lwip_max_tcp_pcb.diff
cd -
# Get the exact IDF version from file "version.txt"
From f0e596d8060787b10f12b04b2d2e276e2190878c Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Fri, 12 Jul 2024 19:40:55 +0200
Subject: [PATCH 03/57] Fix i2s audio
* enable `CONFIG_I2S_ISR_IRAM_SAFE`
---
configs/defconfig.common | 1 +
configs/defconfig.opi_ram | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index 93eedc4b2..48b9352f6 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -11,6 +11,7 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_OFF=y
CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS=y
CONFIG_ARDUHAL_LOG_DEFAULT_LEVEL_NONE=y
CONFIG_I2S_SUPPRESS_DEPRECATE_WARN=y
+CONFIG_I2S_ISR_IRAM_SAFE=y
CONFIG_RMT_SUPPRESS_DEPRECATE_WARN=y
CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
diff --git a/configs/defconfig.opi_ram b/configs/defconfig.opi_ram
index e6df61d08..7b94edaf9 100644
--- a/configs/defconfig.opi_ram
+++ b/configs/defconfig.opi_ram
@@ -4,6 +4,7 @@ CONFIG_SPIRAM_IGNORE_NOTFOUND=y
CONFIG_LCD_RGB_ISR_IRAM_SAFE=y
CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
# bounce buffer mode relies on GDMA EOF interrupt to be service-able
+# I2S_ISR_IRAM_SAFE has to be set!! Done in common config
CONFIG_GDMA_ISR_IRAM_SAFE=y
# Enable the XIP-PSRAM feature, so the ext-mem cache won't be disabled when SPI1 is operating the main flash
CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
From dd17fc6077f49fc354126966b935722d1d692861 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 13 Jul 2024 21:13:32 +0200
Subject: [PATCH 04/57] Update defconfig.esp32
---
configs/defconfig.esp32 | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/configs/defconfig.esp32 b/configs/defconfig.esp32
index 9ceab04e5..92f4dbe4e 100644
--- a/configs/defconfig.esp32
+++ b/configs/defconfig.esp32
@@ -19,6 +19,11 @@ CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1
CONFIG_BT_STACK_NO_LOG=y
CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY=y
+# Enable ULP
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_FSM=y
+CONFIG_ULP_COPROC_RESERVE_MEM=4096
+
CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR=y
CONFIG_ETH_ENABLED=y
From 3db5a6e9965e3589a712d603a3ca9675ad92b226 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Fri, 19 Jul 2024 18:10:34 +0200
Subject: [PATCH 05/57] # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
---
configs/defconfig.common | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index 48b9352f6..e76d17ac6 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -38,6 +38,7 @@ CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y
# CONFIG_ESP_WIFI_FTM_ENABLE is not set
+# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=8
CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=8
CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=16
From 58837ae8e7676ec4b10a75a391523f72fff8e584 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 23 Jul 2024 13:00:37 +0200
Subject: [PATCH 06/57] made scripts executable
---
tools/config_editor/compile.py | 0
tools/config_editor/editor.py | 0
tools/config_editor/settings.py | 0
tools/config_editor/widgets.py | 0
tools/gen_pio_frmwk_manifest.py | 0
tools/gen_pio_lib_manifest.py | 0
tools/get_projbuild_gitconfig.py | 0
7 files changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 tools/config_editor/compile.py
mode change 100644 => 100755 tools/config_editor/editor.py
mode change 100644 => 100755 tools/config_editor/settings.py
mode change 100644 => 100755 tools/config_editor/widgets.py
mode change 100644 => 100755 tools/gen_pio_frmwk_manifest.py
mode change 100644 => 100755 tools/gen_pio_lib_manifest.py
mode change 100644 => 100755 tools/get_projbuild_gitconfig.py
diff --git a/tools/config_editor/compile.py b/tools/config_editor/compile.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/editor.py b/tools/config_editor/editor.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/settings.py b/tools/config_editor/settings.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/widgets.py b/tools/config_editor/widgets.py
old mode 100644
new mode 100755
diff --git a/tools/gen_pio_frmwk_manifest.py b/tools/gen_pio_frmwk_manifest.py
old mode 100644
new mode 100755
diff --git a/tools/gen_pio_lib_manifest.py b/tools/gen_pio_lib_manifest.py
old mode 100644
new mode 100755
diff --git a/tools/get_projbuild_gitconfig.py b/tools/get_projbuild_gitconfig.py
old mode 100644
new mode 100755
From 86374575de91636b3105689b5a21f244ddb20fb3 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 23 Jul 2024 13:01:13 +0200
Subject: [PATCH 07/57] made executable
---
tools/config_editor/compile.py | 0
tools/config_editor/editor.py | 0
tools/config_editor/settings.py | 0
tools/config_editor/widgets.py | 0
tools/gen_pio_frmwk_manifest.py | 0
tools/gen_pio_lib_manifest.py | 0
tools/get_projbuild_gitconfig.py | 0
7 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 tools/config_editor/compile.py
mode change 100755 => 100644 tools/config_editor/editor.py
mode change 100755 => 100644 tools/config_editor/settings.py
mode change 100755 => 100644 tools/config_editor/widgets.py
mode change 100755 => 100644 tools/gen_pio_frmwk_manifest.py
mode change 100755 => 100644 tools/gen_pio_lib_manifest.py
mode change 100755 => 100644 tools/get_projbuild_gitconfig.py
diff --git a/tools/config_editor/compile.py b/tools/config_editor/compile.py
old mode 100755
new mode 100644
diff --git a/tools/config_editor/editor.py b/tools/config_editor/editor.py
old mode 100755
new mode 100644
diff --git a/tools/config_editor/settings.py b/tools/config_editor/settings.py
old mode 100755
new mode 100644
diff --git a/tools/config_editor/widgets.py b/tools/config_editor/widgets.py
old mode 100755
new mode 100644
diff --git a/tools/gen_pio_frmwk_manifest.py b/tools/gen_pio_frmwk_manifest.py
old mode 100755
new mode 100644
diff --git a/tools/gen_pio_lib_manifest.py b/tools/gen_pio_lib_manifest.py
old mode 100755
new mode 100644
diff --git a/tools/get_projbuild_gitconfig.py b/tools/get_projbuild_gitconfig.py
old mode 100755
new mode 100644
From 6a4f22be9384c76d625ee3b8b724dfd3bd4d9463 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 23 Jul 2024 13:11:33 +0200
Subject: [PATCH 08/57] make files executable
---
tools/config_editor/compile.py | 0
tools/config_editor/editor.py | 0
tools/config_editor/settings.py | 0
tools/config_editor/widgets.py | 0
tools/gen_pio_frmwk_manifest.py | 0
tools/gen_pio_lib_manifest.py | 0
tools/get_projbuild_gitconfig.py | 0
7 files changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 tools/config_editor/compile.py
mode change 100644 => 100755 tools/config_editor/editor.py
mode change 100644 => 100755 tools/config_editor/settings.py
mode change 100644 => 100755 tools/config_editor/widgets.py
mode change 100644 => 100755 tools/gen_pio_frmwk_manifest.py
mode change 100644 => 100755 tools/gen_pio_lib_manifest.py
mode change 100644 => 100755 tools/get_projbuild_gitconfig.py
diff --git a/tools/config_editor/compile.py b/tools/config_editor/compile.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/editor.py b/tools/config_editor/editor.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/settings.py b/tools/config_editor/settings.py
old mode 100644
new mode 100755
diff --git a/tools/config_editor/widgets.py b/tools/config_editor/widgets.py
old mode 100644
new mode 100755
diff --git a/tools/gen_pio_frmwk_manifest.py b/tools/gen_pio_frmwk_manifest.py
old mode 100644
new mode 100755
diff --git a/tools/gen_pio_lib_manifest.py b/tools/gen_pio_lib_manifest.py
old mode 100644
new mode 100755
diff --git a/tools/get_projbuild_gitconfig.py b/tools/get_projbuild_gitconfig.py
old mode 100644
new mode 100755
From c03ce779c2e61ca5058c50b9cd82c9dc720a92b8 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 31 Jul 2024 13:36:09 +0200
Subject: [PATCH 09/57] Update install-esp-idf.sh
---
tools/install-esp-idf.sh | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/install-esp-idf.sh b/tools/install-esp-idf.sh
index 3b43b2b7a..0994c09b7 100755
--- a/tools/install-esp-idf.sh
+++ b/tools/install-esp-idf.sh
@@ -67,9 +67,9 @@ if [ ! -x $idf_was_installed ] || [ ! -x $commit_predefined ]; then
# 1) Temporarily patch the ESP32-S2 I2C LL driver to keep the clock source
# 2) Temporarily fix for mmu map and late init of psram https://github.com/espressif/arduino-esp32/issues/9936
cd $IDF_PATH
- patch -p1 -N -i ../patches/esp32s2_i2c_ll_master_init.diff
- patch -p1 -N -i ../patches/mmu_map.diff
- patch -p1 -N -i ../patches/lwip_max_tcp_pcb.diff
+ patch -p1 -N -i $AR_PATCHES/esp32s2_i2c_ll_master_init.diff
+ patch -p1 -N -i $AR_PATCHES/mmu_map.diff
+ patch -p1 -N -i $AR_PATCHES/lwip_max_tcp_pcb.diff
cd -
# Get the exact IDF version from file "version.txt"
From c953dceae7a3b5209aecf598ef8697a8ab836398 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 31 Jul 2024 13:37:09 +0200
Subject: [PATCH 10/57] Update config.sh
---
tools/config.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/config.sh b/tools/config.sh
index a5cdfe840..26c934cc6 100755
--- a/tools/config.sh
+++ b/tools/config.sh
@@ -52,6 +52,7 @@ AR_COMPS="$AR_ROOT/components"
AR_MANAGED_COMPS="$AR_ROOT/managed_components"
AR_OUT="$AR_ROOT/out"
AR_TOOLS="$AR_OUT/tools"
+AR_PATCHES="$AR_ROOT/patches"
AR_PLATFORM_TXT="$AR_OUT/platform.txt"
AR_GEN_PART_PY="$AR_TOOLS/gen_esp32part.py"
AR_SDK="$AR_TOOLS/esp32-arduino-libs/$IDF_TARGET"
From 82209576fc6d29af4f8f8577f55b2d144c18660e Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 10 Aug 2024 18:00:06 +0200
Subject: [PATCH 11/57] Update build.sh
---
build.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/build.sh b/build.sh
index cef559e19..a48f55fe0 100755
--- a/build.sh
+++ b/build.sh
@@ -100,6 +100,9 @@ else
source ./tools/config.sh
fi
+# avoid compile stop when files of managed components have been changed
+rm -rf $AR_MANAGED_COMPS/.component_hash
+
if [ "$BUILD_TYPE" != "all" ]; then
if [ "$TARGET" = "all" ]; then
echo "ERROR: You need to specify target for non-default builds"
From 959d6c2acbd55906476f4b1b5fbd84f1b1d268eb Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 10 Aug 2024 19:15:12 +0200
Subject: [PATCH 12/57] fix compile stop caused by component hash
---
build.sh | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/build.sh b/build.sh
index a48f55fe0..e25cf8eed 100755
--- a/build.sh
+++ b/build.sh
@@ -100,9 +100,6 @@ else
source ./tools/config.sh
fi
-# avoid compile stop when files of managed components have been changed
-rm -rf $AR_MANAGED_COMPS/.component_hash
-
if [ "$BUILD_TYPE" != "all" ]; then
if [ "$TARGET" = "all" ]; then
echo "ERROR: You need to specify target for non-default builds"
@@ -204,6 +201,9 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build IDF-Libs: $idf_libs_configs"
rm -rf build sdkconfig
+ pushd $AR_MANAGED_COMPS
+ rm -- **/.component_hash
+ popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$idf_libs_configs" idf-libs
if [ $? -ne 0 ]; then exit 1; fi
@@ -216,6 +216,9 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build BootLoader: $bootloader_configs"
rm -rf build sdkconfig
+ pushd $AR_MANAGED_COMPS
+ rm -- **/.component_hash
+ popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$bootloader_configs" copy-bootloader
if [ $? -ne 0 ]; then exit 1; fi
done
@@ -229,6 +232,9 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build Memory Variant: $mem_configs"
rm -rf build sdkconfig
+ pushd $AR_MANAGED_COMPS
+ rm -- **/.component_hash
+ popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$mem_configs" mem-variant
if [ $? -ne 0 ]; then exit 1; fi
done
From e135e662470c8089a5d573911be3b5a3a13a6aea Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Thu, 15 Aug 2024 21:06:05 +0200
Subject: [PATCH 13/57] Update pio_start.txt
---
configs/pio_start.txt | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/configs/pio_start.txt b/configs/pio_start.txt
index 616cacbd9..078f0b085 100644
--- a/configs/pio_start.txt
+++ b/configs/pio_start.txt
@@ -35,4 +35,39 @@ FRAMEWORK_SDK_DIR = join(FRAMEWORK_DIR, "tools", "esp32-arduino-libs")
board_config = env.BoardConfig()
+flatten_cppdefines = env.Flatten(env['CPPDEFINES'])
+
+#
+# zigbee libs
+#
+if "ZIGBEE_MODE_ZCZR" in flatten_cppdefines:
+ env.Append(
+ LIBS=[
+ "-lesp_zb_api_zczr",
+ "-lesp_zb_cli_command",
+ "-lzboss_stack.zczr.trace",
+ "-lzboss_stack.zczr",
+ "-lzboss_port"
+ ]
+ )
+if "ZIGBEE_MODE_ED" in flatten_cppdefines:
+ env.Append(
+ LIBS=[
+ "-lesp_zb_api_ed",
+ "-lesp_zb_cli_command",
+ "-lzboss_stack.ed.trace",
+ "-lzboss_stack.ed",
+ "-lzboss_port"
+ ]
+ )
+if "ZIGBEE_MODE_RCP" in flatten_cppdefines:
+ env.Append(
+ LIBS=[
+ "-lesp_zb_api_rcp",
+ "-lesp_zb_cli_command",
+ "-lzboss_stack.rcp",
+ "-lzboss_port"
+ ]
+ )
+
env.Append(
From 5446b61f882fed161ed3a6b34a2d544882b968d9 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Thu, 15 Aug 2024 22:29:02 +0200
Subject: [PATCH 14/57] Update build.sh
---
build.sh | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/build.sh b/build.sh
index e25cf8eed..df0c49eb8 100755
--- a/build.sh
+++ b/build.sh
@@ -10,6 +10,9 @@ if ! [ -x "$(command -v git)" ]; then
exit 1
fi
+# Fixes building some components. See https://github.com/espressif/arduino-esp32/issues/10167
+export IDF_COMPONENT_OVERWRITE_MANAGED_COMPONENTS=1
+
export TARGET="all"
BUILD_TYPE="all"
SKIP_ENV=0
@@ -201,9 +204,6 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build IDF-Libs: $idf_libs_configs"
rm -rf build sdkconfig
- pushd $AR_MANAGED_COMPS
- rm -- **/.component_hash
- popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$idf_libs_configs" idf-libs
if [ $? -ne 0 ]; then exit 1; fi
@@ -216,9 +216,6 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build BootLoader: $bootloader_configs"
rm -rf build sdkconfig
- pushd $AR_MANAGED_COMPS
- rm -- **/.component_hash
- popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$bootloader_configs" copy-bootloader
if [ $? -ne 0 ]; then exit 1; fi
done
@@ -232,9 +229,6 @@ for target_json in `jq -c '.targets[]' configs/builds.json`; do
echo "* Build Memory Variant: $mem_configs"
rm -rf build sdkconfig
- pushd $AR_MANAGED_COMPS
- rm -- **/.component_hash
- popd
idf.py -DIDF_TARGET="$target" -DSDKCONFIG_DEFAULTS="$mem_configs" mem-variant
if [ $? -ne 0 ]; then exit 1; fi
done
From 543522b863de2d97a1e928038ebfcb6246e890b3 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 19 Aug 2024 20:10:37 +0200
Subject: [PATCH 15/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index d9d15d4c6..adf018fe8 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -226,7 +226,6 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
} else {
fifo_num = get_free_fifo();
}
- TU_ASSERT(fifo_num != 0);
#endif
dwc2->epin[epnum].diepctl = dxepctl | (fifo_num << DIEPCTL_TXFNUM_Pos);
dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
From ac25b12bde31b8e21c0cf235032e8547c56add8f Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 21 Aug 2024 10:58:21 +0200
Subject: [PATCH 16/57] Update tusb_config.h
---
components/arduino_tinyusb/include/tusb_config.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h
index ee1e5d270..f4acaa232 100755
--- a/components/arduino_tinyusb/include/tusb_config.h
+++ b/components/arduino_tinyusb/include/tusb_config.h
@@ -75,8 +75,9 @@ extern "C" {
/* */
/* COMMON CONFIGURATION */
/* */
-
+#ifndef CFG_TUSB_MCU
#define CFG_TUSB_MCU OPT_MCU_ESP32S2
+#endif
#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE
#define CFG_TUSB_OS OPT_OS_FREERTOS
From 4700482e23b36709b038df9e9595d8e5897eef59 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 24 Aug 2024 11:46:53 +0200
Subject: [PATCH 17/57] Update CMakeLists.txt
---
components/arduino_tinyusb/CMakeLists.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/components/arduino_tinyusb/CMakeLists.txt b/components/arduino_tinyusb/CMakeLists.txt
index 792b2a39f..b0227ec5a 100755
--- a/components/arduino_tinyusb/CMakeLists.txt
+++ b/components/arduino_tinyusb/CMakeLists.txt
@@ -19,8 +19,8 @@ if(CONFIG_TINYUSB_ENABLED)
set(srcs
# espressif:
- "${COMPONENT_DIR}/src/dcd_esp32sx.c"
- #"${COMPONENT_DIR}/src/dcd_dwc2.c"
+ #"${COMPONENT_DIR}/src/dcd_esp32sx.c"
+ "${COMPONENT_DIR}/src/dcd_dwc2.c"
# tusb:
#"${COMPONENT_DIR}/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c"
#"{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c"
From ce1721b4456b90a3c79fb8d559fa030cab7bb264 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 28 Aug 2024 21:46:11 +0200
Subject: [PATCH 18/57] remove not existing zigbee libs
---
configs/pio_start.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/configs/pio_start.txt b/configs/pio_start.txt
index 078f0b085..0f2fe3d8b 100644
--- a/configs/pio_start.txt
+++ b/configs/pio_start.txt
@@ -45,7 +45,6 @@ if "ZIGBEE_MODE_ZCZR" in flatten_cppdefines:
LIBS=[
"-lesp_zb_api_zczr",
"-lesp_zb_cli_command",
- "-lzboss_stack.zczr.trace",
"-lzboss_stack.zczr",
"-lzboss_port"
]
@@ -55,7 +54,6 @@ if "ZIGBEE_MODE_ED" in flatten_cppdefines:
LIBS=[
"-lesp_zb_api_ed",
"-lesp_zb_cli_command",
- "-lzboss_stack.ed.trace",
"-lzboss_stack.ed",
"-lzboss_port"
]
From df66ca852e2166062109a0754e10ab8398202503 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Fri, 30 Aug 2024 17:33:51 +0200
Subject: [PATCH 19/57] Update build.sh
---
build.sh | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/build.sh b/build.sh
index df0c49eb8..e96fc314b 100755
--- a/build.sh
+++ b/build.sh
@@ -1,18 +1,25 @@
#!/bin/bash
if ! [ -x "$(command -v python3)" ]; then
- echo "ERROR: python is not installed! Please install python first."
+ echo "ERROR: python is not installed or not in PATH! Please install python first."
exit 1
fi
if ! [ -x "$(command -v git)" ]; then
- echo "ERROR: git is not installed! Please install git first."
+ echo "ERROR: git is not installed or not in PATH! Please install git first."
+ exit 1
+fi
+
+if ! [ -x "$(command -v ninja)" ]; then
+ echo "ERROR: ninja is not installed or not in PATH! Please install ninja first."
exit 1
fi
# Fixes building some components. See https://github.com/espressif/arduino-esp32/issues/10167
export IDF_COMPONENT_OVERWRITE_MANAGED_COMPONENTS=1
+CCACHE_ENABLE=1
+
export TARGET="all"
BUILD_TYPE="all"
SKIP_ENV=0
@@ -21,8 +28,9 @@ ARCHIVE_OUT=1
DEPLOY_OUT=0
function print_help() {
- echo "Usage: build.sh [-s] [-A <arduino_branch>] [-I <idf_branch>] [-i <idf_commit>] [-c <path>] [-t <target>] [-b <build|menuconfig|reconfigure|idf-libs|copy-bootloader|mem-variant>] [config ...]"
+ echo "Usage: build.sh [-s] [-n] [-A <arduino_branch>] [-I <idf_branch>] [-i <idf_commit>] [-c <path>] [-t <target>] [-b <build|menuconfig|reconfigure|idf-libs|copy-bootloader|mem-variant>] [config ...]"
echo " -s Skip installing/updating of ESP-IDF and all components"
+ echo " -n Disable ccache"
echo " -A Set which branch of arduino-esp32 to be used for compilation"
echo " -I Set which branch of ESP-IDF to be used for compilation"
echo " -i Set which commit of ESP-IDF to be used for compilation"
@@ -38,6 +46,9 @@ while getopts ":A:I:i:c:t:b:sde" opt; do
s )
SKIP_ENV=1
;;
+ n )
+ CCACHE_ENABLE=0
+ ;;
e )
ARCHIVE_OUT=1
;;
@@ -78,6 +89,8 @@ done
shift $((OPTIND -1))
CONFIGS=$@
+export IDF_CCACHE_ENABLE=$CCACHE_ENABLE
+
# Output the TARGET array
echo "TARGET(s): ${TARGET[@]}"
From eca7e005969583df0a3c4244f22830a1e37dda6b Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 12:26:02 +0200
Subject: [PATCH 20/57] Update app.py
---
tools/config_editor/app.py | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/config_editor/app.py b/tools/config_editor/app.py
index 02ae85d2c..37e2f0e57 100755
--- a/tools/config_editor/app.py
+++ b/tools/config_editor/app.py
@@ -109,10 +109,10 @@ class ConfigEditorApp(App):
ENABLE_COMMAND_PALETTE = False
CSS_PATH = "style.tcss"
SCREENS = {
- "main": MainScreen(),
- "settings": SettingsScreen(),
- "compile": CompileScreen(),
- "editor": EditorScreen(),
+ "main": MainScreen,
+ "settings": SettingsScreen,
+ "compile": CompileScreen,
+ "editor": EditorScreen,
}
def on_mount(self) -> None:
From 9e5ba1c3c5c2516361896c3c1730e69af1348b13 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 12:27:29 +0200
Subject: [PATCH 21/57] Create requirements.txt
---
tools/config_editor/requirements.txt | 1 +
1 file changed, 1 insertion(+)
create mode 100644 tools/config_editor/requirements.txt
diff --git a/tools/config_editor/requirements.txt b/tools/config_editor/requirements.txt
new file mode 100644
index 000000000..f3cac7be0
--- /dev/null
+++ b/tools/config_editor/requirements.txt
@@ -0,0 +1 @@
+textual==0.79.0
From b41cf0bb4b16418f131801b0e99c481bdbee7578 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 12:28:42 +0200
Subject: [PATCH 22/57] Update README.md
---
tools/config_editor/README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/config_editor/README.md b/tools/config_editor/README.md
index 0ca0aaf0a..51d55ee4a 100644
--- a/tools/config_editor/README.md
+++ b/tools/config_editor/README.md
@@ -6,7 +6,7 @@ It has mouse support and can be pre-configured using command line arguments.
## Requirements
- Python 3.9 or later
- - The "textual" library (install it using `pip install textual`)
+ - Install the required packages using `pip install -r requirements.txt`
- The requirements from esp32-arduino-lib-builder
## Troubleshooting
From c7848c03e26d0f38e79e827b97d515a2f6d124cc Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 12:31:02 +0200
Subject: [PATCH 23/57] Update README.md
---
README.md | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/README.md b/README.md
index fe1a47534..add853d0e 100644
--- a/README.md
+++ b/README.md
@@ -2,17 +2,17 @@
This repository contains the scripts that produce the libraries included with Tasmota esp32-arduino.
-### Build on Ubuntu
+Tested on Ubuntu (32 and 64 bit), Raspberry Pi and MacOS.
+
+### Build on Ubuntu and Raspberry Pi
```bash
-sudo apt update && sudo apt install -y git wget curl libssl-dev libncurses-dev flex bison gperf python3 cmake ninja-build ccache jq
-curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py && python3 get-pip.py && \
-pip3 install setuptools pyserial click future wheel cryptography pyparsing pyelftools
-git clone https://github.com/Jason2866/esp32-arduino-lib-builder
+sudo apt-get install git wget curl libssl-dev libncurses-dev flex bison gperf python python-pip python-setuptools python-serial python-click python-cryptography python-future python-pyparsing python-pyelftools cmake ninja-build ccache jq
+sudo pip install --upgrade pip
+git clone https://github.com/espressif/esp32-arduino-lib-builder
cd esp32-arduino-lib-builder
./build.sh
```
-
### Using the User Interface
You can more easily build the libraries using the user interface found in the `tools/config_editor/` folder.
@@ -22,25 +22,23 @@ For more information and troubleshooting, please refer to the [UI README](tools/
To use it, follow these steps:
-1. Make sure you have the required dependencies installed:
+1. Make sure you have the following prerequisites:
- Python 3.9 or later
- - The [Textual](https://github.com/textualize/textual/) library
- All the dependencies listed in the previous section
-2. Execute the script `tools/config_editor/app.py` from any folder. It will automatically detect the path to the root of the repository.
+2. Install the required UI packages using `pip install -r tools/config_editor/requirements.txt`.
-3. Configure the compilation and ESP-IDF options as desired.
+3. Execute the script `tools/config_editor/app.py` from any folder. It will automatically detect the path to the root of the repository.
-4. Click on the "Compile Static Libraries" button to start the compilation process.
+4. Configure the compilation and ESP-IDF options as desired.
-5. The script will show the compilation output in a new screen. Note that the compilation process can take many hours, depending on the number of libraries selected and the options chosen.
+5. Click on the "Compile Static Libraries" button to start the compilation process.
-6. If the compilation is successful you can find the Platformio framework in the `dist` folder alongside this repository.
+6. The script will show the compilation output in a new screen. Note that the compilation process can take many hours, depending on the number of libraries selected and the options chosen.
+7. If the compilation is successful and the option to copy the libraries to the Arduino Core folder is enabled, it will already be available for use in the Arduino IDE. Otherwise, you can find the compiled libraries in the `esp32-arduino-libs` folder alongside this repository.
+ - Note that the copy operation doesn't currently support the core downloaded from the Arduino IDE Boards Manager, only the manual installation from the [`arduino-esp32`](https://github.com/espressif/arduino-esp32) repository.
### Documentation
For more information about how to use the Library builder, please refer to this [Documentation page](https://docs.espressif.com/projects/arduino-esp32/en/latest/lib_builder.html?highlight=lib%20builder)
-
-### Development builds
-Look in release and download a version. There is the Info of the used commits of IDF / Arduino.
From a26898f0ef0df04bbe5f39eb63d7412f115f2388 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 12:31:49 +0200
Subject: [PATCH 24/57] Update README.md
---
README.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/README.md b/README.md
index add853d0e..7535475f0 100644
--- a/README.md
+++ b/README.md
@@ -2,9 +2,9 @@
This repository contains the scripts that produce the libraries included with Tasmota esp32-arduino.
-Tested on Ubuntu (32 and 64 bit), Raspberry Pi and MacOS.
+Tested on Ubuntu and MacOS.
-### Build on Ubuntu and Raspberry Pi
+### Build on Ubuntu
```bash
sudo apt-get install git wget curl libssl-dev libncurses-dev flex bison gperf python python-pip python-setuptools python-serial python-click python-cryptography python-future python-pyparsing python-pyelftools cmake ninja-build ccache jq
sudo pip install --upgrade pip
From 5acd5d473cb6ad3e591a09815d6f7851815a314d Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 31 Aug 2024 15:50:01 +0200
Subject: [PATCH 25/57] Update pio_end.txt
---
configs/pio_end.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/pio_end.txt b/configs/pio_end.txt
index e7544f1dd..f942d442d 100644
--- a/configs/pio_end.txt
+++ b/configs/pio_end.txt
@@ -1,5 +1,5 @@
"ARDUINO_ARCH_ESP32",
- "ESP32",
+ ("ESP32", "ESP32"),
("F_CPU", "$BOARD_F_CPU"),
("ARDUINO", 10812),
("ARDUINO_VARIANT", '\\"%s\\"' % board_config.get("build.variant").replace('"', "")),
From 61be840882eab37a20d711d02a3af14ba063f534 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 9 Sep 2024 12:11:02 +0200
Subject: [PATCH 26/57] Update defconfig.common
---
configs/defconfig.common | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index e76d17ac6..c6ef4ea89 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -37,22 +37,22 @@ CONFIG_ESP_TASK_WDT_PANIC=y
CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y
+# CONFIG_ESP_WIFI_MBEDTLS_CRYPTO is not set
# CONFIG_ESP_WIFI_FTM_ENABLE is not set
# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
-CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=8
-CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=8
-CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=16
# CONFIG_ESP_WIFI_CSI_ENABLED is not set
-CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
-CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+# CONFIG_ESP_WIFI_ENABLE_WPA3_SAE is not set
+# CONFIG_ESP_WIFI_ENABLE_SAE_PK is not set
# CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT is not set
CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
# CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT is not set
# CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA is not set
CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=0
-# CONFIG_ESP_WIFI_MBEDTLS_CRYPTO is not set
# CONFIG_ESP_WIFI_IRAM_OPT is not set
# CONFIG_ESP_WIFI_RX_IRAM_OPT is not set
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=8
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=8
+CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=16
CONFIG_ESP_PHY_REDUCE_TX_POWER=y
CONFIG_ETH_TRANSMIT_MUTEX=y
CONFIG_ETH_SPI_ETHERNET_DM9051=y
@@ -108,6 +108,7 @@ CONFIG_NEWLIB_NANO_FORMAT=y
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y
CONFIG_MBEDTLS_TLS_DISABLED=y
+# CONFIG_MBEDTLS_TLS_ENABLED is not set
# CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN is not set
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=10
# CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE is not set
@@ -171,7 +172,7 @@ CONFIG_MBEDTLS_HARDWARE_SHA=y
CONFIG_MBEDTLS_ECP_C=y
CONFIG_MBEDTLS_ECDH_C=y
CONFIG_MBEDTLS_ECDSA_C=y
-CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
+CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLE=y
# CONFIG_MBEDTLS_DHM_C is not set
# CONFIG_MBEDTLS_ECJPAKE_C is not set
# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set
From 26ec6e727f81ea4cbb1ad6afb062f4bcbf6d6932 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 9 Sep 2024 12:22:55 +0200
Subject: [PATCH 27/57] Update defconfig.common
---
configs/defconfig.common | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index c6ef4ea89..b53ad4ba8 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -172,7 +172,7 @@ CONFIG_MBEDTLS_HARDWARE_SHA=y
CONFIG_MBEDTLS_ECP_C=y
CONFIG_MBEDTLS_ECDH_C=y
CONFIG_MBEDTLS_ECDSA_C=y
-CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLE=y
+CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
# CONFIG_MBEDTLS_DHM_C is not set
# CONFIG_MBEDTLS_ECJPAKE_C is not set
# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set
From aef1f3705c9fc46dcb2a3325541e0c997f9e773b Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 10 Sep 2024 15:57:24 +0200
Subject: [PATCH 28/57] Update defconfig.common
---
configs/defconfig.common | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index b53ad4ba8..8daa1e5f2 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -44,7 +44,7 @@ CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y
# CONFIG_ESP_WIFI_ENABLE_WPA3_SAE is not set
# CONFIG_ESP_WIFI_ENABLE_SAE_PK is not set
# CONFIG_ESP_WIFI_ENTERPRISE_SUPPORT is not set
-CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT is not set
# CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT is not set
# CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA is not set
CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=0
From 8a404f1cb960bf8902af2ef572ba1d85f346f7f6 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sun, 22 Sep 2024 16:04:14 +0200
Subject: [PATCH 29/57] Update defconfig.common
---
configs/defconfig.common | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index 8daa1e5f2..5fc910b8a 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -16,6 +16,10 @@ CONFIG_RMT_SUPPRESS_DEPRECATE_WARN=y
CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_COMPILER_DISABLE_DEFAULT_ERRORS=y
+CONFIG_COMPILER_DISABLE_GCC12_WARNINGS=y
+CONFIG_COMPILER_DISABLE_GCC13_WARNINGS=y
+CONFIG_COMPILER_DISABLE_GCC14_WARNINGS=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y
CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
From cb258fb5c2d8f14e598120ed4f5a69c7ed06deff Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Fri, 27 Sep 2024 13:20:52 +0200
Subject: [PATCH 30/57] Fix remove Arduino defines
---
tools/copy-libs.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/copy-libs.sh b/tools/copy-libs.sh
index 88c1b5400..896effc0e 100755
--- a/tools/copy-libs.sh
+++ b/tools/copy-libs.sh
@@ -102,7 +102,7 @@ for item in "${@:2:${#@}-5}"; do
INCLUDES+="$item "
fi
elif [ "$prefix" = "-D" ]; then
- if [[ "${item:2:7}" != "ARDUINO" ]] && [[ "$item" != "-DESP32" ]]; then #skip ARDUINO defines
+ if [[ "${item:2:7}" != "ARDUINO" ]] && [[ "$item" != "-DESP32=ESP32" ]]; then #skip ARDUINO defines
DEFINES+="$item "
fi
elif [ "$prefix" = "-O" ]; then
From b889eada4b81376d806baba348cea692ee2c0424 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 13:35:47 +0200
Subject: [PATCH 31/57] Update CMakeLists.txt
---
CMakeLists.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 88cede199..bbf8583cb 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -33,3 +33,5 @@ add_custom_command(
VERBATIM
)
add_custom_target(mem-variant DEPENDS "mem_variant")
+
+idf_build_set_property(COMPILE_DEFINITIONS "-DESP32_ARDUINO_LIB_BUILDER" APPEND)
From 252048915dbadbc7ca50bb0d348ee7d282806c82 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 15:15:21 +0200
Subject: [PATCH 32/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 869 ++++++++++++----------
1 file changed, 474 insertions(+), 395 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index adf018fe8..e76bdf70e 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -31,6 +31,9 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
+// Debug level for DWC2
+#define DWC2_DEBUG 2
+
#include "device/dcd.h"
#include "dwc2_type.h"
@@ -43,7 +46,7 @@
#if defined(TUP_USBIP_DWC2_STM32)
#include "dwc2_stm32.h"
-#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#elif defined(TUP_USBIP_DWC2_ESP32)
#include "dwc2_esp32.h"
#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
#include "dwc2_gd32.h"
@@ -57,29 +60,26 @@
#error "Unsupported MCUs"
#endif
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+enum {
+ DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
+};
// DWC2 registers
-#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-
-// Debug level for DWC2
-#define DWC2_DEBUG 2
-
-#ifndef dcache_clean
-#define dcache_clean(_addr, _size)
-#endif
+//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-#ifndef dcache_invalidate
-#define dcache_invalidate(_addr, _size)
-#endif
+TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
+ if (rhport >= DWC2_CONTROLLER_COUNT) {
+ // user mis-configured, ignore and use first controller
+ rhport = 0;
+ }
+ return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
+}
-#ifndef dcache_clean_invalidate
-#define dcache_clean_invalidate(_addr, _size)
-#endif
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
typedef struct {
uint8_t* buffer;
@@ -93,106 +93,235 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+static uint16_t _dfifo_top; // top free location in FIFO RAM
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
-static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
+// Number of IN endpoints active
+static uint8_t _allocated_ep_in_count;
// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
static bool _sof_en;
-// Calculate the RX FIFO size according to minimum recommendations from reference manual
-// RxFIFO = (5 * number of control endpoints + 8) +
-// ((largest USB packet used / 4) + 1 for status information) +
-// (2 * number of OUT endpoints) + 1 for Global NAK
-// with number of control endpoints = 1 we have
-// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints
-// we double the largest USB packet size to be able to hold up to 2 packets
-static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) {
- return 15 + 2 * (max_ep_size / 4) + 2 * ep_count;
+//--------------------------------------------------------------------
+// DMA
+//--------------------------------------------------------------------
+
+TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) {
+ #if !CFG_TUD_DWC2_DMA
+ (void) dwc2;
+ return false;
+ #else
+ // Internal DMA only
+ return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA);
+ #endif
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) {
+ // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count;
+}
+
+static void dma_setup_prepare(uint8_t rhport) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+ if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
+ if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) {
+ return;
+ }
+ }
+
+ // Receive only 1 packet
+ dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
+ dwc2->epout[0].doepdma = (uintptr_t)_setup_packet;
+ dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
}
-TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
+//--------------------------------------------------------------------+
+// Data FIFO
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
// flush TX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
}
-TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) {
+TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
// flush RX fifo and wait for it cleared
dwc2->grstctl = GRSTCTL_RXFFLSH;
while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
}
-static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
+/* USB Data FIFO Layout
+
+ The FIFO is split up into
+ - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called
+ EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before
+ gahbcfg.dmaen is set
+ - Buffer mode: 1 word per endpoint direction
+ - Scatter/Gather DMA: 4 words per endpoint direction
+ - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN.
+ - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size.
+
+ We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is
+ possible since the free space is located between the RX and TX FIFOs.
+
+ ---------------- ep_fifo_size
+ | EPInfo |
+ | for DMA |
+ |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
+ | IN FIFO 0 |
+ | control |
+ |-------------|
+ | IN FIFO 1 |
+ |-------------|
+ | . . . . |
+ |-------------|
+ | IN FIFO n |
+ |-------------|
+ | FREE |
+ |-------------|-- GRXFSIZ (expandable)
+ | OUT FIFO |
+ | ( Shared ) |
+ --------------- 0
+
+ According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+ - Each EP IN needs at least max packet size
+ - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
+ - 13 for setup packets + control words (up to 3 setup packets).
+ - 1 for global NAK (not required/used here).
+ - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
+ - 2 for each used OUT endpoint
+
+ Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
+*/
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
+ return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
+}
+
+static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ uint8_t const ep_count = dwc2_controller->ep_count;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
TU_ASSERT(epnum < ep_count);
uint16_t fifo_size = tu_div_ceil(packet_size, 4);
-
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO 0 |
- // --------------- (320 or 1024) - 16
- // | IN FIFO 1 |
- // --------------- (320 or 1024) - 16 - x
- // | . . . . |
- // --------------- (320 or 1024) - 16 - x - y - ... - z
- // | IN FIFO MAX |
- // ---------------
- // | FREE |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // In FIFO is allocated by following rules:
- // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
if (dir == TUSB_DIR_OUT) {
// Calculate required size of RX FIFO
- uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count);
-
- // If size_rx needs to be extended check if possible and if so enlarge it
- if (dwc2->grxfsiz < sz) {
- TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4);
+ uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count);
- // Enlarge RX FIFO
- dwc2->grxfsiz = sz;
+ // If size_rx needs to be extended check if there is enough free space
+ if (dwc2->grxfsiz < new_sz) {
+ TU_ASSERT(new_sz <= _dfifo_top);
+ dwc2->grxfsiz = new_sz; // Enlarge RX FIFO
}
} else {
- // Note if The TXFELVL is configured as half empty. In order
- // to be able to write a packet at that point, the fifo must be twice the max_size.
+ // Check IN endpoints concurrently active limit
+ if(_dwc2_controller->ep_in_count) {
+ TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
+ _allocated_ep_in_count++;
+ }
+
+ // If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
fifo_size *= 2;
}
// Check if free space is available
- TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4);
- _allocated_fifo_words_tx += fifo_size;
- TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %" PRIu32, fifo_size * 4,
- _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4);
+ TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz);
+ _dfifo_top -= fifo_size;
+ TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top);
- // DIEPTXF starts at FIFO #1.
// Both TXFD and TXSA are in unit of 32-bit words.
- dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) |
- (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
+ if (epnum == 0) {
+ dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top;
+ } else {
+ // DIEPTXF starts at FIFO #1.
+ dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top;
+ }
}
return true;
}
+static void dfifo_init(uint8_t rhport) {
+ const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count);
+
+ if(dma_enabled(dwc2)) {
+ // DMA use last DFIFO to store metadata
+ _dfifo_top = dma_cal_epfifo_base(rhport);
+ }else {
+ _dfifo_top = dwc2_controller->ep_fifo_size / 4;
+ }
+
+ // Allocate FIFO for EP0 IN
+ dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
+}
+
+// Read a single data packet from receive FIFO
+static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile const uint32_t* rx_fifo = dwc2->fifo[0];
+
+ // Reading full available 32 bit words from fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ tu_unaligned_write32(dst, *rx_fifo);
+ dst += 4;
+ }
+
+ // Read the remaining 1-3 bytes from fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem != 0) {
+ uint32_t const tmp = *rx_fifo;
+ dst[0] = tu_u32_byte0(tmp);
+ if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
+ if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
+ }
+}
+
+// Write a single data packet to EPIN FIFO
+static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
+ (void) rhport;
+
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
+
+ // Pushing full available 32 bit words to fifo
+ uint16_t full_words = len >> 2;
+ while (full_words--) {
+ *tx_fifo = tu_unaligned_read32(src);
+ src += 4;
+ }
+
+ // Write the remaining 1-3 bytes into fifo
+ uint8_t const bytes_rem = len & 0x03;
+ if (bytes_rem) {
+ uint32_t tmp_word = src[0];
+ if (bytes_rem > 1) tmp_word |= (src[1] << 8);
+ if (bytes_rem > 2) tmp_word |= (src[2] << 16);
+
+ *tx_fifo = tmp_word;
+ }
+}
+
+//--------------------------------------------------------------------
+// Endpoint
+//--------------------------------------------------------------------
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// Keep count of how many FIFOs are in use
static uint8_t _allocated_fifos = 1; //FIFO0 is always in use
// Will either return an unused FIFO number, or 0 if all are used.
-static uint8_t get_free_fifo(void)
-{
+static uint8_t get_free_fifo(void) {
if (_allocated_fifos < 5) return _allocated_fifos++;
return 0;
}
@@ -208,15 +337,12 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
xfer->interval = p_endpoint_desc->bInterval;
// USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints.
- uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
- (xfer->max_size << DOEPCTL_MPSIZ_Pos);
-
- if (dir == TUSB_DIR_OUT) {
- dwc2->epout[epnum].doepctl = dxepctl;
- dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
- } else {
+ uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+ (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+ (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+ if (dir == TUSB_DIR_IN) {
+ //epctl |= (epnum << DIEPCTL_TXFNUM_Pos);
uint8_t fifo_num = epnum;
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// Special Case for EP5, which is used by CDC but not actually called by the driver
@@ -226,45 +352,46 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
} else {
fifo_num = get_free_fifo();
}
+ //TU_ASSERT(fifo_num != 0);
#endif
- dwc2->epin[epnum].diepctl = dxepctl | (fifo_num << DIEPCTL_TXFNUM_Pos);
- dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+ epctl |= (fifo_num << DIEPCTL_TXFNUM_Pos);
}
+
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
+ dep->ctl = epctl;
+ dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir));
}
static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
+ const uint8_t epnum = tu_edpt_number(ep_addr);
+ const uint8_t dir = tu_edpt_dir(ep_addr);
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
if (dir == TUSB_DIR_IN) {
- dwc2_epin_t* epin = dwc2->epin;
-
// Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) {
- epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+ if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) {
+ dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
} else {
// Stop transmitting packets and NAK IN xfers.
- epin[epnum].diepctl |= DIEPCTL_SNAK;
- while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {}
+ dep->diepctl |= DIEPCTL_SNAK;
+ while ((dep->diepint & DIEPINT_INEPNE) == 0) {}
// Disable the endpoint.
- epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
- while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {}
+ dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+ while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {}
- epin[epnum].diepint = DIEPINT_EPDISD;
+ dep->diepint = DIEPINT_EPDISD;
}
// Flush the FIFO, and wait until we have confirmed it cleared.
- fifo_flush_tx(dwc2, epnum);
+ dfifo_flush_tx(dwc2, epnum);
} else {
- dwc2_epout_t* epout = dwc2->epout;
-
// Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) {
- epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+ if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) {
+ dep->doepctl |= stall ? DOEPCTL_STALL : 0;
} else {
// Asserting GONAK is required to STALL an OUT endpoint.
// Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
@@ -273,11 +400,11 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
dwc2->dctl |= DCTL_SGONAK;
while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {}
- // Ditto here- disable the endpoint.
- epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
- while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {}
+ // Ditto here disable the endpoint.
+ dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+ while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {}
- epout[epnum].doepint = DOEPINT_EPDISD;
+ dep->doepint = DOEPINT_EPDISD;
// Allow other OUT endpoints to keep receiving.
dwc2->dctl |= DCTL_CGONAK;
@@ -293,9 +420,7 @@ static void bus_reset(uint8_t rhport) {
tu_memclr(xfer_status, sizeof(xfer_status));
_sof_en = false;
-
- // clear device address
- dwc2->dcfg &= ~DCFG_DAD_Msk;
+ _allocated_ep_in_count = 1;
// 1. NAK for all OUT endpoints
for (uint8_t n = 0; n < ep_count; n++) {
@@ -309,79 +434,32 @@ static void bus_reset(uint8_t rhport) {
}
}
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
- // 3. Set up interrupt mask
+ // 3. Set up interrupt mask for EP0
dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
- // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
- // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
- // configuration done below.
- //
- // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
- // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
- // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
- // opened when the host sends an additional command: setInterface. At this point in time
- // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
- // an additional memory
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO 0 |
- // --------------- (320 or 1024) - 16
- // | IN FIFO 1 |
- // --------------- (320 or 1024) - 16 - x
- // | . . . . |
- // --------------- (320 or 1024) - 16 - x - y - ... - z
- // | IN FIFO MAX |
- // ---------------
- // | FREE |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
- // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
- //
- // - All EP OUT shared a unique OUT FIFO which uses
- // - 13 for setup packets + control words (up to 3 setup packets).
- // - 1 for global NAK (not required/used here).
- // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
- // - 2 for each used OUT endpoint
- //
- // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
- // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x ep_count = 47 + 2 x ep_count
- // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count
- //
- // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
- // of the overall picture yet. We will use the worst scenario: largest possible + ep_count
- //
- // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
- // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to
- // overwrite this.
-
- // EP0 out max is 64
- dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
-
- // Setup the control endpoint 0
- _allocated_fifo_words_tx = 16;
-
- // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
- dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx);
-
- // Fixed control EP0 size to 64 bytes
+ // 4. Set up DFIFO
+ dfifo_init(rhport);
+
+ // 5. Reset device address
+ dwc2->dcfg &= ~DCFG_DAD_Msk;
+
+ // Fixed both control EP0 size to 64 bytes
dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+ dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
+
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
xfer_status[0][TUSB_DIR_IN].max_size = 64;
- dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ if(dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
+ } else {
+ dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ }
dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
}
@@ -391,68 +469,73 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
// EP0 is limited to one packet each xfer
// We use multiple transaction of xfer->max_size length to get a whole transfer done
if (epnum == 0) {
- xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
ep0_pending[dir] -= total_bytes;
}
// IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
- if (dir == TUSB_DIR_IN) {
- dwc2_epin_t* epin = dwc2->epin;
+ const uint8_t is_epout = 1 - dir;
+ dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum];
+ if (dir == TUSB_DIR_IN) {
// A full IN transfer (multiple packets, possibly) triggers XFRC.
- epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+ dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
- epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ if(dma_enabled(dwc2)) {
+ dep->diepdma = (uintptr_t)xfer->buffer;
- // For ISO endpoint set correct odd/even bit for next frame.
- if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
- }
- // Enable fifo empty interrupt only if there are something to put in the fifo.
- if (total_bytes != 0) {
- dwc2->diepempmsk |= (1 << epnum);
+ // For ISO endpoint set correct odd/even bit for next frame.
+ if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+ }
+
+ dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ } else {
+ dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+
+ // For ISO endpoint set correct odd/even bit for next frame.
+ if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
+ // Take odd/even bit from frame counter.
+ uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
+ dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+ }
+ // Enable fifo empty interrupt only if there are something to put in the fifo.
+ if (total_bytes != 0) {
+ dwc2->diepempmsk |= (1 << epnum);
+ }
}
} else {
- dwc2_epout_t* epout = dwc2->epout;
-
// A full OUT transfer (multiple packets, possibly) triggers XFRC.
- epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
- epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+ dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+ dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
- epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
- if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
+ if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
XFER_CTL_BASE(epnum, dir)->interval == 1) {
// Take odd/even bit from frame counter.
uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+ dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
}
+
+ if(dma_enabled(dwc2)) {
+ dep->doepdma = (uintptr_t)xfer->buffer;
+ }
+
+ dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
}
}
/*------------------------------------------------------------------*/
/* Controller API
*------------------------------------------------------------------*/
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-void print_dwc2_info(dwc2_regs_t* dwc2) {
- // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
- // use dwc2_info.py/md for bit-field value and comparison with other ports
- volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
- TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
- for (size_t i = 0; i < 5; i++) {
- TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]);
- }
- TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]);
-}
-#endif
static void reset_core(dwc2_regs_t* dwc2) {
// reset core
@@ -471,13 +554,10 @@ static void reset_core(dwc2_regs_t* dwc2) {
static bool phy_hs_supported(dwc2_regs_t* dwc2) {
(void) dwc2;
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
- // note: esp32 incorrect report its hs_phy_type as utmi
- return false;
-#elif !TUD_OPT_HIGH_SPEED
+#if !TUD_OPT_HIGH_SPEED
return false;
#else
- return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+ return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
#endif
}
@@ -488,7 +568,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg |= GUSBCFG_PHYSEL;
// MCU specific PHY init before reset
- dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
+ dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// Reset core after selecting PHY
reset_core(dwc2);
@@ -499,7 +579,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
// MCU specific PHY update post reset
- dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
+ dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
// set max speed
dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
@@ -511,7 +591,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// De-select FS PHY
gusbcfg &= ~GUSBCFG_PHYSEL;
- if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) {
+ if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
// Select ULPI
@@ -532,7 +612,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
// Set 16-bit interface if supported
- if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+ if (dwc2->ghwcfg4_bm.phy_data_width) {
+ gusbcfg |= GUSBCFG_PHYIF16;
+ }
}
// Apply config
@@ -548,7 +630,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// - 9 if using 8-bit PHY interface
// - 5 if using 16-bit PHY interface
gusbcfg &= ~GUSBCFG_TRDT_Msk;
- gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+ gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
dwc2->gusbcfg = gusbcfg;
// MCU specific PHY update post reset
@@ -561,17 +643,26 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
- if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
+ if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+ dcfg |= DCFG_XCVRDLY;
+ }
dwc2->dcfg = dcfg;
}
static bool check_dwc2(dwc2_regs_t* dwc2) {
#if CFG_TUSB_DEBUG >= DWC2_DEBUG
- print_dwc2_info(dwc2);
+ // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
+ // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
+ volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
+ TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
+ for (size_t i = 0; i < 5; i++) {
+ TU_LOG1("0x%08" PRIX32 ", ", p[i]);
+ }
+ TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
#endif
- // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+ // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
(void) dwc2;
#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
@@ -581,18 +672,17 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
return true;
}
-void dcd_init(uint8_t rhport) {
+bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
+ (void) rhport;
+ (void) rh_init;
// Programming model begins in the last section of the chapter on the USB
// peripheral in each Reference Manual.
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Check Synopsys ID register, failed if controller clock/power is not enabled
- if (!check_dwc2(dwc2)) return;
+ TU_ASSERT(check_dwc2(dwc2));
dcd_disconnect(rhport);
- // max number of endpoints & total_fifo_size are:
- // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
-
if (phy_hs_supported(dwc2)) {
phy_hs_init(dwc2); // Highspeed
} else {
@@ -622,8 +712,8 @@ void dcd_init(uint8_t rhport) {
// (non zero-length packet), send STALL back and discard.
dwc2->dcfg |= DCFG_NZLSOHSK;
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
// Clear all interrupts
uint32_t int_mask = dwc2->gintsts;
@@ -632,12 +722,21 @@ void dcd_init(uint8_t rhport) {
dwc2->gotgint |= int_mask;
// Required as part of core initialization.
- dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM |
- GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
+ dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
// Configure TX FIFO empty level for interrupt. Default is complete empty
dwc2->gahbcfg |= GAHBCFG_TXFELVL;
+ if (dma_enabled(dwc2)) {
+ const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
+ dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
+
+ // DMA seems to be only settable after a core reset
+ dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
+ }else {
+ dwc2->gintmsk |= GINTMSK_RXFLVLM;
+ }
+
// Enable global interrupt
dwc2->gahbcfg |= GAHBCFG_GINT;
@@ -650,6 +749,8 @@ void dcd_init(uint8_t rhport) {
// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
dcd_connect(rhport);
+
+ return true;
}
void dcd_int_enable(uint8_t rhport) {
@@ -689,12 +790,34 @@ void dcd_remote_wakeup(uint8_t rhport) {
void dcd_connect(uint8_t rhport) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+ usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+ conf.pad_pull_override = 0;
+ conf.dp_pullup = 0;
+ conf.dp_pulldown = 0;
+ conf.dm_pullup = 0;
+ conf.dm_pulldown = 0;
+ USB_WRAP.otg_conf = conf;
+#endif
+
dwc2->dctl &= ~DCTL_SDIS;
}
void dcd_disconnect(uint8_t rhport) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+
+#ifdef TUP_USBIP_DWC2_ESP32
+ usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf;
+ conf.pad_pull_override = 1;
+ conf.dp_pullup = 0;
+ conf.dp_pulldown = 1;
+ conf.dm_pullup = 0;
+ conf.dm_pulldown = 1;
+ USB_WRAP.otg_conf = conf;
+#endif
+
dwc2->dctl |= DCTL_SDIS;
}
@@ -718,7 +841,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
*------------------------------------------------------------------*/
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) {
- TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
+ TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt)));
edpt_activate(rhport, desc_edpt);
return true;
}
@@ -728,47 +851,40 @@ void dcd_edpt_close_all(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+ _allocated_ep_in_count = 1;
+
// Disable non-control interrupt
dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
for (uint8_t n = 1; n < ep_count; n++) {
- // disable OUT endpoint
- if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) {
- dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS;
- }
- xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
- // disable IN endpoint
- if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
- dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+ for (uint8_t d = 0; d < 2; d++) {
+ dwc2_dep_t* dep = &dwc2->ep[d][n];
+ if (dep->ctl & EPCTL_EPENA) {
+ dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS;
+ }
+ xfer_status[n][1-d].max_size = 0;
}
- xfer_status[n][TUSB_DIR_IN].max_size = 0;
}
- // reset allocated fifo OUT
- dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
- // reset allocated fifo IN
- _allocated_fifo_words_tx = 16;
-
#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
_allocated_fifos = 1;
#endif
- fifo_flush_tx(dwc2, 0x10); // all tx fifo
- fifo_flush_rx(dwc2);
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
+
+ dfifo_init(rhport); // re-init dfifo
}
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
- TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size));
+ TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size));
return true;
}
bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
// Disable EP to clear potential incomplete transfers
edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false);
-
edpt_activate(rhport, p_endpoint_desc);
-
return true;
}
@@ -821,7 +937,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
uint16_t const short_packet_size = total_bytes % xfer->max_size;
// Zero-size packet is special case.
- if (short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+ if (short_packet_size > 0 || (total_bytes == 0)) {
+ num_packets++;
+ }
// Schedule packets to be sent within interrupt
edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -835,100 +953,38 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
edpt_disable(rhport, ep_addr, true);
+ if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) {
+ dma_setup_prepare(rhport);
+ }
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
- (void) rhport;
-
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
-
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
+ dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
// Clear stall and reset data toggle
- if (dir == TUSB_DIR_IN) {
- dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
- dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
- } else {
- dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
- dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
- }
+ dep->ctl &= ~EPCTL_STALL;;
+ dep->ctl |= EPCTL_SD0PID_SEVNFRM;
}
-/*------------------------------------------------------------------*/
-
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile const uint32_t* rx_fifo = dwc2->fifo[0];
-
- // Reading full available 32 bit words from fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- tu_unaligned_write32(dst, *rx_fifo);
- dst += 4;
- }
-
- // Read the remaining 1-3 bytes from fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem != 0) {
- uint32_t const tmp = *rx_fifo;
- dst[0] = tu_u32_byte0(tmp);
- if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
- if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
- }
-}
-
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
-
- // Pushing full available 32 bit words to fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- *tx_fifo = tu_unaligned_read32(src);
- src += 4;
- }
-
- // Write the remaining 1-3 bytes into fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem) {
- uint32_t tmp_word = src[0];
- if (bytes_rem > 1) tmp_word |= (src[1] << 8);
- if (bytes_rem > 2) tmp_word |= (src[2] << 16);
-
- *tx_fifo = tmp_word;
- }
-}
+//--------------------------------------------------------------------
+// Interrupt Handler
+//--------------------------------------------------------------------
+// Process shared receive FIFO, this interrupt is only used in Slave mode
static void handle_rxflvl_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
volatile uint32_t const* rx_fifo = dwc2->fifo[0];
// Pop control word off FIFO
- uint32_t const ctl_word = dwc2->grxstsp;
- uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
- uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
- uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
-
+ uint32_t const grxstsp = dwc2->grxstsp;
+ uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+ uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
+ uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
dwc2_epout_t* epout = &dwc2->epout[epnum];
-//#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-// const char * pktsts_str[] =
-// {
-// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
-// "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
-// };
-// TU_LOG_LOCATION();
-// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
-// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
-//#endif
-
switch (pktsts) {
// Global OUT NAK: do nothing
case GRXSTS_PKTSTS_GLOBALOUTNAK:
@@ -936,15 +992,14 @@ static void handle_rxflvl_irq(uint8_t rhport) {
case GRXSTS_PKTSTS_SETUPRX:
// Setup packet received
-
- // We can receive up to three setup packets in succession, but
- // only the last one is valid.
+ // We can receive up to three setup packets in succession, but only the last one is valid.
_setup_packet[0] = (*rx_fifo);
_setup_packet[1] = (*rx_fifo);
break;
case GRXSTS_PKTSTS_SETUPDONE:
- // Setup packet done (Interrupt)
+ // Setup packet done:
+ // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
break;
@@ -958,7 +1013,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
} else {
// Linear buffer
- read_fifo_packet(rhport, xfer->buffer, bcnt);
+ dfifo_read_packet(rhport, xfer->buffer, bcnt);
// Increment pointer to xfer data
xfer->buffer += bcnt;
@@ -972,34 +1027,16 @@ static void handle_rxflvl_irq(uint8_t rhport) {
ep0_pending[TUSB_DIR_OUT] = 0;
}
}
- }
break;
+ }
- // Out packet done (Interrupt)
case GRXSTS_PKTSTS_OUTDONE:
- // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
- // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
- // XFRC complete is additionally generated when
- // - setup packet is received
- // - complete the data stage of control write is complete
- if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
- uint32_t doepint = epout->doepint;
-
- if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) {
- // skip this "no-data" transfer complete event
- // Note: STPKTRX will be clear later by setup received handler
- uint32_t clear_flags = DOEPINT_XFRC;
-
- if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
-
- epout->doepint = clear_flags;
-
- // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n");
- }
- }
+ /* Out packet done
+ After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
+ the specified OUT endpoint which will be handled by handle_epout_irq() */
break;
- default: // Invalid
+ default:
TU_BREAKPOINT();
break;
}
@@ -1011,37 +1048,68 @@ static void handle_epout_irq(uint8_t rhport) {
// DAINT for a given EP clears when DOEPINTx is cleared.
// OEPINT will be cleared when DAINT's out bits are cleared.
- for (uint8_t n = 0; n < ep_count; n++) {
- if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) {
- dwc2_epout_t* epout = &dwc2->epout[n];
+ for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
+ if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) {
+ dwc2_epout_t* epout = &dwc2->epout[epnum];
+ const uint32_t doepint = epout->doepint;
+ TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, );
+
+ // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently.
+ if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
+ if (doepint & DOEPINT_STSPHSRX) {
+ // Status phase received for control write: In token received from Host
+ epout->doepint = DOEPINT_STSPHSRX;
+ }
- uint32_t const doepint = epout->doepint;
+ if (doepint & DOEPINT_STPKTRX) {
+ // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively
+ epout->doepint = DOEPINT_STPKTRX;
+ }
+ }
- // SETUP packet Setup Phase done.
- if (doepint & DOEPINT_STUP) {
- uint32_t clear_flag = DOEPINT_STUP;
+ if (doepint & DOEPINT_SETUP) {
+ epout->doepint = DOEPINT_SETUP;
- // STPKTRX is only available for version from 3_00a
- if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) {
- clear_flag |= DOEPINT_STPKTRX;
+ if(dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
}
- epout->doepint = clear_flag;
dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
}
// OUT XFER complete
- if (epout->doepint & DOEPINT_XFRC) {
+ if (doepint & DOEPINT_XFRC) {
epout->doepint = DOEPINT_XFRC;
- xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
- // EP0 can only handle one packet
- if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
- // Schedule another packet to be received.
- edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
- } else {
- dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ // only handle data skip if it is setup or status related
+ // Normal OUT transfer complete
+ if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) {
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+ if(dma_enabled(dwc2)) {
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // EP0 can only handle one packet Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+ } else {
+ // Fix packet length
+ uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+ xfer->total_len -= remain;
+ // this is ZLP, so prepare EP0 for next setup
+ if(epnum == 0 && xfer->total_len == 0) {
+ dma_setup_prepare(rhport);
+ }
+
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ } else {
+ // EP0 can only handle one packet
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+ } else {
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
}
}
}
@@ -1068,6 +1136,9 @@ static void handle_epin_irq(uint8_t rhport) {
// Schedule another packet to be transmitted.
edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
} else {
+ if((n == 0) && dma_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
+ }
dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
}
@@ -1097,7 +1168,7 @@ static void handle_epin_irq(uint8_t rhport) {
volatile uint32_t* tx_fifo = dwc2->fifo[n];
tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
} else {
- write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+ dfifo_write_packet(rhport, n, xfer->buffer, packet_size);
// Increment pointer to xfer data
xfer->buffer += packet_size;
@@ -1113,6 +1184,29 @@ static void handle_epin_irq(uint8_t rhport) {
}
}
+/* Interrupt Hierarchy
+
+ DxEPMSK.XferComplMsk DxEPINTn.XferCompl
+ | |
+ +---------- AND --------+
+ |
+ DAINT.xEPnInt DAINTMSK.xEPnMsk
+ | |
+ +---------- AND --------+
+ |
+ GINTSTS.xEPInt GINTMSK.xEPIntMsk
+ | |
+ +---------- AND --------+
+ |
+ GAHBCFG.GblIntrMsk
+ |
+ IRQn
+
+ Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
+ are combined to generate dedicated interrupt line for each endpoint.
+ */
+
+
void dcd_int_handler(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
@@ -1200,13 +1294,10 @@ void dcd_int_handler(uint8_t rhport) {
// RxFIFO non-empty interrupt handling.
if (int_status & GINTSTS_RXFLVL) {
// RXFLVL bit is read-only
+ dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading
- // Mask out RXFLVL while reading data from FIFO
- dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
-
- // Loop until all available packets were handled
do {
- handle_rxflvl_irq(rhport);
+ handle_rxflvl_irq(rhport); // read all packets
} while(dwc2->gintsts & GINTSTS_RXFLVL);
dwc2->gintmsk |= GINTMSK_RXFLVLM;
@@ -1231,25 +1322,13 @@ void dcd_int_handler(uint8_t rhport) {
// }
}
-#if defined(TUP_USBIP_DWC2_TEST_MODE) && CFG_TUD_TEST_MODE
-
-bool dcd_check_test_mode_support(test_mode_t test_selector) {
- // Check if test mode selector is unsupported
- if (TEST_FORCE_ENABLE < test_selector || TEST_J > test_selector) {
- return false;
- }
-
- return true;
-}
-
-void dcd_enter_test_mode(uint8_t rhport, test_mode_t test_selector) {
- // Get port address...
+#if CFG_TUD_TEST_MODE
+void dcd_enter_test_mode(uint8_t rhport, tusb_feature_test_mode_t test_selector) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
// Enable the test mode
- dwc2->dctl = (dwc2->dctl & ~DCTL_TCTL_Msk) | (test_selector << DCTL_TCTL_Pos);
+ dwc2->dctl = (dwc2->dctl & ~DCTL_TCTL_Msk) | (((uint8_t) test_selector) << DCTL_TCTL_Pos);
}
-
-#endif /* TUP_USBIP_DWC2_TEST_MODE && CFG_TUD_TEST_MODE */
+#endif
#endif
From f6b9b22166f07c1d5944b1764b08bc2d63448083 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 15:16:07 +0200
Subject: [PATCH 33/57] Update CMakeLists.txt
---
components/arduino_tinyusb/CMakeLists.txt | 26 +++++++++++++----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/components/arduino_tinyusb/CMakeLists.txt b/components/arduino_tinyusb/CMakeLists.txt
index b0227ec5a..6a2e35150 100755
--- a/components/arduino_tinyusb/CMakeLists.txt
+++ b/components/arduino_tinyusb/CMakeLists.txt
@@ -15,14 +15,18 @@ if(CONFIG_TINYUSB_ENABLED)
"-DCFG_TUSB_DEBUG=${CONFIG_TINYUSB_DEBUG_LEVEL}"
"-Wno-type-limits" # needed for the vanila tinyusb with turned off classes
)
+ elseif(IDF_TARGET STREQUAL "esp32p4")
+ set(compile_options
+ "-DCFG_TUSB_MCU=OPT_MCU_ESP32P4"
+ "-DCFG_TUSB_DEBUG=${CONFIG_TINYUSB_DEBUG_LEVEL}"
+ "-Wno-type-limits" # needed for the vanila tinyusb with turned off classes
+ )
endif()
set(srcs
# espressif:
- #"${COMPONENT_DIR}/src/dcd_esp32sx.c"
"${COMPONENT_DIR}/src/dcd_dwc2.c"
# tusb:
- #"${COMPONENT_DIR}/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c"
#"{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c"
"${COMPONENT_DIR}/tinyusb/src/class/cdc/cdc_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/hid/hid_device.c"
@@ -32,6 +36,7 @@ if(CONFIG_TINYUSB_ENABLED)
"${COMPONENT_DIR}/tinyusb/src/class/dfu/dfu_rt_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/dfu/dfu_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/vendor/vendor_device.c"
+ "${COMPONENT_DIR}/tinyusb/src/class/net/ncm_device.c"
"${COMPONENT_DIR}/tinyusb/src/common/tusb_fifo.c"
"${COMPONENT_DIR}/tinyusb/src/device/usbd_control.c"
"${COMPONENT_DIR}/tinyusb/src/device/usbd.c"
@@ -56,16 +61,15 @@ if(CONFIG_TINYUSB_ENABLED)
set(requires esp_rom freertos soc)
set(priv_requires arduino main)
- ### tinyusb lib ###
- ###################
- idf_component_register(INCLUDE_DIRS ${includes_public} PRIV_INCLUDE_DIRS ${includes_private} SRCS ${srcs} REQUIRES ${requires} PRIV_REQUIRES ${priv_requires})
- # add_library(${COMPONENT_TARGET} STATIC ${srcs})
- # target_include_directories(
- # ${COMPONENT_TARGET}
- # PUBLIC ${includes_public}
- # PRIVATE ${includes_private})
+
+ idf_component_register(
+ INCLUDE_DIRS ${includes_public}
+ PRIV_INCLUDE_DIRS ${includes_private}
+ SRCS ${srcs}
+ REQUIRES ${requires}
+ PRIV_REQUIRES ${priv_requires}
+ )
target_compile_options(${COMPONENT_TARGET} PRIVATE ${compile_options})
- #target_link_libraries(${COMPONENT_TARGET} INTERFACE ${COMPONENT_TARGET})
else()
From 1557fc45f7af691abf70e5cb05ab6009dcde0b09 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 15:17:24 +0200
Subject: [PATCH 34/57] Update Kconfig.projbuild
---
components/arduino_tinyusb/Kconfig.projbuild | 39 +++++++++++++++-----
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/components/arduino_tinyusb/Kconfig.projbuild b/components/arduino_tinyusb/Kconfig.projbuild
index 50e24b6a6..65d9c37be 100755
--- a/components/arduino_tinyusb/Kconfig.projbuild
+++ b/components/arduino_tinyusb/Kconfig.projbuild
@@ -4,7 +4,7 @@ menu "Arduino TinyUSB"
config TINYUSB_ENABLED
bool "Enable TinyUSB driver"
default y
- depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
select FREERTOS_SUPPORT_STATIC_ALLOCATION
select FREERTOS_USE_AUTHENTIC_INCLUDE_PATHS
help
@@ -28,14 +28,16 @@ menu "Arduino TinyUSB"
config TINYUSB_CDC_RX_BUFSIZE
int "CDC FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of RX
config TINYUSB_CDC_TX_BUFSIZE
int "CDC FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of TX
@@ -86,7 +88,8 @@ menu "Arduino TinyUSB"
config TINYUSB_HID_BUFSIZE
int "HID Buffer size"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_HID_ENABLED
help
HID Buffer size. Should be sufficient to hold ID (if any) + Data
@@ -111,14 +114,16 @@ menu "Arduino TinyUSB"
config TINYUSB_MIDI_RX_BUFSIZE
int "MIDI FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of RX
config TINYUSB_MIDI_TX_BUFSIZE
int "MIDI FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of TX
@@ -143,8 +148,9 @@ menu "Arduino TinyUSB"
config TINYUSB_VIDEO_STREAMING_BUFSIZE
int "VIDEO streaming endpoint size"
- range 0 64
- default 64
+ range 0 512
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VIDEO_ENABLED
help
VIDEO streaming endpoint size
@@ -219,20 +225,33 @@ menu "Arduino TinyUSB"
config TINYUSB_VENDOR_RX_BUFSIZE
int "VENDOR FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of RX
config TINYUSB_VENDOR_TX_BUFSIZE
int "VENDOR FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of TX
endmenu
+ menu "NCM driver"
+ depends on TINYUSB_ENABLED
+
+ config TINYUSB_NCM_ENABLED
+ bool "Enable USB NCM TinyUSB driver"
+ default y
+ help
+ Enable USB NCM TinyUSB driver.
+
+ endmenu
+
config TINYUSB_DEBUG_LEVEL
int "TinyUSB log level (0-3)"
default 0
From d88630b2881f1d2cf326dbac00e8539a0e8c8235 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 15:18:17 +0200
Subject: [PATCH 35/57] Update tusb_config.h
---
components/arduino_tinyusb/include/tusb_config.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h
index f4acaa232..458c78cf1 100755
--- a/components/arduino_tinyusb/include/tusb_config.h
+++ b/components/arduino_tinyusb/include/tusb_config.h
@@ -72,6 +72,10 @@ extern "C" {
# define CONFIG_TINYUSB_VENDOR_ENABLED 0
#endif
+#ifndef CONFIG_TINYUSB_NCM_ENABLED
+# define CONFIG_TINYUSB_NCM_ENABLED 0
+#endif
+
/* */
/* COMMON CONFIGURATION */
/* */
@@ -96,11 +100,18 @@ extern "C" {
# define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4)
#endif
+#if CONFIG_IDF_TARGET_ESP32P4
+#define CFG_TUD_MAX_SPEED OPT_MODE_HIGH_SPEED
+#else
+#define CFG_TUD_MAX_SPEED OPT_MODE_FULL_SPEED
+#endif
+
/* */
/* DRIVER CONFIGURATION */
/* */
#define CFG_TUD_MAINTASK_SIZE 4096
+#define CFG_TUD_ENDOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
#define CFG_TUD_ENDOINT0_SIZE 64
// Enabled Drivers
@@ -113,6 +124,7 @@ extern "C" {
#define CFG_TUD_DFU_RUNTIME CONFIG_TINYUSB_DFU_RT_ENABLED
#define CFG_TUD_DFU CONFIG_TINYUSB_DFU_ENABLED
#define CFG_TUD_VENDOR CONFIG_TINYUSB_VENDOR_ENABLED
+#define CFG_TUD_NCM CONFIG_TINYUSB_NCM_ENABLED
// CDC FIFO size of TX and RX
#define CFG_TUD_CDC_RX_BUFSIZE CONFIG_TINYUSB_CDC_RX_BUFSIZE
From 850fcd72c1c35b1ce1a1c561db67f376ca9cc80e Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 23 Oct 2024 22:05:21 +0200
Subject: [PATCH 36/57] Delete components/arduino_tinyusb/src/dcd_esp32sx.c
---
components/arduino_tinyusb/src/dcd_esp32sx.c | 965 -------------------
1 file changed, 965 deletions(-)
delete mode 100755 components/arduino_tinyusb/src/dcd_esp32sx.c
diff --git a/components/arduino_tinyusb/src/dcd_esp32sx.c b/components/arduino_tinyusb/src/dcd_esp32sx.c
deleted file mode 100755
index 324aad595..000000000
--- a/components/arduino_tinyusb/src/dcd_esp32sx.c
+++ /dev/null
@@ -1,965 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Additions Copyright (c) 2020, Espressif Systems (Shanghai) Co. Ltd.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) || (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED)
-
-// Espressif
-#include "freertos/xtensa_api.h"
-#include "esp_intr_alloc.h"
-#include "esp_log.h"
-#include "soc/dport_reg.h"
-#include "soc/gpio_sig_map.h"
-#include "soc/usb_periph.h"
-#include "soc/usb_reg.h"
-#include "soc/usb_struct.h"
-#include "soc/periph_defs.h" // for interrupt source
-#include "soc/usb_wrap_struct.h"
-
-#include "device/dcd.h"
-
-#ifndef USB_OUT_EP_NUM
-#define USB_OUT_EP_NUM ((int) (sizeof(USB0.out_ep_reg) / sizeof(USB0.out_ep_reg[0])))
-#endif
-
-#ifndef USB_IN_EP_NUM
-#define USB_IN_EP_NUM ((int) (sizeof(USB0.in_ep_reg) / sizeof(USB0.in_ep_reg[0])))
-#endif
-
-// Max number of bi-directional endpoints including EP0
-// Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
-// We should probably prohibit enabling Endpoint IN > 4 (not done yet)
-#define EP_MAX USB_OUT_EP_NUM
-
-// FIFO size in bytes
-#define EP_FIFO_SIZE 1024
-
-// Max number of IN EP FIFOs
-#define EP_FIFO_NUM 5
-
-typedef struct {
- uint8_t *buffer;
- // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
- uint16_t total_len;
- uint16_t queued_len;
- uint16_t max_size;
- bool short_packet;
- uint8_t interval;
-} xfer_ctl_t;
-
-static const char *TAG = "TUSB:DCD";
-static intr_handle_t usb_ih;
-
-
-static uint32_t _setup_packet[2];
-
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-static xfer_ctl_t xfer_status[EP_MAX][2];
-
-// Keep count of how many FIFOs are in use
-static uint8_t _allocated_fifos = 1; //FIFO0 is always in use
-
-// Will either return an unused FIFO number, or 0 if all are used.
-static uint8_t get_free_fifo(void)
-{
- if (_allocated_fifos < EP_FIFO_NUM) return _allocated_fifos++;
- return 0;
-}
-
-// Setup the control endpoint 0.
-static void bus_reset(void)
-{
- for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) {
- USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
- }
-
- // clear device address
- USB0.dcfg &= ~USB_DEVADDR_M;
-
- USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M;
- USB0.doepmsk = USB_SETUPMSK_M | USB_XFERCOMPLMSK;
- USB0.diepmsk = USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
-
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO MAX |
- // ---------------
- // | ... |
- // --------------- y + x + 16 + GRXFSIZ
- // | IN FIFO 2 |
- // --------------- x + 16 + GRXFSIZ
- // | IN FIFO 1 |
- // --------------- 16 + GRXFSIZ
- // | IN FIFO 0 |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
- // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
- //
- // - All EP OUT shared a unique OUT FIFO which uses
- // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
- // * 2 locations for OUT endpoint control words.
- // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
- // * 1 location for global NAK (not required/used here).
- // * It is recommended to allocate 2 times the largest packet size, therefore
- // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
- USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10,
- USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo
- USB0.grxfsiz = 52;
-
- // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
- USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
-
- // Ready to receive SETUP packet
- USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M;
-
- USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
-}
-
-static void enum_done_processing(void)
-{
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
- // On current silicon on the Full Speed core, speed is fixed to Full Speed.
- // However, keep for debugging and in case Low Speed is ever supported.
- uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
-
- // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL
- if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz)
- USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes
- USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
- xfer_status[0][TUSB_DIR_OUT].max_size = 64;
- xfer_status[0][TUSB_DIR_IN].max_size = 64;
- } else {
- USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes
- USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
- xfer_status[0][TUSB_DIR_OUT].max_size = 8;
- xfer_status[0][TUSB_DIR_IN].max_size = 8;
- }
-}
-
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
- ESP_LOGV(TAG, "DCD init - Start");
-
- bool did_persist = (USB_WRAP.date.val & (1 << 31)) != 0;
-
- if (did_persist) {
- //Clear persistence of USB peripheral through reset
- USB_WRAP.date.val = 0;
- } else {
- // A. Disconnect
- ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up");
- USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect
-
- // B. Programming DCFG
- /* If USB host misbehaves during status portion of control xfer
- (non zero-length packet), send STALL back and discard. Full speed. */
- USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL
- (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476)
- }
-
- USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON
- USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode
- USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
-
- // C. Setting SNAKs, then connect
- for (int n = 0; n < USB_OUT_EP_NUM; n++) {
- USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
- }
-
- if (!did_persist) {
- // D. Interruption masking
- USB0.gintmsk = 0; //mask all
- USB0.gotgint = ~0U; //clear OTG ints
- USB0.gintsts = ~0U; //clear pending ints
- }
-
- USB0.gintmsk = USB_OTGINTMSK_M |
- USB_MODEMISMSK_M |
- USB_RXFLVIMSK_M |
- USB_ERLYSUSPMSK_M |
- USB_USBSUSPMSK_M |
- USB_USBRSTMSK_M |
- USB_ENUMDONEMSK_M |
- USB_RESETDETMSK_M |
- USB_DISCONNINTMSK_M; // host most only
- if (did_persist) {
- USB0.grstctl &= ~USB_TXFNUM_M;
- USB0.grstctl |= 0x10 << USB_TXFNUM_S;
- USB0.grstctl |= USB_TXFFLSH;
- USB0.grxfsiz = 52;
-
- for (int n = 0; n < USB_IN_EP_NUM; n++) {
- USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M | USB_D_TXFEMP0_M;
- USB0.in_ep_reg[n].diepctl &= ~USB_D_STALL0_M; // clear Stall
- USB0.in_ep_reg[n].diepctl |= USB_D_CNAK0 | USB_D_EPENA0; // clear NAK
- }
- USB0.dtknqr4_fifoemptymsk &= ~(0x7F);
-
- USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
-
- USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
- USB0.doepmsk |= USB_SETUP0 | USB_XFERCOMPLMSK;
- USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M;//USB_INEPNAKEFFMSK
-
- USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
- USB0.gotgint = ~0; //clear OTG ints
- USB0.gintsts = ~0; //clear pending ints
- enum_done_processing();
- dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
- tusb_control_request_t request = {
- .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, .type = TUSB_REQ_TYPE_STANDARD, .direction = TUSB_DIR_OUT },
- .bRequest = TUSB_REQ_SET_CONFIGURATION,
- .wValue = 1,
- .wIndex = 0,
- .wLength = 0
- };
- dcd_event_setup_received(0, (uint8_t *)&request, true);
- } else {
- dcd_connect(rhport);
- }
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
- (void)rhport;
- ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr);
- USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S);
- // Response with status after changing device address
- dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
- (void)rhport;
-
- // set remote wakeup
- USB0.dctl |= USB_RMTWKUPSIG_M;
-
- // enable SOF to detect bus resume
- USB0.gintsts = USB_SOF_M;
- USB0.gintmsk |= USB_SOFMSK_M;
-
- // Per specs: remote wakeup signal bit must be clear within 1-15ms
- vTaskDelay(pdMS_TO_TICKS(1));
-
- USB0.dctl &= ~USB_RMTWKUPSIG_M;
-}
-
-// connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
-{
- (void) rhport;
- USB0.dctl &= ~USB_SFTDISCON_M;
-}
-
-// disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
-{
- (void) rhport;
- USB0.dctl |= USB_SFTDISCON_M;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
- (void) rhport;
- (void) en;
-
- // TODO implement later
-}
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint port
- *------------------------------------------------------------------*/
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
-{
- ESP_LOGV(TAG, "DCD endpoint opened");
- (void)rhport;
-
- usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
- usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
-
- uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
- uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
- TU_ASSERT(epnum < EP_MAX);
-
- xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
- xfer->max_size = tu_edpt_packet_size(desc_edpt);
- xfer->interval = desc_edpt->bInterval;
-
- if (dir == TUSB_DIR_OUT) {
- out_ep[epnum].doepctl &= ~(USB_D_EPTYPE0_M | USB_D_MPS0_M);
- out_ep[epnum].doepctl |= USB_USBACTEP1_M |
- desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S |
- (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) |
- xfer->max_size << USB_MPS1_S;
- USB0.daintmsk |= (1 << (16 + epnum));
- } else {
- // "USB Data FIFOs" section in reference manual
- // Peripheral FIFO architecture
- //
- // --------------- 320 or 1024 ( 1280 or 4096 bytes )
- // | IN FIFO MAX |
- // ---------------
- // | ... |
- // --------------- y + x + 16 + GRXFSIZ
- // | IN FIFO 2 |
- // --------------- x + 16 + GRXFSIZ
- // | IN FIFO 1 |
- // --------------- 16 + GRXFSIZ
- // | IN FIFO 0 |
- // --------------- GRXFSIZ
- // | OUT FIFO |
- // | ( Shared ) |
- // --------------- 0
- //
- // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
- // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
- // - Offset: GRXFSIZ + 16 + Size*(epnum-1)
- // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
- uint8_t fifo_num = 0;
- // Special Case for EP5, which is used by CDC but not actually called by the driver
- // we can give it a fake FIFO
- if (epnum == 5) {
- fifo_num = EP_FIFO_NUM;
- } else {
- fifo_num = get_free_fifo();
- }
- TU_ASSERT(fifo_num != 0);
-
- in_ep[epnum].diepctl &= ~(USB_D_TXFNUM1_M | USB_D_EPTYPE1_M | USB_DI_SETD0PID1 | USB_D_MPS1_M);
- in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
- fifo_num << USB_D_TXFNUM1_S |
- desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
- (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
- xfer->max_size << 0;
-
- USB0.daintmsk |= (1 << (0 + epnum));
-
- // Both TXFD and TXSA are in unit of 32-bit words.
- // IN FIFO 0 was configured during enumeration, hence the "+ 16".
- uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16;
- uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_FIFO_NUM-1);
- uint32_t const fifo_offset = allocated_size + fifo_size*(fifo_num-1);
-
- // DIEPTXF starts at FIFO #1.
- USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset;
- }
- return true;
-}
-
-void dcd_edpt_close_all(uint8_t rhport)
-{
- (void) rhport;
-
- usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
- usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
-
- // Disable non-control interrupt
- USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M;
-
- for(uint8_t n = 1; n < EP_MAX; n++)
- {
- // disable OUT endpoint
- out_ep[n].doepctl = 0;
- xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
- // disable IN endpoint
- in_ep[n].diepctl = 0;
- xfer_status[n][TUSB_DIR_IN].max_size = 0;
- }
-
- _allocated_fifos = 1;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
-{
- (void)rhport;
-
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
-
- xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
- xfer->buffer = buffer;
- // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API
- xfer->total_len = total_bytes;
- xfer->queued_len = 0;
- xfer->short_packet = false;
-
- uint16_t num_packets = (total_bytes / xfer->max_size);
- uint8_t short_packet_size = total_bytes % xfer->max_size;
-
- // Zero-size packet is special case.
- if (short_packet_size > 0 || (total_bytes == 0)) {
- num_packets++;
- }
-
- ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i",
- epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"),
- num_packets, total_bytes);
-
- // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
- // here.
- if (dir == TUSB_DIR_IN) {
- // A full IN transfer (multiple packets, possibly) triggers XFRC.
- USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
- USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
-
- // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
- if ((USB0.in_ep_reg[epnum].diepctl & USB_D_EPTYPE0_M) == (1 << USB_D_EPTYPE1_S) && xfer->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (USB0.dsts & (1u << USB_SOFFN_S));
- USB0.in_ep_reg[epnum].diepctl |= (odd_frame_now ? USB_DI_SETD0PID1 : USB_DI_SETD1PID1);
- }
-
- // Enable fifo empty interrupt only if there are something to put in the fifo.
- if(total_bytes != 0) {
- USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
- }
- } else {
- // Each complete packet for OUT xfers triggers XFRC.
- USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
- USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
-
- // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
- if ((USB0.out_ep_reg[epnum].doepctl & USB_D_EPTYPE0_M) == (1 << USB_D_EPTYPE1_S) && xfer->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (USB0.dsts & (1u << USB_SOFFN_S));
- USB0.out_ep_reg[epnum].doepctl |= (odd_frame_now ? USB_DO_SETD0PID1 : USB_DO_SETD1PID1);
- }
- }
- return true;
-}
-
-#if 0 // TODO support dcd_edpt_xfer_fifo API
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
- (void)rhport;
-}
-#endif
-
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
- (void)rhport;
-
- usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
- usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
-
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
-
- if (dir == TUSB_DIR_IN) {
- // Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) {
- in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M);
- } else {
- // Stop transmitting packets and NAK IN xfers.
- in_ep[epnum].diepctl |= USB_DI_SNAK1_M;
- // while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) ;
- while ((in_ep[epnum].diepint & USB_D_INEPNAKEFF1_M) == 0) ;
-
- // Disable the endpoint. Note that both SNAK and STALL are set here.
- in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M);
- while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) ;
- in_ep[epnum].diepint = USB_D_EPDISBLD0_M;
- }
-
- // Flush the FIFO, and wait until we have confirmed it cleared.
- uint8_t const fifo_num = ((in_ep[epnum].diepctl >> USB_D_TXFNUM1_S) & USB_D_TXFNUM1_V);
- // USB0.grstctl |= (fifo_num << USB_TXFNUM_S);
- // USB0.grstctl |= USB_TXFFLSH_M;
- // while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ;
- uint32_t rstctl_last = USB0.grstctl;
- uint32_t rstctl = USB_TXFFLSH_M;
- rstctl |= (fifo_num << USB_TXFNUM_S);
- USB0.grstctl = rstctl;
- while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ;
- USB0.grstctl = rstctl_last;
- // TODO: Clear grstctl::fifo_num after fifo flsh
- } else {
- // Only disable currently enabled non-control endpoint
- if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) {
- out_ep[epnum].doepctl |= USB_STALL0_M;
- } else {
- // Asserting GONAK is required to STALL an OUT endpoint.
- // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
- // anyway, and it can't be cleared by user code. If this while loop never
- // finishes, we have bigger problems than just the stack.
- USB0.dctl |= USB_SGOUTNAK_M;
- while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) ;
-
- // Ditto here- disable the endpoint. Note that only STALL and not SNAK
- // is set here.
- out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M);
- while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) ;
- out_ep[epnum].doepint = USB_EPDISBLD0_M;
-
- // Allow other OUT endpoints to keep receiving.
- USB0.dctl |= USB_CGOUTNAK_M;
- }
- }
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
- (void)rhport;
-
- usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
- usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
-
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
-
- if (dir == TUSB_DIR_IN) {
- in_ep[epnum].diepctl &= ~USB_D_STALL1_M;
-
- uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S;
- // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
- // and bulk endpoints.
- if (eptype == 2 || eptype == 3) {
- in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M;
- }
- } else {
- out_ep[epnum].doepctl &= ~USB_STALL1_M;
-
- uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S;
- // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
- // and bulk endpoints.
- if (eptype == 2 || eptype == 3) {
- out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M;
- }
- }
-}
-
-/*------------------------------------------------------------------*/
-
-static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size)
-{
- ESP_EARLY_LOGV(TAG, "USB - receive_packet");
- volatile uint32_t *rx_fifo = USB0.fifo[0];
-
- // See above TODO
- // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos;
- // xfer->queued_len = xfer->total_len - remaining;
-
- uint16_t remaining = xfer->total_len - xfer->queued_len;
- uint16_t to_recv_size;
-
- if (remaining <= xfer->max_size) {
- // Avoid buffer overflow.
- to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
- } else {
- // Room for full packet, choose recv_size based on what the microcontroller
- // claims.
- to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
- }
-
- // Common buffer read
-#if 0 // TODO support dcd_edpt_xfer_fifo API
- if (xfer->ff)
- {
- // Ring buffer
- tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, to_recv_size);
- }
- else
-#endif
- {
- uint8_t to_recv_rem = to_recv_size % 4;
- uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
-
- // Do not assume xfer buffer is aligned.
- uint8_t *base = (xfer->buffer + xfer->queued_len);
-
- // This for loop always runs at least once- skip if less than 4 bytes
- // to collect.
- if (to_recv_size >= 4) {
- for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) {
- uint32_t tmp = (*rx_fifo);
- base[i] = tmp & 0x000000FF;
- base[i + 1] = (tmp & 0x0000FF00) >> 8;
- base[i + 2] = (tmp & 0x00FF0000) >> 16;
- base[i + 3] = (tmp & 0xFF000000) >> 24;
- }
- }
-
- // Do not read invalid bytes from RX FIFO.
- if (to_recv_rem != 0) {
- uint32_t tmp = (*rx_fifo);
- uint8_t *last_32b_bound = base + to_recv_size_aligned;
-
- last_32b_bound[0] = tmp & 0x000000FF;
- if (to_recv_rem > 1) {
- last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
- }
- if (to_recv_rem > 2) {
- last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
- }
- }
- }
-
- xfer->queued_len += xfer_size;
-
- // Per USB spec, a short OUT packet (including length 0) is always
- // indicative of the end of a transfer (at least for ctl, bulk, int).
- xfer->short_packet = (xfer_size < xfer->max_size);
-}
-
-static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num)
-{
- ESP_EARLY_LOGV(TAG, "USB - transmit_packet");
- volatile uint32_t *tx_fifo = USB0.fifo[fifo_num];
-
- uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S;
- xfer->queued_len = xfer->total_len - remaining;
-
- uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
-
-#if 0 // TODO support dcd_edpt_xfer_fifo API
- if (xfer->ff)
- {
- tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, to_xfer_size);
- }
- else
-#endif
- {
- uint8_t to_xfer_rem = to_xfer_size % 4;
- uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
-
- // Buffer might not be aligned to 32b, so we need to force alignment
- // by copying to a temp var.
- uint8_t *base = (xfer->buffer + xfer->queued_len);
-
- // This for loop always runs at least once- skip if less than 4 bytes
- // to send off.
- if (to_xfer_size >= 4) {
- for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
- uint32_t tmp = base[i] | (base[i + 1] << 8) |
- (base[i + 2] << 16) | (base[i + 3] << 24);
- (*tx_fifo) = tmp;
- }
- }
-
- // Do not read beyond end of buffer if not divisible by 4.
- if (to_xfer_rem != 0) {
- uint32_t tmp = 0;
- uint8_t *last_32b_bound = base + to_xfer_size_aligned;
-
- tmp |= last_32b_bound[0];
- if (to_xfer_rem > 1) {
- tmp |= (last_32b_bound[1] << 8);
- }
- if (to_xfer_rem > 2) {
- tmp |= (last_32b_bound[2] << 16);
- }
-
- (*tx_fifo) = tmp;
- }
- }
-}
-
-static void read_rx_fifo(void)
-{
- // Pop control word off FIFO (completed xfers will have 2 control words,
- // we only pop one ctl word each interrupt).
- uint32_t const ctl_word = USB0.grxstsp;
- uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
- uint8_t const epnum = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S;
- uint16_t const bcnt = (ctl_word & USB_BCNT_M ) >> USB_BCNT_S;
-
- switch (pktsts) {
- case 0x01: // Global OUT NAK (Interrupt)
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
- break;
-
- case 0x02: { // Out packet recvd
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet");
- xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
- receive_packet(xfer, bcnt);
- }
- break;
-
- case 0x03: // Out packet done (Interrupt)
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done");
- break;
-
- case 0x04: // Step 2: Setup transaction completed (Interrupt)
- // After this event, OEPINT interrupt will occur with SETUP bit set
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
- USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M;
- break;
-
- case 0x06: { // Step1: Setup data packet received
- volatile uint32_t *rx_fifo = USB0.fifo[0];
-
- // We can receive up to three setup packets in succession, but
- // only the last one is valid. Therefore we just overwrite it
- _setup_packet[0] = (*rx_fifo);
- _setup_packet[1] = (*rx_fifo);
-
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
- }
- break;
-
- default: // Invalid, do something here, like breakpoint?
- TU_BREAKPOINT();
- break;
- }
-}
-
-static void handle_epout_ints(void)
-{
- // GINTSTS will be cleared with DAINT == 0
- // DAINT for a given EP clears when DOEPINTx is cleared.
- // DOEPINT will be cleared when DAINT's out bits are cleared.
- for (int n = 0; n < USB_OUT_EP_NUM; n++) {
- xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
- if (USB0.daint & (1 << (16 + n))) {
- // SETUP packet Setup Phase done.
- if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
- USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
- dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
- }
-
- // OUT XFER complete (single packet).q
- if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) {
-
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)");
- USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M;
-
- // Transfer complete if short packet or total len is transferred
- if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
- xfer->short_packet = false;
- dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
- } else {
- // Schedule another packet to be received.
- USB0.out_ep_reg[n].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
- USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
- }
- }
- }
- }
-}
-
-static void handle_epin_ints(void)
-{
- // GINTSTS will be cleared with DAINT == 0
- // DAINT for a given EP clears when DIEPINTx is cleared.
- // IEPINT will be cleared when DAINT's out bits are cleared.
- for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) {
- xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
-
- if (USB0.daint & (1 << (0 + n))) {
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n);
-
- if (USB0.in_ep_reg[n].diepint & BIT(15)) {
- USB0.in_ep_reg[n].diepint = BIT(15);
- ESP_EARLY_LOGE(TAG, "Unknown Condition");//todo:
- bus_reset();
- }
-
- // IN XFER complete (entire xfer).
- if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!");
- USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M;
- dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
- if (!(USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M)) {
- ESP_EARLY_LOGE(TAG, "Complete but not empty: %u/%u", xfer->queued_len, xfer->total_len);//todo:
- }
- }
-
- // XFER FIFO empty
- if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) {
- ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!");
- USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M;
- transmit_packet(xfer, &USB0.in_ep_reg[n], n);
-
- // Turn off TXFE if all bytes are written.
- if (xfer->queued_len == xfer->total_len)
- {
- USB0.dtknqr4_fifoemptymsk &= ~(1 << n);
- }
- }
-
- // XFER Timeout
- if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) {
- // Clear interrupt or enpoint will hang.
- USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M;
- ESP_EARLY_LOGE(TAG, "XFER Timeout");//todo:
- // Maybe retry?
- }
- }
- }
-}
-
-
-static void _dcd_int_handler(void* arg)
-{
- (void) arg;
- uint8_t const rhport = 0;
-
- const uint32_t int_msk = USB0.gintmsk;
- const uint32_t int_status = USB0.gintsts & int_msk;
-
- if (int_status & USB_USBRST_M) {
- // start of reset
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
- USB0.gintsts = USB_USBRST_M;
- // FIFOs will be reassigned when the endpoints are reopen
- _allocated_fifos = 1;
- bus_reset();
- }
-
- if (int_status & USB_RESETDET_M) {
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
- USB0.gintsts = USB_RESETDET_M;
- // no need to double reset
- if ((int_status & USB_USBRST_M) == 0) {
- _allocated_fifos = 1;
- bus_reset();
- }
- }
-
- if (int_status & USB_ENUMDONE_M) {
- // ENUMDNE detects speed of the link. For full-speed, we
- // always expect the same value. This interrupt is considered
- // the end of reset.
- USB0.gintsts = USB_ENUMDONE_M;
- enum_done_processing();
- dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
- }
-
- if(int_status & USB_USBSUSP_M)
- {
- USB0.gintsts = USB_USBSUSP_M;
- //dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
- dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
- _allocated_fifos = 1;
- }
-
- if(int_status & USB_WKUPINT_M)
- {
- USB0.gintsts = USB_WKUPINT_M;
- dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
- }
-
- if (int_status & USB_OTGINT_M)
- {
- // OTG INT bit is read-only
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
-
- uint32_t const otg_int = USB0.gotgint;
-
- if (otg_int & USB_SESENDDET_M)
- {
- dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
- _allocated_fifos = 1;
- }
-
- USB0.gotgint = otg_int;
- }
-
- if (int_status & USB_SOF_M) {
- USB0.gintsts = USB_SOF_M;
-
- // Disable SOF interrupt since currently only used for remote wakeup detection
- USB0.gintmsk &= ~USB_SOFMSK_M;
-
- dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
- }
-
-
- if (int_status & USB_RXFLVI_M) {
- // RXFLVL bit is read-only
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
-
- // Mask out RXFLVL while reading data from FIFO
- USB0.gintmsk &= ~USB_RXFLVIMSK_M;
- read_rx_fifo();
- USB0.gintmsk |= USB_RXFLVIMSK_M;
- }
-
- // OUT endpoint interrupt handling.
- if (int_status & USB_OEPINT_M) {
- // OEPINT is read-only
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
- handle_epout_ints();
- }
-
- // IN endpoint interrupt handling.
- if (int_status & USB_IEPINT_M) {
- // IEPINT bit read-only
- ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
- handle_epin_ints();
- }
-
- // Without handling
- USB0.gintsts |= USB_CURMOD_INT_M |
- USB_MODEMIS_M |
- USB_OTGINT_M |
- USB_NPTXFEMP_M |
- USB_GINNAKEFF_M |
- USB_GOUTNAKEFF |
- USB_ERLYSUSP_M |
- USB_USBSUSP_M |
- USB_ISOOUTDROP_M |
- USB_EOPF_M |
- USB_EPMIS_M |
- USB_INCOMPISOIN_M |
- USB_INCOMPIP_M |
- USB_FETSUSP_M |
- USB_PTXFEMP_M;
-}
-
-void dcd_int_enable (uint8_t rhport)
-{
- (void) rhport;
- esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) _dcd_int_handler, NULL, &usb_ih);
-}
-
-void dcd_int_disable (uint8_t rhport)
-{
- (void) rhport;
- esp_intr_free(usb_ih);
-}
-
-#endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3
-
From 4278fbc8f8ba03c1ba904c7ccd0c593594c2ee60 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Thu, 24 Oct 2024 09:39:59 +0200
Subject: [PATCH 37/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index e76bdf70e..0be3c6eee 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -316,7 +316,7 @@ static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const*
//--------------------------------------------------------------------
// Endpoint
//--------------------------------------------------------------------
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
// Keep count of how many FIFOs are in use
static uint8_t _allocated_fifos = 1; //FIFO0 is always in use
@@ -344,7 +344,7 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
if (dir == TUSB_DIR_IN) {
//epctl |= (epnum << DIEPCTL_TXFNUM_Pos);
uint8_t fifo_num = epnum;
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
// Special Case for EP5, which is used by CDC but not actually called by the driver
// we can give it a fake FIFO
if (epnum == 5) {
@@ -866,7 +866,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
}
}
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
_allocated_fifos = 1;
#endif
@@ -1216,7 +1216,7 @@ void dcd_int_handler(uint8_t rhport) {
if (int_status & GINTSTS_USBRST) {
// USBRST is start of reset.
dwc2->gintsts = GINTSTS_USBRST;
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
_allocated_fifos = 1;
#endif
bus_reset(rhport);
@@ -1252,7 +1252,7 @@ void dcd_int_handler(uint8_t rhport) {
dwc2->gintsts = GINTSTS_USBSUSP;
//dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
_allocated_fifos = 1;
#endif
}
@@ -1271,7 +1271,7 @@ void dcd_int_handler(uint8_t rhport) {
if (otg_int & GOTGINT_SEDET) {
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#if defined(TUP_USBIP_DWC2_ESP32)
_allocated_fifos = 1;
#endif
}
From 71121f6c144cc3602ca29ef1df6e2f63a01d5da1 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Thu, 24 Oct 2024 09:44:15 +0200
Subject: [PATCH 38/57] Update Kconfig.projbuild
---
components/arduino_tinyusb/Kconfig.projbuild | 28 +++++++-------------
1 file changed, 10 insertions(+), 18 deletions(-)
diff --git a/components/arduino_tinyusb/Kconfig.projbuild b/components/arduino_tinyusb/Kconfig.projbuild
index 65d9c37be..1db30506f 100755
--- a/components/arduino_tinyusb/Kconfig.projbuild
+++ b/components/arduino_tinyusb/Kconfig.projbuild
@@ -4,7 +4,7 @@ menu "Arduino TinyUSB"
config TINYUSB_ENABLED
bool "Enable TinyUSB driver"
default y
- depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
+ depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
select FREERTOS_SUPPORT_STATIC_ALLOCATION
select FREERTOS_USE_AUTHENTIC_INCLUDE_PATHS
help
@@ -28,16 +28,14 @@ menu "Arduino TinyUSB"
config TINYUSB_CDC_RX_BUFSIZE
int "CDC FIFO size of RX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of RX
config TINYUSB_CDC_TX_BUFSIZE
int "CDC FIFO size of TX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of TX
@@ -88,8 +86,7 @@ menu "Arduino TinyUSB"
config TINYUSB_HID_BUFSIZE
int "HID Buffer size"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_HID_ENABLED
help
HID Buffer size. Should be sufficient to hold ID (if any) + Data
@@ -114,16 +111,14 @@ menu "Arduino TinyUSB"
config TINYUSB_MIDI_RX_BUFSIZE
int "MIDI FIFO size of RX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of RX
config TINYUSB_MIDI_TX_BUFSIZE
int "MIDI FIFO size of TX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of TX
@@ -148,9 +143,8 @@ menu "Arduino TinyUSB"
config TINYUSB_VIDEO_STREAMING_BUFSIZE
int "VIDEO streaming endpoint size"
- range 0 512
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ range 0 64
+ default 64
depends on TINYUSB_VIDEO_ENABLED
help
VIDEO streaming endpoint size
@@ -225,16 +219,14 @@ menu "Arduino TinyUSB"
config TINYUSB_VENDOR_RX_BUFSIZE
int "VENDOR FIFO size of RX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of RX
config TINYUSB_VENDOR_TX_BUFSIZE
int "VENDOR FIFO size of TX"
- default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
- default 512 if IDF_TARGET_ESP32P4
+ default 64
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of TX
From f4001766f2a2ffd1a1696c3b53d94c9171185e46 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 6 Nov 2024 12:09:35 +0100
Subject: [PATCH 39/57] fix(zigbee): Unlink the zigbee libs
---
tools/copy-libs.sh | 64 ++++++++++++++++++++++++++++------------------
1 file changed, 39 insertions(+), 25 deletions(-)
diff --git a/tools/copy-libs.sh b/tools/copy-libs.sh
index 896effc0e..41672b5b3 100755
--- a/tools/copy-libs.sh
+++ b/tools/copy-libs.sh
@@ -56,6 +56,8 @@ AS_FLAGS=""
INCLUDES=""
DEFINES=""
+EXCLUDE_LIBS=";"
+
LD_FLAGS=""
LD_LIBS=""
LD_LIB_FILES=""
@@ -78,6 +80,17 @@ else
TOOLCHAIN="riscv32-esp-elf"
fi
+# copy zigbee + zboss lib
+if [ -d "managed_components/espressif__esp-zigbee-lib/lib/$IDF_TARGET/" ]; then
+ cp -r "managed_components/espressif__esp-zigbee-lib/lib/$IDF_TARGET"/* "$AR_SDK/lib/"
+ EXCLUDE_LIBS+="esp_zb_api_ed;"
+fi
+
+if [ -d "managed_components/espressif__esp-zboss-lib/lib/$IDF_TARGET/" ]; then
+ cp -r "managed_components/espressif__esp-zboss-lib/lib/$IDF_TARGET"/* "$AR_SDK/lib/"
+ EXCLUDE_LIBS+="zboss_stack.ed;zboss_port.debug;"
+fi
+
#collect includes, defines and c-flags
str=`cat build/compile_commands.json | grep arduino-lib-builder-gcc.c | grep command | cut -d':' -f2 | cut -d',' -f1`
str="${str:2:${#str}-1}" #remove leading space and quotes
@@ -200,12 +213,14 @@ for item; do
add_next=1
LD_FLAGS+="$item "
elif [ "${item:0:2}" = "-l" ]; then # -l[lib_name]
- LD_LIBS+="$item "
- exclude_libs=";m;c;gcc;stdc++;"
short_name="${item:2}"
- if [[ $exclude_libs != *";$short_name;"* && $LD_LIBS_SEARCH != *"lib$short_name.a"* ]]; then
- LD_LIBS_SEARCH+="lib$short_name.a "
- #echo "lib add: $item"
+ if [[ $EXCLUDE_LIBS != *";$short_name;"* ]]; then
+ LD_LIBS+="$item "
+ exclude_libs=";m;c;gcc;stdc++;"
+ if [[ $exclude_libs != *";$short_name;"* && $LD_LIBS_SEARCH != *"lib$short_name.a"* ]]; then
+ LD_LIBS_SEARCH+="lib$short_name.a "
+ #echo "1. lib add: $item"
+ fi
fi
elif [ "$item" = "-o" ]; then
add_next=0
@@ -244,30 +259,38 @@ for item; do
if [[ $LD_LIB_FILES != *"$item"* ]]; then
# do we already have lib with the same name?
if [[ $LD_LIBS != *"-l$lname"* ]]; then
- # echo "collecting lib '$lname' and file: $item"
- LD_LIB_FILES+="$item "
- LD_LIBS+="-l$lname "
+ if [[ $EXCLUDE_LIBS != *";$lname;"* ]]; then
+ #echo "2. collecting lib '$lname' and file: $item"
+ LD_LIB_FILES+="$item "
+ LD_LIBS+="-l$lname "
+ fi
else
# echo "!!! need to rename: '$lname'"
for i in {2..9}; do
n_item="${item:0:${#item}-2}_$i.a"
n_name=$lname"_$i"
if [ -f "$n_item" ]; then
- # echo "renamed add: -l$n_name"
- LD_LIBS+="-l$n_name "
+ if [[ $EXCLUDE_LIBS != *";$lname;"* ]]; then
+ #echo "3. renamed add: -l$n_name"
+ LD_LIBS+="-l$n_name "
+ fi
break
elif [[ $LD_LIB_FILES != *"$n_item"* && $LD_LIBS != *"-l$n_name"* ]]; then
- echo "Renaming '$lname' to '$n_name': $item"
- cp -f "$item" "$n_item"
- LD_LIB_FILES+="$n_item "
- LD_LIBS+="-l$n_name "
+ if [[ $EXCLUDE_LIBS != *";$lname;"* ]]; then
+ #echo "4. Renaming '$lname' to '$n_name': $item"
+ cp -f "$item" "$n_item"
+ LD_LIB_FILES+="$n_item "
+ LD_LIBS+="-l$n_name "
+ fi
break
fi
done
fi
else
- # echo "just add: -l$lname"
- LD_LIBS+="-l$lname "
+ if [[ $EXCLUDE_LIBS != *";$lname;"* ]]; then
+ #echo "5. just add: -l$lname"
+ LD_LIBS+="-l$lname "
+ fi
fi
else
echo "*** Skipping $(basename $item): size too small $lsize"
@@ -493,15 +516,6 @@ echo -n "$LD_FLAGS" > "$FLAGS_DIR/ld_flags"
echo -n "$LD_SCRIPTS" > "$FLAGS_DIR/ld_scripts"
echo -n "$AR_LIBS" > "$FLAGS_DIR/ld_libs"
-# copy zigbee + zboss lib
-if [ -d "managed_components/espressif__esp-zigbee-lib/lib/$IDF_TARGET/" ]; then
- cp -r "managed_components/espressif__esp-zigbee-lib/lib/$IDF_TARGET"/* "$AR_SDK/lib/"
-fi
-
-if [ -d "managed_components/espressif__esp-zboss-lib/lib/$IDF_TARGET/" ]; then
- cp -r "managed_components/espressif__esp-zboss-lib/lib/$IDF_TARGET"/* "$AR_SDK/lib/"
-fi
-
if [ -d "managed_components/espressif__esp32-camera/driver/private_include/" ]; then
cp -r "managed_components/espressif__esp32-camera/driver/private_include/cam_hal.h" "$AR_SDK/include/espressif__esp32-camera/driver/include/"
fi
From 10c0c24780a2d9136e4c8b4cd99bb2a5cbb42707 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 6 Nov 2024 13:03:22 +0100
Subject: [PATCH 40/57] Update copy-libs.sh
---
tools/copy-libs.sh | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/copy-libs.sh b/tools/copy-libs.sh
index 41672b5b3..669718a7f 100755
--- a/tools/copy-libs.sh
+++ b/tools/copy-libs.sh
@@ -39,7 +39,9 @@ fi
if [ -e "$AR_SDK/platformio-build.py" ]; then
rm -rf "$AR_SDK/platformio-build.py"
fi
+
mkdir -p "$AR_SDK"
+mkdir -p "$AR_SDK/lib"
function get_actual_path(){
p="$PWD"; cd "$1"; r="$PWD"; cd "$p"; echo "$r";
@@ -450,8 +452,6 @@ echo " join(FRAMEWORK_DIR, \"cores\", board_config.get(\"build.core\"))"
echo " ]," >> "$AR_PLATFORMIO_PY"
echo "" >> "$AR_PLATFORMIO_PY"
-mkdir -p "$AR_SDK/lib"
-
AR_LIBS="$LD_LIBS"
PIO_LIBS=""
set -- $LD_LIBS
From 14ad0491f6ef601f58531f9b8b1c11377683f91f Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 12 Nov 2024 23:01:09 +0100
Subject: [PATCH 41/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 489 +++++-----------------
1 file changed, 106 insertions(+), 383 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index 0be3c6eee..00d0584b4 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -35,45 +35,7 @@
#define DWC2_DEBUG 2
#include "device/dcd.h"
-#include "dwc2_type.h"
-
-// Following symbols must be defined by port header
-// - _dwc2_controller[]: array of controllers
-// - DWC2_EP_MAX: largest EP counts of all controllers
-// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
-// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
-// - dwc2_remote_wakeup_delay
-
-#if defined(TUP_USBIP_DWC2_STM32)
- #include "dwc2_stm32.h"
-#elif defined(TUP_USBIP_DWC2_ESP32)
- #include "dwc2_esp32.h"
-#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
- #include "dwc2_gd32.h"
-#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
- #include "dwc2_bcm.h"
-#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
- #include "dwc2_efm32.h"
-#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
- #include "dwc2_xmc.h"
-#else
- #error "Unsupported MCUs"
-#endif
-
-enum {
- DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
-};
-
-// DWC2 registers
-//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
-
-TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
- if (rhport >= DWC2_CONTROLLER_COUNT) {
- // user mis-configured, ignore and use first controller
- rhport = 0;
- }
- return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
-}
+#include "dwc2_common.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
@@ -94,7 +56,7 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
// EP0 transfers are limited to 1 packet - larger sizes has to be split
static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
-static uint16_t _dfifo_top; // top free location in FIFO RAM
+static uint16_t _dfifo_top; // top free location in DFIFO in words
// Number of IN endpoints active
static uint8_t _allocated_ep_in_count;
@@ -106,20 +68,10 @@ static bool _sof_en;
// DMA
//--------------------------------------------------------------------
-TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) {
- #if !CFG_TUD_DWC2_DMA
+TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
(void) dwc2;
- return false;
- #else
// Internal DMA only
- return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA);
- #endif
-}
-
-TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) {
- // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
- const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
- return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count;
+ return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
}
static void dma_setup_prepare(uint8_t rhport) {
@@ -141,18 +93,8 @@ static void dma_setup_prepare(uint8_t rhport) {
// Data FIFO
//--------------------------------------------------------------------+
-TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) {
- // flush TX fifo and wait for it cleared
- dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos);
- while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {}
-}
-TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
- // flush RX fifo and wait for it cleared
- dwc2->grstctl = GRSTCTL_RXFFLSH;
- while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {}
-}
-/* USB Data FIFO Layout
+/* Device Data FIFO scheme
The FIFO is split up into
- EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called
@@ -167,11 +109,9 @@ TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
possible since the free space is located between the RX and TX FIFOs.
---------------- ep_fifo_size
- | EPInfo |
- | for DMA |
+ | DxEPIDMAn |
|-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth)
- | IN FIFO 0 |
- | control |
+ | IN FIFO 0 | control EP
|-------------|
| IN FIFO 1 |
|-------------|
@@ -190,13 +130,13 @@ TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) {
- All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula):
- 13 for setup packets + control words (up to 3 setup packets).
- 1 for global NAK (not required/used here).
- - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1"
+ - Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)"
- 2 for each used OUT endpoint
Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum
*/
-TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
+TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) {
return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count;
}
@@ -212,7 +152,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
uint16_t fifo_size = tu_div_ceil(packet_size, 4);
if (dir == TUSB_DIR_OUT) {
// Calculate required size of RX FIFO
- uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count);
+ uint16_t const new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
// If size_rx needs to be extended check if there is enough free space
if (dwc2->grxfsiz < new_sz) {
@@ -227,7 +167,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
}
// If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
- if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) {
+ if ((dwc2->gahbcfg & GAHBCFG_TX_FIFO_EPMTY_LVL) == 0) {
fifo_size *= 2;
}
@@ -248,70 +188,23 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
return true;
}
-static void dfifo_init(uint8_t rhport) {
+static void dfifo_device_init(uint8_t rhport) {
const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count);
+ dwc2->grxfsiz = calc_device_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count);
- if(dma_enabled(dwc2)) {
- // DMA use last DFIFO to store metadata
- _dfifo_top = dma_cal_epfifo_base(rhport);
- }else {
- _dfifo_top = dwc2_controller->ep_fifo_size / 4;
+ // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
+ const bool is_dma = dma_device_enabled(dwc2);
+ _dfifo_top = dwc2_controller->ep_fifo_size/4;
+ if (is_dma) {
+ _dfifo_top -= 2 * dwc2_controller->ep_count;
}
+ dwc2->gdfifocfg = (_dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dfifo_top;
// Allocate FIFO for EP0 IN
dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
}
-// Read a single data packet from receive FIFO
-static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile const uint32_t* rx_fifo = dwc2->fifo[0];
-
- // Reading full available 32 bit words from fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- tu_unaligned_write32(dst, *rx_fifo);
- dst += 4;
- }
-
- // Read the remaining 1-3 bytes from fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem != 0) {
- uint32_t const tmp = *rx_fifo;
- dst[0] = tu_u32_byte0(tmp);
- if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp);
- if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp);
- }
-}
-
-// Write a single data packet to EPIN FIFO
-static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) {
- (void) rhport;
-
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num];
-
- // Pushing full available 32 bit words to fifo
- uint16_t full_words = len >> 2;
- while (full_words--) {
- *tx_fifo = tu_unaligned_read32(src);
- src += 4;
- }
-
- // Write the remaining 1-3 bytes into fifo
- uint8_t const bytes_rem = len & 0x03;
- if (bytes_rem) {
- uint32_t tmp_word = src[0];
- if (bytes_rem > 1) tmp_word |= (src[1] << 8);
- if (bytes_rem > 2) tmp_word |= (src[2] << 16);
-
- *tx_fifo = tmp_word;
- }
-}
//--------------------------------------------------------------------
// Endpoint
@@ -326,7 +219,7 @@ static uint8_t get_free_fifo(void) {
return 0;
}
#endif
-
+
static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
@@ -434,6 +327,10 @@ static void bus_reset(uint8_t rhport) {
}
}
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+ _allocated_fifos = 1;
+#endif
+
dfifo_flush_tx(dwc2, 0x10); // all tx fifo
dfifo_flush_rx(dwc2);
@@ -443,7 +340,7 @@ static void bus_reset(uint8_t rhport) {
dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
// 4. Set up DFIFO
- dfifo_init(rhport);
+ dfifo_device_init(rhport);
// 5. Reset device address
dwc2->dcfg &= ~DCFG_DAD_Msk;
@@ -455,7 +352,7 @@ static void bus_reset(uint8_t rhport) {
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
xfer_status[0][TUSB_DIR_IN].max_size = 64;
- if(dma_enabled(dwc2)) {
+ if(dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport);
} else {
dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
@@ -485,9 +382,9 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
if (dir == TUSB_DIR_IN) {
// A full IN transfer (multiple packets, possibly) triggers XFRC.
dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
- ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
+ ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
- if(dma_enabled(dwc2)) {
+ if(dma_device_enabled(dwc2)) {
dep->diepdma = (uintptr_t)xfer->buffer;
// For ISO endpoint set correct odd/even bit for next frame.
@@ -525,7 +422,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
}
- if(dma_enabled(dwc2)) {
+ if(dma_device_enabled(dwc2)) {
dep->doepdma = (uintptr_t)xfer->buffer;
}
@@ -533,174 +430,41 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
}
}
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-
-static void reset_core(dwc2_regs_t* dwc2) {
- // reset core
- dwc2->grstctl |= GRSTCTL_CSRST;
-
- // wait for reset bit is cleared
- // TODO version 4.20a should wait for RESET DONE mask
- while (dwc2->grstctl & GRSTCTL_CSRST) {}
-
- // wait for AHB master IDLE
- while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
-
- // wait for device mode ?
-}
-
-static bool phy_hs_supported(dwc2_regs_t* dwc2) {
- (void) dwc2;
-
-#if !TUD_OPT_HIGH_SPEED
- return false;
-#else
- return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
-#endif
-}
-
-static void phy_fs_init(dwc2_regs_t* dwc2) {
- TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
-
- // Select FS PHY
- dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-
- // MCU specific PHY init before reset
- dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
-
- // Reset core after selecting PHY
- reset_core(dwc2);
-
- // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
- // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
- // these bits can be programmed to a larger value. Default is 5
- dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
-
- // MCU specific PHY update post reset
- dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
-
- // set max speed
- dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
-}
-
-static void phy_hs_init(dwc2_regs_t* dwc2) {
- uint32_t gusbcfg = dwc2->gusbcfg;
-
- // De-select FS PHY
- gusbcfg &= ~GUSBCFG_PHYSEL;
-
- if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
- TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
-
- // Select ULPI
- gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
-
- // ULPI 8-bit interface, single data rate
- gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
-
- // default internal VBUS Indicator and Drive
- gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-
- // Disable FS/LS ULPI
- gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
- } else {
- TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
-
- // Select UTMI+ with 8-bit interface
- gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
-
- // Set 16-bit interface if supported
- if (dwc2->ghwcfg4_bm.phy_data_width) {
- gusbcfg |= GUSBCFG_PHYIF16;
- }
- }
-
- // Apply config
- dwc2->gusbcfg = gusbcfg;
-
- // mcu specific phy init
- dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
-
- // Reset core after selecting PHY
- reset_core(dwc2);
-
- // Set turn-around, must after core reset otherwise it will be clear
- // - 9 if using 8-bit PHY interface
- // - 5 if using 16-bit PHY interface
- gusbcfg &= ~GUSBCFG_TRDT_Msk;
- gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
- dwc2->gusbcfg = gusbcfg;
-
- // MCU specific PHY update post reset
- dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
-
- // Set max speed
- uint32_t dcfg = dwc2->dcfg;
- dcfg &= ~DCFG_DSPD_Msk;
- dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
-
- // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
- // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
- if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
- dcfg |= DCFG_XCVRDLY;
- }
-
- dwc2->dcfg = dcfg;
-}
-
-static bool check_dwc2(dwc2_regs_t* dwc2) {
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
- // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
- // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
- volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
- TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
- for (size_t i = 0; i < 5; i++) {
- TU_LOG1("0x%08" PRIX32 ", ", p[i]);
- }
- TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
-#endif
-
- // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
- (void) dwc2;
-#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
- uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
- TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
-#endif
-
- return true;
-}
-
+//--------------------------------------------------------------------
+// Controller API
+//--------------------------------------------------------------------
bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
- (void) rhport;
(void) rh_init;
- // Programming model begins in the last section of the chapter on the USB
- // peripheral in each Reference Manual.
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- // Check Synopsys ID register, failed if controller clock/power is not enabled
- TU_ASSERT(check_dwc2(dwc2));
- dcd_disconnect(rhport);
+ // Core Initialization
+ const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
+ TU_ASSERT(dwc2_core_init(rhport, is_highspeed));
- if (phy_hs_supported(dwc2)) {
- phy_hs_init(dwc2); // Highspeed
+ if (dma_device_enabled(dwc2)) {
+ // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
+ dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
} else {
- phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
+ dwc2->gintmsk |= GINTSTS_RXFLVL;
}
- // Restart PHY clock
- dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
+ // Device Initialization
+ dcd_disconnect(rhport);
- /* Set HS/FS Timeout Calibration to 7 (max available value).
- * The number of PHY clocks that the application programs in
- * this field is added to the high/full speed interpacket timeout
- * duration in the core to account for any additional delays
- * introduced by the PHY. This can be required, because the delay
- * introduced by the PHY in generating the linestate condition
- * can vary from one PHY to another.
- */
- dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+ // Set device max speed
+ uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
+ if (is_highspeed) {
+ dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
+
+ // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
+ // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
+ if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+ dcfg |= DCFG_XCVRDLY;
+ }
+ }else {
+ dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos;
+ }
+ dwc2->dcfg = dcfg;
// Force device mode
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
@@ -708,48 +472,19 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
- // If USB host misbehaves during status portion of control xfer
- // (non zero-length packet), send STALL back and discard.
+ // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard
dwc2->dcfg |= DCFG_NZLSOHSK;
- dfifo_flush_tx(dwc2, 0x10); // all tx fifo
- dfifo_flush_rx(dwc2);
-
- // Clear all interrupts
- uint32_t int_mask = dwc2->gintsts;
- dwc2->gintsts |= int_mask;
- int_mask = dwc2->gotgint;
- dwc2->gotgint |= int_mask;
-
- // Required as part of core initialization.
- dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
-
- // Configure TX FIFO empty level for interrupt. Default is complete empty
- dwc2->gahbcfg |= GAHBCFG_TXFELVL;
-
- if (dma_enabled(dwc2)) {
- const uint16_t epinfo_base = dma_cal_epfifo_base(rhport);
- dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base;
+ // Enable required interrupts
+ dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
- // DMA seems to be only settable after a core reset
- dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
- }else {
- dwc2->gintmsk |= GINTMSK_RXFLVLM;
- }
-
- // Enable global interrupt
- dwc2->gahbcfg |= GAHBCFG_GINT;
-
- // make sure we are in device mode
-// TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), );
-
-// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
-// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
-// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
-// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
+ // TX FIFO empty level for interrupt is complete empty
+ uint32_t gahbcfg = dwc2->gahbcfg;
+ gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL;
+ gahbcfg |= GAHBCFG_GINT; // Enable global interrupt
+ dwc2->gahbcfg = gahbcfg;
dcd_connect(rhport);
-
return true;
}
@@ -873,7 +608,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
dfifo_flush_tx(dwc2, 0x10); // all tx fifo
dfifo_flush_rx(dwc2);
- dfifo_init(rhport); // re-init dfifo
+ dfifo_device_init(rhport); // re-init dfifo
}
bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {
@@ -904,11 +639,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
// Schedule the first transaction for EP0 transfer
edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
} else {
- uint16_t num_packets = (total_bytes / xfer->max_size);
- uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
- // Zero-size packet is special case.
- if ((short_packet_size > 0) || (total_bytes == 0)) num_packets++;
+ uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size);
+ if (num_packets == 0) {
+ num_packets = 1; // zero length packet still count as 1
+ }
// Schedule packets to be sent within interrupt
edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -952,8 +686,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
}
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
edpt_disable(rhport, ep_addr, true);
- if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) {
+ if((tu_edpt_number(ep_addr) == 0) && dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport);
}
}
@@ -976,16 +711,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
// Process shared receive FIFO, this interrupt is only used in Slave mode
static void handle_rxflvl_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- volatile uint32_t const* rx_fifo = dwc2->fifo[0];
+ const volatile uint32_t* rx_fifo = dwc2->fifo[0];
// Pop control word off FIFO
- uint32_t const grxstsp = dwc2->grxstsp;
- uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
- uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos;
- uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
+ const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
+ const uint8_t epnum = grxstsp_bm.ep_ch_num;
+ const uint16_t byte_count = grxstsp_bm.byte_count;
dwc2_epout_t* epout = &dwc2->epout[epnum];
- switch (pktsts) {
+ switch (grxstsp_bm.packet_status) {
// Global OUT NAK: do nothing
case GRXSTS_PKTSTS_GLOBALOUTNAK:
break;
@@ -1010,18 +744,18 @@ static void handle_rxflvl_irq(uint8_t rhport) {
// Read packet off RxFIFO
if (xfer->ff) {
// Ring buffer
- tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
+ tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
} else {
// Linear buffer
- dfifo_read_packet(rhport, xfer->buffer, bcnt);
+ dfifo_read_packet(dwc2, xfer->buffer, byte_count);
// Increment pointer to xfer data
- xfer->buffer += bcnt;
+ xfer->buffer += byte_count;
}
- // Truncate transfer length in case of short packet
- if (bcnt < xfer->max_size) {
- xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+ // short packet, minus remaining bytes (xfer_size)
+ if (byte_count < xfer->max_size) {
+ xfer->total_len -= epout->doeptsiz_bm.xfer_size;
if (epnum == 0) {
xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
ep0_pending[TUSB_DIR_OUT] = 0;
@@ -1070,7 +804,7 @@ static void handle_epout_irq(uint8_t rhport) {
if (doepint & DOEPINT_SETUP) {
epout->doepint = DOEPINT_SETUP;
- if(dma_enabled(dwc2)) {
+ if(dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport);
}
@@ -1086,7 +820,7 @@ static void handle_epout_irq(uint8_t rhport) {
if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) {
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
- if(dma_enabled(dwc2)) {
+ if(dma_device_enabled(dwc2)) {
if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
// EP0 can only handle one packet Schedule another packet to be received.
edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
@@ -1118,8 +852,7 @@ static void handle_epout_irq(uint8_t rhport) {
static void handle_epin_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
- dwc2_epin_t* epin = dwc2->epin;
+ const uint8_t ep_count = _dwc2_controller[rhport].ep_count;
// DAINT for a given EP clears when DIEPINTx is cleared.
// IEPINT will be cleared when DAINT's out bits are cleared.
@@ -1127,16 +860,17 @@ static void handle_epin_irq(uint8_t rhport) {
if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) {
// IN XFER complete (entire xfer).
xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+ dwc2_epin_t* epin = &dwc2->epin[n];
- if (epin[n].diepint & DIEPINT_XFRC) {
- epin[n].diepint = DIEPINT_XFRC;
+ if (epin->diepint & DIEPINT_XFRC) {
+ epin->diepint = DIEPINT_XFRC;
// EP0 can only handle one packet
if ((n == 0) && ep0_pending[TUSB_DIR_IN]) {
// Schedule another packet to be transmitted.
edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
} else {
- if((n == 0) && dma_enabled(dwc2)) {
+ if((n == 0) && dma_device_enabled(dwc2)) {
dma_setup_prepare(rhport);
}
dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -1144,39 +878,38 @@ static void handle_epin_irq(uint8_t rhport) {
}
// XFER FIFO empty
- if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
+ if ((epin->diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
// diepint's TXFE bit is read-only, software cannot clear it.
// It will only be cleared by hardware when written bytes is more than
// - 64 bytes or
- // - Half of TX FIFO size (configured by DIEPTXF)
-
- uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+ // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
+ const uint16_t remain_packets = epin->dieptsiz_bm.packet_count;
// Process every single packet (only whole packets can be written to fifo)
- for (uint16_t i = 0; i < remaining_packets; i++) {
- uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+ for (uint16_t i = 0; i < remain_packets; i++) {
+ const uint16_t remain_bytes = (uint16_t) epin->dieptsiz_bm.xfer_size;
// Packet can not be larger than ep max size
- uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
+ const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
// It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
// EP has to be checked if the buffer can take another WHOLE packet
- if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+ if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
+ break;
+ }
// Push packet to Tx-FIFO
if (xfer->ff) {
volatile uint32_t* tx_fifo = dwc2->fifo[n];
- tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
+ tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, xact_bytes);
} else {
- dfifo_write_packet(rhport, n, xfer->buffer, packet_size);
-
- // Increment pointer to xfer data
- xfer->buffer += packet_size;
+ dfifo_write_packet(dwc2, n, xfer->buffer, xact_bytes);
+ xfer->buffer += xact_bytes;
}
}
// Turn off TXFE if all bytes are written.
- if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) {
+ if (epin->dieptsiz_bm.xfer_size == 0) {
dwc2->diepempmsk &= ~(1 << n);
}
}
@@ -1186,21 +919,11 @@ static void handle_epin_irq(uint8_t rhport) {
/* Interrupt Hierarchy
- DxEPMSK.XferComplMsk DxEPINTn.XferCompl
- | |
- +---------- AND --------+
- |
- DAINT.xEPnInt DAINTMSK.xEPnMsk
- | |
- +---------- AND --------+
- |
- GINTSTS.xEPInt GINTMSK.xEPIntMsk
- | |
- +---------- AND --------+
- |
- GAHBCFG.GblIntrMsk
- |
- IRQn
+ DxEPINTn
+ |
+ DAINT.xEPn
+ |
+ GINTSTS: xEPInt
Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
are combined to generate dedicated interrupt line for each endpoint.
From ade40cfad90773b9bd3b88dfd881a84b6c049fb4 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 12 Nov 2024 23:18:14 +0100
Subject: [PATCH 42/57] Update CMakeLists.txt
---
components/arduino_tinyusb/CMakeLists.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/components/arduino_tinyusb/CMakeLists.txt b/components/arduino_tinyusb/CMakeLists.txt
index 6a2e35150..a3965728d 100755
--- a/components/arduino_tinyusb/CMakeLists.txt
+++ b/components/arduino_tinyusb/CMakeLists.txt
@@ -28,6 +28,7 @@ if(CONFIG_TINYUSB_ENABLED)
"${COMPONENT_DIR}/src/dcd_dwc2.c"
# tusb:
#"{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c"
+ "{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dwc2_common.c"
"${COMPONENT_DIR}/tinyusb/src/class/cdc/cdc_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/hid/hid_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/midi/midi_device.c"
From d7223b561fd614bc3d77f9b62e664bfb459f5bdc Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Wed, 13 Nov 2024 09:51:16 +0100
Subject: [PATCH 43/57] Update CMakeLists.txt
---
components/arduino_tinyusb/CMakeLists.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/components/arduino_tinyusb/CMakeLists.txt b/components/arduino_tinyusb/CMakeLists.txt
index a3965728d..fd6f5983d 100755
--- a/components/arduino_tinyusb/CMakeLists.txt
+++ b/components/arduino_tinyusb/CMakeLists.txt
@@ -27,8 +27,8 @@ if(CONFIG_TINYUSB_ENABLED)
# espressif:
"${COMPONENT_DIR}/src/dcd_dwc2.c"
# tusb:
- #"{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c"
- "{COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dwc2_common.c"
+ #"${COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c"
+ "${COMPONENT_DIR}/tinyusb/src/portable/synopsys/dwc2/dwc2_common.c"
"${COMPONENT_DIR}/tinyusb/src/class/cdc/cdc_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/hid/hid_device.c"
"${COMPONENT_DIR}/tinyusb/src/class/midi/midi_device.c"
From 50a58f5ed717f9e6fa931f394a49be686da1f163 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 19 Nov 2024 15:50:43 +0100
Subject: [PATCH 44/57] Update tinyusb...
---
components/arduino_tinyusb/src/dcd_dwc2.c | 746 +++++++++++-----------
1 file changed, 384 insertions(+), 362 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index 00d0584b4..da4709a72 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -37,6 +37,12 @@
#include "device/dcd.h"
#include "dwc2_common.h"
+#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
+ #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX
+#else
+ #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep)
+#endif
+
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
@@ -71,7 +77,7 @@ static bool _sof_en;
TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
(void) dwc2;
// Internal DMA only
- return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+ return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
}
static void dma_setup_prepare(uint8_t rhport) {
@@ -209,7 +215,7 @@ static void dfifo_device_init(uint8_t rhport) {
//--------------------------------------------------------------------
// Endpoint
//--------------------------------------------------------------------
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// Keep count of how many FIFOs are in use
static uint8_t _allocated_fifos = 1; //FIFO0 is always in use
@@ -222,22 +228,30 @@ static uint8_t get_free_fifo(void) {
static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
- uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+ const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+ const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir);
xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
xfer->interval = p_endpoint_desc->bInterval;
- // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints.
- uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
- (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
- (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+ // Endpoint control
+ union {
+ uint32_t value;
+ dwc2_depctl_t bm;
+ } depctl;
+ depctl.value = 0;
+
+ depctl.bm.mps = xfer->max_size;
+ depctl.bm.active = 1;
+ depctl.bm.type = p_endpoint_desc->bmAttributes.xfer;
+ if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
+ depctl.bm.set_data0_iso_even = 1;
+ }
if (dir == TUSB_DIR_IN) {
- //epctl |= (epnum << DIEPCTL_TXFNUM_Pos);
+ //depctl.bm.tx_fifo_num = epnum;
uint8_t fifo_num = epnum;
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
// Special Case for EP5, which is used by CDC but not actually called by the driver
// we can give it a fake FIFO
if (epnum == 5) {
@@ -245,13 +259,12 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
} else {
fifo_num = get_free_fifo();
}
- //TU_ASSERT(fifo_num != 0);
#endif
- epctl |= (fifo_num << DIEPCTL_TXFNUM_Pos);
+ depctl.bm.tx_fifo_num = fifo_num;
}
- dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
- dep->ctl = epctl;
+ dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
+ dep->ctl = depctl.value;
dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir));
}
@@ -261,7 +274,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
const uint8_t epnum = tu_edpt_number(ep_addr);
const uint8_t dir = tu_edpt_dir(ep_addr);
- dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
+ dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
if (dir == TUSB_DIR_IN) {
// Only disable currently enabled non-control endpoint
@@ -305,128 +318,66 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) {
}
}
-// Start of Bus Reset
-static void bus_reset(uint8_t rhport) {
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
-
- tu_memclr(xfer_status, sizeof(xfer_status));
-
- _sof_en = false;
- _allocated_ep_in_count = 1;
-
- // 1. NAK for all OUT endpoints
- for (uint8_t n = 0; n < ep_count; n++) {
- dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
- }
-
- // 2. Disable all IN endpoints
- for (uint8_t n = 0; n < ep_count; n++) {
- if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
- dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
- }
- }
-
-#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
- _allocated_fifos = 1;
-#endif
-
- dfifo_flush_tx(dwc2, 0x10); // all tx fifo
- dfifo_flush_rx(dwc2);
-
- // 3. Set up interrupt mask for EP0
- dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
- dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
- dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
-
- // 4. Set up DFIFO
- dfifo_device_init(rhport);
-
- // 5. Reset device address
- dwc2->dcfg &= ~DCFG_DAD_Msk;
-
- // Fixed both control EP0 size to 64 bytes
- dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
- dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
-
- xfer_status[0][TUSB_DIR_OUT].max_size = 64;
- xfer_status[0][TUSB_DIR_IN].max_size = 64;
-
- if(dma_device_enabled(dwc2)) {
- dma_setup_prepare(rhport);
- } else {
- dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
- }
-
- dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
-}
-
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets,
- uint16_t total_bytes) {
- (void) rhport;
-
+static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir);
+ dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
+
+ uint16_t num_packets;
+ uint16_t total_bytes;
- // EP0 is limited to one packet each xfer
- // We use multiple transaction of xfer->max_size length to get a whole transfer done
+ // EP0 is limited to one packet per xfer
if (epnum == 0) {
total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
ep0_pending[dir] -= total_bytes;
+ num_packets = 1;
+ } else {
+ total_bytes = xfer->total_len;
+ num_packets = tu_div_ceil(total_bytes, xfer->max_size);
+ if (num_packets == 0) {
+ num_packets = 1; // zero length packet still count as 1
+ }
}
- // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
- const uint8_t is_epout = 1 - dir;
- dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum];
-
- if (dir == TUSB_DIR_IN) {
- // A full IN transfer (multiple packets, possibly) triggers XFRC.
- dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
- ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
-
- if(dma_device_enabled(dwc2)) {
- dep->diepdma = (uintptr_t)xfer->buffer;
-
- // For ISO endpoint set correct odd/even bit for next frame.
- if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
- }
-
- dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC.
+ union {
+ uint32_t value;
+ dwc2_ep_tsize_t bm;
+ } deptsiz;
+ deptsiz.value = 0;
+ deptsiz.bm.xfer_size = total_bytes;
+ deptsiz.bm.packet_count = num_packets;
+
+ dep->tsiz = deptsiz.value;
+
+ // control
+ union {
+ dwc2_depctl_t bm;
+ uint32_t value;
+ } depctl;
+ depctl.value = dep->ctl;
+
+ depctl.bm.clear_nak = 1;
+ depctl.bm.enable = 1;
+ if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
+ const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u);
+ if (odd_now) {
+ depctl.bm.set_data0_iso_even = 1;
} else {
- dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
-
- // For ISO endpoint set correct odd/even bit for next frame.
- if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
- }
- // Enable fifo empty interrupt only if there are something to put in the fifo.
- if (total_bytes != 0) {
- dwc2->diepempmsk |= (1 << epnum);
- }
- }
- } else {
- // A full OUT transfer (multiple packets, possibly) triggers XFRC.
- dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
- dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
- ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
-
- if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
- XFER_CTL_BASE(epnum, dir)->interval == 1) {
- // Take odd/even bit from frame counter.
- uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
- dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+ depctl.bm.set_data1_iso_odd = 1;
}
+ }
- if(dma_device_enabled(dwc2)) {
- dep->doepdma = (uintptr_t)xfer->buffer;
- }
+ const bool is_dma = dma_device_enabled(dwc2);
+ if(is_dma) {
+ dep->diepdma = (uintptr_t) xfer->buffer;
+ }
+
+ dep->diepctl = depctl.value; // enable endpoint
- dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+ // Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable
+ if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) {
+ dwc2->diepempmsk |= (1 << epnum);
}
}
@@ -439,18 +390,10 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
// Core Initialization
const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
- TU_ASSERT(dwc2_core_init(rhport, is_highspeed));
-
- if (dma_device_enabled(dwc2)) {
- // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
- dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
- } else {
- dwc2->gintmsk |= GINTSTS_RXFLVL;
- }
-
- // Device Initialization
- dcd_disconnect(rhport);
+ const bool is_dma = dma_device_enabled(dwc2);
+ TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma));
+ //------------- 7.1 Device Initialization -------------//
// Set device max speed
uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk;
if (is_highspeed) {
@@ -461,20 +404,21 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
dcfg |= DCFG_XCVRDLY;
}
- }else {
+ } else {
dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos;
}
+
+ dcfg |= DCFG_NZLSOHSK; // send STALL back and discard if host send non-zlp during control status
dwc2->dcfg = dcfg;
+ dcd_disconnect(rhport);
+
// Force device mode
dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
// Clear A override, force B Valid
dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
- // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard
- dwc2->dcfg |= DCFG_NZLSOHSK;
-
// Enable required interrupts
dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
@@ -601,7 +545,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
}
}
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
_allocated_fifos = 1;
#endif
@@ -635,19 +579,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
// EP0 can only handle one packet
if (epnum == 0) {
ep0_pending[dir] = total_bytes;
-
- // Schedule the first transaction for EP0 transfer
- edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
- } else {
- uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size);
- if (num_packets == 0) {
- num_packets = 1; // zero length packet still count as 1
- }
-
- // Schedule packets to be sent within interrupt
- edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
}
+ // Schedule packets to be sent within interrupt
+ edpt_schedule_packets(rhport, epnum, dir);
+
return true;
}
@@ -667,16 +603,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
xfer->ff = ff;
xfer->total_len = total_bytes;
- uint16_t num_packets = (total_bytes / xfer->max_size);
- uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
- // Zero-size packet is special case.
- if (short_packet_size > 0 || (total_bytes == 0)) {
- num_packets++;
- }
-
// Schedule packets to be sent within interrupt
- edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+ // TODO xfer fifo may only available for slave mode
+ edpt_schedule_packets(rhport, epnum, dir);
return true;
}
@@ -697,7 +626,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
- dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum];
+ dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
// Clear stall and reset data toggle
dep->ctl &= ~EPCTL_STALL;;
@@ -708,6 +637,99 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
// Interrupt Handler
//--------------------------------------------------------------------
+// 7.4.1 Initialization on USB Reset
+static void handle_bus_reset(uint8_t rhport) {
+ dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+ const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
+
+ tu_memclr(xfer_status, sizeof(xfer_status));
+
+ _sof_en = false;
+ _allocated_ep_in_count = 1;
+
+ // 1. NAK for all OUT endpoints
+ for (uint8_t n = 0; n < ep_count; n++) {
+ dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
+ }
+
+ // Disable all IN endpoints
+ for (uint8_t n = 0; n < ep_count; n++) {
+ if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
+ dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
+ }
+ }
+
+ // 2. Set up interrupt mask for EP0
+ dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
+ dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+ dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
+
+ // 4. Set up DFIFO
+ dfifo_flush_tx(dwc2, 0x10); // all tx fifo
+ dfifo_flush_rx(dwc2);
+ dfifo_device_init(rhport);
+
+ // 5. Reset device address
+ dwc2->dcfg_bm.address = 0;
+
+ // Fixed both control EP0 size to 64 bytes
+ dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+ dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos);
+
+ xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+ xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+ if(dma_device_enabled(dwc2)) {
+ dma_setup_prepare(rhport);
+ } else {
+ dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+ }
+
+ dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+}
+
+static void handle_enum_done(uint8_t rhport) {
+ dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+ tusb_speed_t speed;
+ switch (dwc2->dsts_bm.enum_speed) {
+ case DCFG_SPEED_HIGH:
+ speed = TUSB_SPEED_HIGH;
+ break;
+
+ case DCFG_SPEED_LOW:
+ speed = TUSB_SPEED_LOW;
+ break;
+
+ case DCFG_SPEED_FULL_30_60MHZ:
+ case DCFG_SPEED_FULL_48MHZ:
+ default:
+ speed = TUSB_SPEED_FULL;
+ break;
+ }
+
+ // TODO must update GUSBCFG_TRDT according to link speed
+ dcd_event_bus_reset(rhport, speed, true);
+}
+
+#if 0
+TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) {
+ const char* str[] = {
+ "XFRC", "DIS", "AHBERR", "SETUP_DONE",
+ "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7",
+ "OPERR", "BNA", "RSV10", "ISODROP",
+ "BBLERR", "NAK", "NYET", "SETUP_RX"
+ };
+
+ for(uint32_t i=0; i<TU_ARRAY_SIZE(str); i++) {
+ if (doepint & TU_BIT(i)) {
+ TU_LOG1("%s ", str[i]);
+ }
+ }
+ TU_LOG1("\r\n");
+}
+#endif
+
+#if CFG_TUD_DWC2_SLAVE_ENABLE
// Process shared receive FIFO, this interrupt is only used in Slave mode
static void handle_rxflvl_irq(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
@@ -716,271 +738,275 @@ static void handle_rxflvl_irq(uint8_t rhport) {
// Pop control word off FIFO
const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
const uint8_t epnum = grxstsp_bm.ep_ch_num;
- const uint16_t byte_count = grxstsp_bm.byte_count;
- dwc2_epout_t* epout = &dwc2->epout[epnum];
+
+ dwc2_dep_t* epout = &dwc2->epout[epnum];
switch (grxstsp_bm.packet_status) {
- // Global OUT NAK: do nothing
- case GRXSTS_PKTSTS_GLOBALOUTNAK:
+ case GRXSTS_PKTSTS_GLOBAL_OUT_NAK:
+ // Global OUT NAK: do nothing
break;
- case GRXSTS_PKTSTS_SETUPRX:
+ case GRXSTS_PKTSTS_SETUP_RX:
// Setup packet received
- // We can receive up to three setup packets in succession, but only the last one is valid.
+ // We can receive up to three setup packets in succession, but only the last one is valid.
_setup_packet[0] = (*rx_fifo);
_setup_packet[1] = (*rx_fifo);
break;
- case GRXSTS_PKTSTS_SETUPDONE:
+ case GRXSTS_PKTSTS_SETUP_DONE:
// Setup packet done:
// After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq()
epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
break;
- case GRXSTS_PKTSTS_OUTRX: {
+ case GRXSTS_PKTSTS_RX_DATA: {
// Out packet received
+ const uint16_t byte_count = grxstsp_bm.byte_count;
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
- // Read packet off RxFIFO
- if (xfer->ff) {
- // Ring buffer
- tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
- } else {
- // Linear buffer
- dfifo_read_packet(dwc2, xfer->buffer, byte_count);
-
- // Increment pointer to xfer data
- xfer->buffer += byte_count;
- }
+ if (byte_count) {
+ // Read packet off RxFIFO
+ if (xfer->ff) {
+ tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count);
+ } else {
+ dfifo_read_packet(dwc2, xfer->buffer, byte_count);
+ xfer->buffer += byte_count;
+ }
- // short packet, minus remaining bytes (xfer_size)
- if (byte_count < xfer->max_size) {
- xfer->total_len -= epout->doeptsiz_bm.xfer_size;
- if (epnum == 0) {
- xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
- ep0_pending[TUSB_DIR_OUT] = 0;
+ // short packet, minus remaining bytes (xfer_size)
+ if (byte_count < xfer->max_size) {
+ xfer->total_len -= epout->tsiz_bm.xfer_size;
+ if (epnum == 0) {
+ xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
+ ep0_pending[TUSB_DIR_OUT] = 0;
+ }
}
}
break;
}
- case GRXSTS_PKTSTS_OUTDONE:
- /* Out packet done
- After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
- the specified OUT endpoint which will be handled by handle_epout_irq() */
+ case GRXSTS_PKTSTS_RX_COMPLETE:
+ // Out packet done
+ // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on
+ // the specified OUT endpoint which will be handled by handle_epout_irq()
break;
- default:
- TU_BREAKPOINT();
- break;
+ default: break;
}
}
-static void handle_epout_irq(uint8_t rhport) {
- dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
+ if (doepint_bm.setup_phase_done) {
+ dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ return;
+ }
- // DAINT for a given EP clears when DOEPINTx is cleared.
- // OEPINT will be cleared when DAINT's out bits are cleared.
- for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
- if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) {
- dwc2_epout_t* epout = &dwc2->epout[epnum];
- const uint32_t doepint = epout->doepint;
- TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, );
-
- // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently.
- if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) {
- if (doepint & DOEPINT_STSPHSRX) {
- // Status phase received for control write: In token received from Host
- epout->doepint = DOEPINT_STSPHSRX;
- }
+ // Normal OUT transfer complete
+ if (doepint_bm.xfer_complete) {
+ // only handle data skip if it is setup or status related
+ // Note: even though (xfer_complete + status_phase_rx) is for buffered DMA only, for STM32L47x (dwc2 v3.00a) they
+ // can is set when GRXSTS_PKTSTS_SETUP_RX is popped therefore they can bet set before/together with setup_phase_done
+ if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
- if (doepint & DOEPINT_STPKTRX) {
- // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively
- epout->doepint = DOEPINT_STPKTRX;
- }
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // EP0 can only handle one packet, Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
+ } else {
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
+ }
+ }
+}
- if (doepint & DOEPINT_SETUP) {
- epout->doepint = DOEPINT_SETUP;
+static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ dwc2_dep_t* epin = &dwc2->epin[epnum];
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
- if(dma_device_enabled(dwc2)) {
- dma_setup_prepare(rhport);
- }
+ if (diepint_bm.xfer_complete) {
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
+ // EP0 can only handle one packet. Schedule another packet to be transmitted.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
+ } else {
+ dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
+
+ // TX FIFO empty bit is read-only. It will only be cleared by hardware when written bytes is more than
+ // - 64 bytes or
+ // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
+ if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
+ const uint16_t remain_packets = epin->tsiz_bm.packet_count;
- dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ // Process every single packet (only whole packets can be written to fifo)
+ for (uint16_t i = 0; i < remain_packets; i++) {
+ const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size;
+ const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
+
+ // Check if dtxfsts has enough space available
+ if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
+ break;
}
- // OUT XFER complete
- if (doepint & DOEPINT_XFRC) {
- epout->doepint = DOEPINT_XFRC;
-
- // only handle data skip if it is setup or status related
- // Normal OUT transfer complete
- if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) {
- xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
- if(dma_device_enabled(dwc2)) {
- if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
- // EP0 can only handle one packet Schedule another packet to be received.
- edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
- } else {
- // Fix packet length
- uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
- xfer->total_len -= remain;
- // this is ZLP, so prepare EP0 for next setup
- if(epnum == 0 && xfer->total_len == 0) {
- dma_setup_prepare(rhport);
- }
-
- dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
- }
- } else {
- // EP0 can only handle one packet
- if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
- // Schedule another packet to be received.
- edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
- } else {
- dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
- }
- }
- }
+ // Push packet to Tx-FIFO
+ if (xfer->ff) {
+ volatile uint32_t* tx_fifo = dwc2->fifo[epnum];
+ tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*)(uintptr_t)tx_fifo, xact_bytes);
+ } else {
+ dfifo_write_packet(dwc2, epnum, xfer->buffer, xact_bytes);
+ xfer->buffer += xact_bytes;
}
}
+
+ // Turn off TXFE if all bytes are written.
+ if (epin->tsiz_bm.xfer_size == 0) {
+ dwc2->diepempmsk &= ~(1 << epnum);
+ }
}
}
+#endif
-static void handle_epin_irq(uint8_t rhport) {
+#if CFG_TUD_DWC2_DMA_ENABLE
+static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- const uint8_t ep_count = _dwc2_controller[rhport].ep_count;
- // DAINT for a given EP clears when DIEPINTx is cleared.
- // IEPINT will be cleared when DAINT's out bits are cleared.
- for (uint8_t n = 0; n < ep_count; n++) {
- if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) {
- // IN XFER complete (entire xfer).
- xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
- dwc2_epin_t* epin = &dwc2->epin[n];
-
- if (epin->diepint & DIEPINT_XFRC) {
- epin->diepint = DIEPINT_XFRC;
-
- // EP0 can only handle one packet
- if ((n == 0) && ep0_pending[TUSB_DIR_IN]) {
- // Schedule another packet to be transmitted.
- edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
- } else {
- if((n == 0) && dma_device_enabled(dwc2)) {
- dma_setup_prepare(rhport);
- }
- dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ if (doepint_bm.setup_phase_done) {
+ dma_setup_prepare(rhport);
+ dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ return;
+ }
+
+ // OUT XFER complete
+ if (doepint_bm.xfer_complete) {
+ // only handle data skip if it is setup or status related
+ // Normal OUT transfer complete
+ if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ // EP0 can only handle one packet Schedule another packet to be received.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
+ } else {
+ dwc2_dep_t* epout = &dwc2->epout[epnum];
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+ // determine actual received bytes
+ const uint16_t remain = epout->tsiz_bm.xfer_size;
+ xfer->total_len -= remain;
+
+ // this is ZLP, so prepare EP0 for next setup
+ // TODO use status phase rx
+ if(epnum == 0 && xfer->total_len == 0) {
+ dma_setup_prepare(rhport);
}
+
+ dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
+ }
+ }
+}
- // XFER FIFO empty
- if ((epin->diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) {
- // diepint's TXFE bit is read-only, software cannot clear it.
- // It will only be cleared by hardware when written bytes is more than
- // - 64 bytes or
- // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
- const uint16_t remain_packets = epin->dieptsiz_bm.packet_count;
-
- // Process every single packet (only whole packets can be written to fifo)
- for (uint16_t i = 0; i < remain_packets; i++) {
- const uint16_t remain_bytes = (uint16_t) epin->dieptsiz_bm.xfer_size;
-
- // Packet can not be larger than ep max size
- const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
-
- // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
- // EP has to be checked if the buffer can take another WHOLE packet
- if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) {
- break;
- }
+static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) {
+ xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
- // Push packet to Tx-FIFO
- if (xfer->ff) {
- volatile uint32_t* tx_fifo = dwc2->fifo[n];
- tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, xact_bytes);
- } else {
- dfifo_write_packet(dwc2, n, xfer->buffer, xact_bytes);
- xfer->buffer += xact_bytes;
- }
- }
+ if (diepint_bm.xfer_complete) {
+ if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
+ // EP0 can only handle one packet. Schedule another packet to be transmitted.
+ edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
+ } else {
+ if(epnum == 0) {
+ dma_setup_prepare(rhport);
+ }
+ dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+ }
+ }
+}
+#endif
- // Turn off TXFE if all bytes are written.
- if (epin->dieptsiz_bm.xfer_size == 0) {
- dwc2->diepempmsk &= ~(1 << n);
+static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
+ dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ const bool is_dma = dma_device_enabled(dwc2);
+ const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
+ const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos;
+ dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0];
+
+ // DAINT for a given EP clears when DEPINTx is cleared.
+ // EPINT will be cleared when DAINT bits are cleared.
+ for (uint8_t epnum = 0; epnum < ep_count; epnum++) {
+ if (dwc2->daint & TU_BIT(daint_offset + epnum)) {
+ dwc2_dep_t* epout = &ep_base[epnum];
+ union {
+ uint32_t value;
+ dwc2_diepint_t diepint_bm;
+ dwc2_doepint_t doepint_bm;
+ } intr;
+ intr.value = epout->intr;
+
+ epout->intr = intr.value; // Clear interrupt
+
+ if (is_dma) {
+ #if CFG_TUD_DWC2_DMA_ENABLE
+ if (dir == TUSB_DIR_IN) {
+ handle_epin_dma(rhport, epnum, intr.diepint_bm);
+ } else {
+ handle_epout_dma(rhport, epnum, intr.doepint_bm);
+ }
+ #endif
+ } else {
+ #if CFG_TUD_DWC2_SLAVE_ENABLE
+ if (dir == TUSB_DIR_IN) {
+ handle_epin_slave(rhport, epnum, intr.diepint_bm);
+ } else {
+ handle_epout_slave(rhport, epnum, intr.doepint_bm);
}
+ #endif
}
}
}
}
/* Interrupt Hierarchy
-
- DxEPINTn
- |
- DAINT.xEPn
- |
- GINTSTS: xEPInt
+ DIEPINT DIEPINT
+ \ /
+ \ /
+ DAINT
+ / \
+ / \
+ GINTSTS: OEPInt IEPInt | USBReset | EnumDone | USBSusp | WkUpInt | OTGInt | SOF | RXFLVL
Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
are combined to generate dedicated interrupt line for each endpoint.
*/
-
-
void dcd_int_handler(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- uint32_t const int_mask = dwc2->gintmsk;
- uint32_t const int_status = dwc2->gintsts & int_mask;
+ const uint32_t gintmask = dwc2->gintmsk;
+ const uint32_t gintsts = dwc2->gintsts & gintmask;
- if (int_status & GINTSTS_USBRST) {
+ if (gintsts & GINTSTS_USBRST) {
// USBRST is start of reset.
dwc2->gintsts = GINTSTS_USBRST;
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
_allocated_fifos = 1;
#endif
- bus_reset(rhport);
+ handle_bus_reset(rhport);
}
- if (int_status & GINTSTS_ENUMDNE) {
+ if (gintsts & GINTSTS_ENUMDNE) {
// ENUMDNE is the end of reset where speed of the link is detected
dwc2->gintsts = GINTSTS_ENUMDNE;
-
- tusb_speed_t speed;
- switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) {
- case DSTS_ENUMSPD_HS:
- speed = TUSB_SPEED_HIGH;
- break;
-
- case DSTS_ENUMSPD_LS:
- speed = TUSB_SPEED_LOW;
- break;
-
- case DSTS_ENUMSPD_FS_HSPHY:
- case DSTS_ENUMSPD_FS:
- default:
- speed = TUSB_SPEED_FULL;
- break;
- }
-
- // TODO must update GUSBCFG_TRDT according to link speed
-
- dcd_event_bus_reset(rhport, speed, true);
+ handle_enum_done(rhport);
}
- if (int_status & GINTSTS_USBSUSP) {
+ if (gintsts & GINTSTS_USBSUSP) {
dwc2->gintsts = GINTSTS_USBSUSP;
//dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
_allocated_fifos = 1;
#endif
}
- if (int_status & GINTSTS_WKUINT) {
+ if (gintsts & GINTSTS_WKUINT) {
dwc2->gintsts = GINTSTS_WKUINT;
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
}
@@ -988,13 +1014,13 @@ void dcd_int_handler(uint8_t rhport) {
// TODO check GINTSTS_DISCINT for disconnect detection
// if(int_status & GINTSTS_DISCINT)
- if (int_status & GINTSTS_OTGINT) {
+ if (gintsts & GINTSTS_OTGINT) {
// OTG INT bit is read-only
uint32_t const otg_int = dwc2->gotgint;
if (otg_int & GOTGINT_SEDET) {
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-#if defined(TUP_USBIP_DWC2_ESP32)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
_allocated_fifos = 1;
#endif
}
@@ -1002,7 +1028,7 @@ void dcd_int_handler(uint8_t rhport) {
dwc2->gotgint = otg_int;
}
- if(int_status & GINTSTS_SOF) {
+ if(gintsts & GINTSTS_SOF) {
dwc2->gintsts = GINTSTS_SOF;
const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
@@ -1014,8 +1040,9 @@ void dcd_int_handler(uint8_t rhport) {
dcd_event_sof(rhport, frame, true);
}
+#if CFG_TUD_DWC2_SLAVE_ENABLE
// RxFIFO non-empty interrupt handling.
- if (int_status & GINTSTS_RXFLVL) {
+ if (gintsts & GINTSTS_RXFLVL) {
// RXFLVL bit is read-only
dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading
@@ -1025,24 +1052,19 @@ void dcd_int_handler(uint8_t rhport) {
dwc2->gintmsk |= GINTMSK_RXFLVLM;
}
+#endif
// OUT endpoint interrupt handling.
- if (int_status & GINTSTS_OEPINT) {
+ if (gintsts & GINTSTS_OEPINT) {
// OEPINT is read-only, clear using DOEPINTn
- handle_epout_irq(rhport);
+ handle_ep_irq(rhport, TUSB_DIR_OUT);
}
// IN endpoint interrupt handling.
- if (int_status & GINTSTS_IEPINT) {
+ if (gintsts & GINTSTS_IEPINT) {
// IEPINT bit read-only, clear using DIEPINTn
- handle_epin_irq(rhport);
+ handle_ep_irq(rhport, TUSB_DIR_IN);
}
-
- // // Check for Incomplete isochronous IN transfer
- // if(int_status & GINTSTS_IISOIXFR) {
- // printf(" IISOIXFR!\r\n");
- //// TU_LOG(DWC2_DEBUG, " IISOIXFR!\r\n");
- // }
}
#if CFG_TUD_TEST_MODE
From 54e34b5d058c6b899330e875b12029781fb09743 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 25 Nov 2024 13:12:16 +0100
Subject: [PATCH 45/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 146 ++++++++++++++--------
1 file changed, 92 insertions(+), 54 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index da4709a72..da36a144f 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -31,6 +31,10 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
+#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
+#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
+#endif
+
// Debug level for DWC2
#define DWC2_DEBUG 2
@@ -46,9 +50,6 @@
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM
//--------------------------------------------------------------------+
-
-static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-
typedef struct {
uint8_t* buffer;
tu_fifo_t* ff;
@@ -60,19 +61,46 @@ typedef struct {
static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
-// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
-static uint16_t _dfifo_top; // top free location in DFIFO in words
+typedef struct {
+ // EP0 transfers are limited to 1 packet - larger sizes has to be split
+ uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
+ uint16_t dfifo_top; // top free location in DFIFO in words
+
+ // Number of IN endpoints active
+ uint8_t allocated_epin_count;
+
+ // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
+ bool sof_en;
+} dcd_data_t;
-// Number of IN endpoints active
-static uint8_t _allocated_ep_in_count;
+static dcd_data_t _dcd_data;
-// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
-static bool _sof_en;
+CFG_TUD_MEM_SECTION static struct {
+ TUD_EPBUF_DEF(setup_packet, 8);
+} _dcd_usbbuf;
//--------------------------------------------------------------------
// DMA
//--------------------------------------------------------------------
+#if CFG_TUD_MEM_DCACHE_ENABLE
+void dcd_dcache_clean(const void* addr, uint32_t data_size) {
+ if (addr && data_size) {
+ dwc2_dcache_clean(addr, data_size);
+ }
+}
+
+void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+ if (addr && data_size) {
+ dwc2_dcache_invalidate(addr, data_size);
+ }
+}
+
+void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+ if (addr && data_size) {
+ dwc2_dcache_clean_invalidate(addr, data_size);
+ }
+}
+#endif
TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
(void) dwc2;
@@ -91,7 +119,7 @@ static void dma_setup_prepare(uint8_t rhport) {
// Receive only 1 packet
dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
- dwc2->epout[0].doepdma = (uintptr_t)_setup_packet;
+ dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_packet;
dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
}
@@ -149,27 +177,27 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t larges
static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
- uint8_t const ep_count = dwc2_controller->ep_count;
- uint8_t const epnum = tu_edpt_number(ep_addr);
- uint8_t const dir = tu_edpt_dir(ep_addr);
+ const uint8_t ep_count = dwc2_controller->ep_count;
+ const uint8_t epnum = tu_edpt_number(ep_addr);
+ const uint8_t dir = tu_edpt_dir(ep_addr);
TU_ASSERT(epnum < ep_count);
uint16_t fifo_size = tu_div_ceil(packet_size, 4);
if (dir == TUSB_DIR_OUT) {
// Calculate required size of RX FIFO
- uint16_t const new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
+ const uint16_t new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
// If size_rx needs to be extended check if there is enough free space
if (dwc2->grxfsiz < new_sz) {
- TU_ASSERT(new_sz <= _dfifo_top);
+ TU_ASSERT(new_sz <= _dcd_data.dfifo_top);
dwc2->grxfsiz = new_sz; // Enlarge RX FIFO
}
} else {
// Check IN endpoints concurrently active limit
if(_dwc2_controller->ep_in_count) {
- TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
- _allocated_ep_in_count++;
+ TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count);
+ _dcd_data.allocated_epin_count++;
}
// If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
@@ -178,16 +206,16 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
}
// Check if free space is available
- TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz);
- _dfifo_top -= fifo_size;
- TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top);
+ TU_ASSERT(_dcd_data.dfifo_top >= fifo_size + dwc2->grxfsiz);
+ _dcd_data.dfifo_top -= fifo_size;
+ // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, dfifo_top);
// Both TXFD and TXSA are in unit of 32-bit words.
if (epnum == 0) {
- dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top;
+ dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
} else {
// DIEPTXF starts at FIFO #1.
- dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top;
+ dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
}
}
@@ -201,11 +229,11 @@ static void dfifo_device_init(uint8_t rhport) {
// Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
const bool is_dma = dma_device_enabled(dwc2);
- _dfifo_top = dwc2_controller->ep_fifo_size/4;
+ _dcd_data.dfifo_top = dwc2_controller->ep_fifo_size/4;
if (is_dma) {
- _dfifo_top -= 2 * dwc2_controller->ep_count;
+ _dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count;
}
- dwc2->gdfifocfg = (_dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dfifo_top;
+ dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
// Allocate FIFO for EP0 IN
dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
@@ -225,8 +253,8 @@ static uint8_t get_free_fifo(void) {
return 0;
}
#endif
-
-static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
+
+static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint_desc) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
@@ -328,8 +356,8 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
// EP0 is limited to one packet per xfer
if (epnum == 0) {
- total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
- ep0_pending[dir] -= total_bytes;
+ total_bytes = tu_min16(_dcd_data.ep0_pending[dir], xfer->max_size);
+ _dcd_data.ep0_pending[dir] -= total_bytes;
num_packets = 1;
} else {
total_bytes = xfer->total_len;
@@ -370,14 +398,18 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
const bool is_dma = dma_device_enabled(dwc2);
if(is_dma) {
+ if (dir == TUSB_DIR_IN && total_bytes != 0) {
+ dcd_dcache_clean(xfer->buffer, total_bytes);
+ }
dep->diepdma = (uintptr_t) xfer->buffer;
- }
-
- dep->diepctl = depctl.value; // enable endpoint
+ dep->diepctl = depctl.value; // enable endpoint
+ } else {
+ dep->diepctl = depctl.value; // enable endpoint
- // Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable
- if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) {
- dwc2->diepempmsk |= (1 << epnum);
+ // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
+ if (dir == TUSB_DIR_IN && total_bytes != 0) {
+ dwc2->diepempmsk |= (1 << epnum);
+ }
}
}
@@ -388,6 +420,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
(void) rh_init;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+ tu_memclr(&_dcd_data, sizeof(_dcd_data));
+
// Core Initialization
const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
const bool is_dma = dma_device_enabled(dwc2);
@@ -505,7 +539,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
(void) rhport;
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
- _sof_en = en;
+ _dcd_data.sof_en = en;
if (en) {
dwc2->gintsts = GINTSTS_SOF;
@@ -530,7 +564,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
- _allocated_ep_in_count = 1;
+ _dcd_data.allocated_epin_count = 1;
// Disable non-control interrupt
dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
@@ -578,7 +612,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
// EP0 can only handle one packet
if (epnum == 0) {
- ep0_pending[dir] = total_bytes;
+ _dcd_data.ep0_pending[dir] = total_bytes;
}
// Schedule packets to be sent within interrupt
@@ -644,8 +678,8 @@ static void handle_bus_reset(uint8_t rhport) {
tu_memclr(xfer_status, sizeof(xfer_status));
- _sof_en = false;
- _allocated_ep_in_count = 1;
+ _dcd_data.sof_en = false;
+ _dcd_data.allocated_epin_count = 1;
// 1. NAK for all OUT endpoints
for (uint8_t n = 0; n < ep_count; n++) {
@@ -746,12 +780,14 @@ static void handle_rxflvl_irq(uint8_t rhport) {
// Global OUT NAK: do nothing
break;
- case GRXSTS_PKTSTS_SETUP_RX:
+ case GRXSTS_PKTSTS_SETUP_RX: {
// Setup packet received
+ uint32_t* setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_packet;
// We can receive up to three setup packets in succession, but only the last one is valid.
- _setup_packet[0] = (*rx_fifo);
- _setup_packet[1] = (*rx_fifo);
+ setup[0] = (*rx_fifo);
+ setup[1] = (*rx_fifo);
break;
+ }
case GRXSTS_PKTSTS_SETUP_DONE:
// Setup packet done:
@@ -777,8 +813,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
if (byte_count < xfer->max_size) {
xfer->total_len -= epout->tsiz_bm.xfer_size;
if (epnum == 0) {
- xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
- ep0_pending[TUSB_DIR_OUT] = 0;
+ xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
+ _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
}
}
}
@@ -797,7 +833,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
if (doepint_bm.setup_phase_done) {
- dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
return;
}
@@ -809,7 +845,7 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe
if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
- if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
// EP0 can only handle one packet, Schedule another packet to be received.
edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
} else {
@@ -825,7 +861,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
if (diepint_bm.xfer_complete) {
- if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
+ if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
// EP0 can only handle one packet. Schedule another packet to be transmitted.
edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
} else {
@@ -873,7 +909,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
if (doepint_bm.setup_phase_done) {
dma_setup_prepare(rhport);
- dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
+ dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8);
+ dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true);
return;
}
@@ -882,7 +919,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
// only handle data skip if it is setup or status related
// Normal OUT transfer complete
if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
- if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
+ if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
// EP0 can only handle one packet Schedule another packet to be received.
edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
} else {
@@ -899,6 +936,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
dma_setup_prepare(rhport);
}
+ dcd_dcache_invalidate(xfer->buffer, xfer->total_len);
dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
}
@@ -909,7 +947,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
if (diepint_bm.xfer_complete) {
- if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
+ if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
// EP0 can only handle one packet. Schedule another packet to be transmitted.
edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
} else {
@@ -1016,7 +1054,7 @@ void dcd_int_handler(uint8_t rhport) {
if (gintsts & GINTSTS_OTGINT) {
// OTG INT bit is read-only
- uint32_t const otg_int = dwc2->gotgint;
+ const uint32_t otg_int = dwc2->gotgint;
if (otg_int & GOTGINT_SEDET) {
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
@@ -1033,7 +1071,7 @@ void dcd_int_handler(uint8_t rhport) {
const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
// Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection
- if (!_sof_en) {
+ if (!_dcd_data.sof_en) {
dwc2->gintmsk &= ~GINTMSK_SOFM;
}
From 94e3463c467483ce6222376b43c8bf11bee7d568 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 25 Nov 2024 15:03:51 +0100
Subject: [PATCH 46/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index da36a144f..8a2b585b4 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -83,22 +83,19 @@ CFG_TUD_MEM_SECTION static struct {
// DMA
//--------------------------------------------------------------------
#if CFG_TUD_MEM_DCACHE_ENABLE
-void dcd_dcache_clean(const void* addr, uint32_t data_size) {
- if (addr && data_size) {
- dwc2_dcache_clean(addr, data_size);
- }
+bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
+ TU_VERIFY(addr && data_size);
+ return dwc2_dcache_clean(addr, data_size);
}
-void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
- if (addr && data_size) {
- dwc2_dcache_invalidate(addr, data_size);
- }
+bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
+ TU_VERIFY(addr && data_size);
+ return dwc2_dcache_invalidate(addr, data_size);
}
-void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
- if (addr && data_size) {
- dwc2_dcache_clean_invalidate(addr, data_size);
- }
+bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
+ TU_VERIFY(addr && data_size);
+ return dwc2_dcache_clean_invalidate(addr, data_size);
}
#endif
From 10e5a4fb2abefe92273fa2136c9eed07589fd34c Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Mon, 27 Jan 2025 23:13:57 +0100
Subject: [PATCH 47/57] release/v3.0.x
---
tools/config.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/config.sh b/tools/config.sh
index 26c934cc6..ec96d7726 100755
--- a/tools/config.sh
+++ b/tools/config.sh
@@ -11,7 +11,7 @@ fi
# Arduino branch to use
if [ -z $AR_BRANCH ]; then
- AR_BRANCH="main"
+ AR_BRANCH="release/v3.0.x"
fi
if [ -z $IDF_TARGET ]; then
From f8e6b28b69feb20530e8bc44b41769f499de616f Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 28 Jan 2025 00:21:49 +0100
Subject: [PATCH 48/57] Update config.sh
---
tools/config.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/config.sh b/tools/config.sh
index ec96d7726..12ca68119 100755
--- a/tools/config.sh
+++ b/tools/config.sh
@@ -11,7 +11,7 @@ fi
# Arduino branch to use
if [ -z $AR_BRANCH ]; then
- AR_BRANCH="release/v3.0.x"
+ AR_BRANCH="release/v3.0.10"
fi
if [ -z $IDF_TARGET ]; then
From e1c5e47870a5d254eda36e7091c994c3b6c3898a Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Tue, 28 Jan 2025 00:23:44 +0100
Subject: [PATCH 49/57] Update dcd_dwc2.c
---
components/arduino_tinyusb/src/dcd_dwc2.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c
index 8a2b585b4..d6796641a 100644
--- a/components/arduino_tinyusb/src/dcd_dwc2.c
+++ b/components/arduino_tinyusb/src/dcd_dwc2.c
@@ -31,8 +31,8 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
-#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
-#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
+#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUD_DWC2_DMA_ENABLE)
+#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUD_DWC2_DMA_ENABLE to be enabled
#endif
// Debug level for DWC2
@@ -44,7 +44,7 @@
#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
#define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX
#else
- #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep)
+ #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1)
#endif
//--------------------------------------------------------------------+
@@ -192,8 +192,8 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
}
} else {
// Check IN endpoints concurrently active limit
- if(_dwc2_controller->ep_in_count) {
- TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count);
+ if(dwc2_controller->ep_in_count) {
+ TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count);
_dcd_data.allocated_epin_count++;
}
@@ -561,7 +561,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
- _dcd_data.allocated_epin_count = 1;
+ _dcd_data.allocated_epin_count = 0;
// Disable non-control interrupt
dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
@@ -641,10 +641,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
return true;
}
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
- edpt_disable(rhport, ep_addr, false);
-}
-
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
edpt_disable(rhport, ep_addr, true);
@@ -676,7 +672,7 @@ static void handle_bus_reset(uint8_t rhport) {
tu_memclr(xfer_status, sizeof(xfer_status));
_dcd_data.sof_en = false;
- _dcd_data.allocated_epin_count = 1;
+ _dcd_data.allocated_epin_count = 0;
// 1. NAK for all OUT endpoints
for (uint8_t n = 0; n < ep_count; n++) {
From ec4d717cc89097aad5daa0a7dd3f5fcb95546bd8 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 1 Feb 2025 18:43:21 +0100
Subject: [PATCH 50/57] Update builds.json
---
configs/builds.json | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/configs/builds.json b/configs/builds.json
index 02695519c..acd1791ea 100644
--- a/configs/builds.json
+++ b/configs/builds.json
@@ -36,6 +36,12 @@
"out":"lib/libesp_hw_support.a",
"targets":["esp32s3"]
},
+ {
+ "file":"libesp_lcd.a",
+ "src":"build/esp-idf/esp_lcd/libesp_lcd.a",
+ "out":"lib/libesp_lcd.a",
+ "targets":["esp32s3"]
+ },
{
"file":"sections.ld",
"src":"build/esp-idf/esp_system/ld/sections.ld",
From c144ffcf4d89adc78d5f8fd15fa232806397d087 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 1 Feb 2025 18:46:45 +0100
Subject: [PATCH 51/57] Update builds.json
---
configs/builds.json | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/configs/builds.json b/configs/builds.json
index acd1791ea..46e1c6cdf 100644
--- a/configs/builds.json
+++ b/configs/builds.json
@@ -137,25 +137,17 @@
{
"target": "esp32s3",
"features":[],
- "idf_libs":["qio","80m","opi_ram"],
+ "idf_libs":["qio","80m","qio_ram"],
"bootloaders":[
["qio","120m","qio_ram"],
- ["qio","120m","opi_ram"],
["qio","80m","qio_ram"],
- ["qio","80m","opi_ram"],
- ["opi","120m","qio_ram"],
- ["opi","120m","opi_ram"],
- ["opi","80m","qio_ram"],
+ ["dio","80m","qio_ram"],
["opi","80m","opi_ram"]
],
"mem_variants":[
- ["qio","120m","qio_ram"],
- ["qio","120m","opi_ram"],
- ["qio","80m","qio_ram"],
- ["qio","80m","opi_ram"],
- ["opi","120m","qio_ram"],
- ["opi","120m","opi_ram"],
- ["opi","80m","qio_ram"],
+ ["qio","80m","opi_ram"],
+ ["dio","80m","qio_ram"],
+ ["dio","80m","opi_ram"],
["opi","80m","opi_ram"]
]
}
From c8177cfa1969f3d2b0df697138b07e7494eb9e1b Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 10:41:29 +0100
Subject: [PATCH 52/57] Update tusb_config.h
---
components/arduino_tinyusb/include/tusb_config.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h
index 458c78cf1..7802bea8f 100755
--- a/components/arduino_tinyusb/include/tusb_config.h
+++ b/components/arduino_tinyusb/include/tusb_config.h
@@ -115,7 +115,11 @@ extern "C" {
#define CFG_TUD_ENDOINT0_SIZE 64
// Enabled Drivers
-#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_ENABLED
+#ifdef CONFIG_TINYUSB_CDC_MAX_PORTS
+#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_MAX_PORTS
+#else
+#define CFG_TUD_CDC 0
+#endif
#define CFG_TUD_MSC CONFIG_TINYUSB_MSC_ENABLED
#define CFG_TUD_HID CONFIG_TINYUSB_HID_ENABLED
#define CFG_TUD_MIDI CONFIG_TINYUSB_MIDI_ENABLED
From 524b5c229cdbae4bdc665c05b785401588e12be3 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 10:49:00 +0100
Subject: [PATCH 53/57] Update config.sh
---
tools/config.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/config.sh b/tools/config.sh
index 12ca68119..ec96d7726 100755
--- a/tools/config.sh
+++ b/tools/config.sh
@@ -11,7 +11,7 @@ fi
# Arduino branch to use
if [ -z $AR_BRANCH ]; then
- AR_BRANCH="release/v3.0.10"
+ AR_BRANCH="release/v3.0.x"
fi
if [ -z $IDF_TARGET ]; then
From 739ac195456c337201fece36b0d406f2bd5e97d6 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 11:33:08 +0100
Subject: [PATCH 54/57] revert change
---
components/arduino_tinyusb/include/tusb_config.h | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h
index 7802bea8f..458c78cf1 100755
--- a/components/arduino_tinyusb/include/tusb_config.h
+++ b/components/arduino_tinyusb/include/tusb_config.h
@@ -115,11 +115,7 @@ extern "C" {
#define CFG_TUD_ENDOINT0_SIZE 64
// Enabled Drivers
-#ifdef CONFIG_TINYUSB_CDC_MAX_PORTS
-#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_MAX_PORTS
-#else
-#define CFG_TUD_CDC 0
-#endif
+#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_ENABLED
#define CFG_TUD_MSC CONFIG_TINYUSB_MSC_ENABLED
#define CFG_TUD_HID CONFIG_TINYUSB_HID_ENABLED
#define CFG_TUD_MIDI CONFIG_TINYUSB_MIDI_ENABLED
From b4dd8cad874c3a306eb9376c8d33af5ffb3c2300 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 13:16:23 +0100
Subject: [PATCH 55/57] feat(cdc): Add support for two CDC ports at once
---
components/arduino_tinyusb/include/tusb_config.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h
index 458c78cf1..7802bea8f 100755
--- a/components/arduino_tinyusb/include/tusb_config.h
+++ b/components/arduino_tinyusb/include/tusb_config.h
@@ -115,7 +115,11 @@ extern "C" {
#define CFG_TUD_ENDOINT0_SIZE 64
// Enabled Drivers
-#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_ENABLED
+#ifdef CONFIG_TINYUSB_CDC_MAX_PORTS
+#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_MAX_PORTS
+#else
+#define CFG_TUD_CDC 0
+#endif
#define CFG_TUD_MSC CONFIG_TINYUSB_MSC_ENABLED
#define CFG_TUD_HID CONFIG_TINYUSB_HID_ENABLED
#define CFG_TUD_MIDI CONFIG_TINYUSB_MIDI_ENABLED
From 7100b123f1a7ada19d37a9d5a3eae137e5b7c642 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 13:19:02 +0100
Subject: [PATCH 56/57] Update Kconfig.projbuild
---
components/arduino_tinyusb/Kconfig.projbuild | 36 ++++++++++++++------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/components/arduino_tinyusb/Kconfig.projbuild b/components/arduino_tinyusb/Kconfig.projbuild
index 1db30506f..f0a1b4dc6 100755
--- a/components/arduino_tinyusb/Kconfig.projbuild
+++ b/components/arduino_tinyusb/Kconfig.projbuild
@@ -4,7 +4,7 @@ menu "Arduino TinyUSB"
config TINYUSB_ENABLED
bool "Enable TinyUSB driver"
default y
- depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
select FREERTOS_SUPPORT_STATIC_ALLOCATION
select FREERTOS_USE_AUTHENTIC_INCLUDE_PATHS
help
@@ -28,18 +28,28 @@ menu "Arduino TinyUSB"
config TINYUSB_CDC_RX_BUFSIZE
int "CDC FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of RX
config TINYUSB_CDC_TX_BUFSIZE
int "CDC FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_CDC_ENABLED
help
CDC FIFO size of TX
+ config TINYUSB_CDC_MAX_PORTS
+ int "Maximum enabled CDC ports"
+ range 1 2
+ default 1
+ depends on TINYUSB_CDC_ENABLED
+ help
+ Maximum enabled CDC ports
+
endmenu
menu "Mass Storage (MSC) driver"
@@ -86,7 +96,8 @@ menu "Arduino TinyUSB"
config TINYUSB_HID_BUFSIZE
int "HID Buffer size"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_HID_ENABLED
help
HID Buffer size. Should be sufficient to hold ID (if any) + Data
@@ -111,14 +122,16 @@ menu "Arduino TinyUSB"
config TINYUSB_MIDI_RX_BUFSIZE
int "MIDI FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of RX
config TINYUSB_MIDI_TX_BUFSIZE
int "MIDI FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_MIDI_ENABLED
help
MIDI FIFO size of TX
@@ -143,8 +156,9 @@ menu "Arduino TinyUSB"
config TINYUSB_VIDEO_STREAMING_BUFSIZE
int "VIDEO streaming endpoint size"
- range 0 64
- default 64
+ range 0 512
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VIDEO_ENABLED
help
VIDEO streaming endpoint size
@@ -219,14 +233,16 @@ menu "Arduino TinyUSB"
config TINYUSB_VENDOR_RX_BUFSIZE
int "VENDOR FIFO size of RX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of RX
config TINYUSB_VENDOR_TX_BUFSIZE
int "VENDOR FIFO size of TX"
- default 64
+ default 64 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+ default 512 if IDF_TARGET_ESP32P4
depends on TINYUSB_VENDOR_ENABLED
help
VENDOR FIFO size of TX
From 7cf6fdcf1a6cfdd08b7697c4900dd651681fdac7 Mon Sep 17 00:00:00 2001
From: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Date: Sat, 22 Mar 2025 13:20:10 +0100
Subject: [PATCH 57/57] Update defconfig.common
---
configs/defconfig.common | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/defconfig.common b/configs/defconfig.common
index 5fc910b8a..8874d6ba0 100644
--- a/configs/defconfig.common
+++ b/configs/defconfig.common
@@ -109,6 +109,9 @@ CONFIG_LWIP_UDP_RECVMBOX_SIZE=64
CONFIG_NEWLIB_NANO_FORMAT=y
# CONFIG_DAC_DMA_AUTO_16BIT_ALIGN is not set
+#TinyUSB Config
+CONFIG_TINYUSB_CDC_MAX_PORTS=2
+
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y
CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y
CONFIG_MBEDTLS_TLS_DISABLED=y