updates

* keep folder flags

* Use 80Mhz for PSRAM too

* Use 40Mhz for PSRAM too

* lib lcd needs to be specific for S3

* esp32-p4: Enable optimizations for RGB LCD

* Update Kconfig.projbuild

* Update tusb_config.h

* CONFIG_TINYUSB_CDC_MAX_PORTS=2

* AR_BRANCH="release/v3.1.x"

* fix(TinyUSB): USB HUB Subport Added, FIFO sizes(Bias Periodic OUT)

* Update defconfig.opi_ram

* set s3 cache size to 16kb

* CONFIG_HEAP_POISONING_DISABLED=y

* rm "-DNDEBUG" from compile DEFINES

* Update prepare-ci.sh

* Update dcd_dwc2.c

* Update dcd_dwc2.patch

* remove duplicate entry

* CONFIG_MBEDTLS_SHA1_C=y

* Fix compile error sha1

* better IDF commit checkout handling

* Update install-esp-idf.sh

Author: Jason2866

components/arduino_tinyusb/Kconfig.projbuild

@@ -42,6 +42,14 @@ menu "Arduino TinyUSB"
             help
                 CDC FIFO size of TX
 
+        config TINYUSB_CDC_MAX_PORTS
+            int "Maximum enabled CDC ports"
+            range 1 2
+            default 1
+            depends on TINYUSB_CDC_ENABLED
+            help
+                Maximum enabled CDC ports
+
     endmenu
 
     menu "Mass Storage (MSC) driver"

components/arduino_tinyusb/include/tusb_config.h

@@ -115,7 +115,11 @@ extern "C" {
 #define CFG_TUD_ENDOINT0_SIZE 		64
 
 // Enabled Drivers
-#define CFG_TUD_CDC 				CONFIG_TINYUSB_CDC_ENABLED
+#ifdef CONFIG_TINYUSB_CDC_MAX_PORTS
+#define CFG_TUD_CDC 				CONFIG_TINYUSB_CDC_MAX_PORTS
+#else
+#define CFG_TUD_CDC 				0
+#endif
 #define CFG_TUD_MSC 				CONFIG_TINYUSB_MSC_ENABLED
 #define CFG_TUD_HID 				CONFIG_TINYUSB_HID_ENABLED
 #define CFG_TUD_MIDI 				CONFIG_TINYUSB_MIDI_ENABLED

components/arduino_tinyusb/patches/dcd_dwc2.patch

@@ -19,11 +19,11 @@
    dwc2_regs_t* dwc2 = DWC2_REG(rhport);
    const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
 @@ -266,7 +277,18 @@
-     depctl.bm.set_data0_iso_even = 1;
+     depctl.set_data0_iso_even = 1;
    }
    if (dir == TUSB_DIR_IN) {
--    depctl.bm.tx_fifo_num = epnum;
-+    //depctl.bm.tx_fifo_num = epnum;
+-    depctl.tx_fifo_num = epnum;
++    //depctl.tx_fifo_num = epnum;
 +    uint8_t fifo_num = epnum;
 +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 +    // Special Case for EP5, which is used by CDC but not actually called by the driver
@@ -34,7 +34,7 @@
 +      fifo_num = get_free_fifo();
 +    }
 +#endif
-+    depctl.bm.tx_fifo_num = fifo_num;
++    depctl.tx_fifo_num = fifo_num;
    }
 
    dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];

components/arduino_tinyusb/src/dcd_dwc2.c

@@ -41,12 +41,6 @@
 #include "device/dcd.h"
 #include "dwc2_common.h"
 
-#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  #define DWC2_EP_COUNT(_dwc2)   DWC2_EP_MAX
-#else
-  #define DWC2_EP_COUNT(_dwc2)  ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1)
-#endif
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -79,6 +73,16 @@ CFG_TUD_MEM_SECTION static struct {
   TUD_EPBUF_DEF(setup_packet, 8);
 } _dcd_usbbuf;
 
+TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
+  #if TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  return DWC2_EP_MAX;
+  #else
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  return ghwcfg2.num_dev_ep + 1;
+  #endif
+}
+
+
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
@@ -102,7 +106,8 @@ bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
 TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
   (void) dwc2;
   // Internal DMA only
-  return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  return CFG_TUD_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
 }
 
 static void dma_setup_prepare(uint8_t rhport) {
@@ -261,20 +266,15 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint
   xfer->interval = p_endpoint_desc->bInterval;
 
   // Endpoint control
-  union {
-    uint32_t value;
-    dwc2_depctl_t bm;
-  } depctl;
-  depctl.value = 0;
-
-  depctl.bm.mps = xfer->max_size;
-  depctl.bm.active = 1;
-  depctl.bm.type = p_endpoint_desc->bmAttributes.xfer;
+  dwc2_depctl_t depctl = {.value = 0};
+  depctl.mps = xfer->max_size;
+  depctl.active = 1;
+  depctl.type = p_endpoint_desc->bmAttributes.xfer;
   if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) {
-    depctl.bm.set_data0_iso_even = 1;
+    depctl.set_data0_iso_even = 1;
   }
   if (dir == TUSB_DIR_IN) {
-    //depctl.bm.tx_fifo_num = epnum;
+    //depctl.tx_fifo_num = epnum;
     uint8_t fifo_num = epnum;
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
     // Special Case for EP5, which is used by CDC but not actually called by the driver
@@ -285,7 +285,7 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint
       fifo_num = get_free_fifo();
     }
 #endif
-    depctl.bm.tx_fifo_num = fifo_num;
+    depctl.tx_fifo_num = fifo_num;
   }
 
   dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum];
@@ -365,31 +365,22 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
   }
 
   // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC.
-  union {
-    uint32_t value;
-    dwc2_ep_tsize_t bm;
-  } deptsiz;
-  deptsiz.value = 0;
-  deptsiz.bm.xfer_size =  total_bytes;
-  deptsiz.bm.packet_count = num_packets;
-
+  dwc2_ep_tsize_t deptsiz = {.value = 0};
+  deptsiz.xfer_size = total_bytes;
+  deptsiz.packet_count = num_packets;
   dep->tsiz = deptsiz.value;
 
   // control
-  union {
-    dwc2_depctl_t bm;
-    uint32_t value;
-  } depctl;
-  depctl.value = dep->ctl;
-
-  depctl.bm.clear_nak = 1;
-  depctl.bm.enable = 1;
-  if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
-    const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u);
+  dwc2_depctl_t depctl = {.value = dep->ctl};
+  depctl.clear_nak = 1;
+  depctl.enable = 1;
+  if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) {
+    const dwc2_dsts_t dsts = {.value = dwc2->dsts};
+    const uint32_t odd_now = dsts.frame_number & 1u;
     if (odd_now) {
-      depctl.bm.set_data0_iso_even = 1;
+      depctl.set_data0_iso_even = 1;
     } else {
-      depctl.bm.set_data1_iso_odd = 1;
+      depctl.set_data1_iso_odd = 1;
     }
   }
 
@@ -432,7 +423,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
 
     // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
     // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
-    if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
+    const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+    if (ghwcfg2.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
       dcfg |= DCFG_XCVRDLY;
     }
   } else {
@@ -667,7 +659,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
 // 7.4.1 Initialization on USB Reset
 static void handle_bus_reset(uint8_t rhport) {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
-  const uint8_t ep_count =  DWC2_EP_COUNT(dwc2);
+  const uint8_t ep_count =  dwc2_ep_count(dwc2);
 
   tu_memclr(xfer_status, sizeof(xfer_status));
 
@@ -697,7 +689,9 @@ static void handle_bus_reset(uint8_t rhport) {
   dfifo_device_init(rhport);
 
   // 5. Reset device address
-  dwc2->dcfg_bm.address = 0;
+  dwc2_dcfg_t dcfg = {.value = dwc2->dcfg};
+  dcfg.address = 0;
+  dwc2->dcfg = dcfg.value;
 
   // Fixed both control EP0 size to 64 bytes
   dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -717,8 +711,9 @@ static void handle_bus_reset(uint8_t rhport) {
 
 static void handle_enum_done(uint8_t rhport) {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+  const dwc2_dsts_t dsts = {.value = dwc2->dsts};
   tusb_speed_t speed;
-  switch (dwc2->dsts_bm.enum_speed) {
+  switch (dsts.enum_speed) {
     case DCFG_SPEED_HIGH:
       speed = TUSB_SPEED_HIGH;
     break;
@@ -763,12 +758,12 @@ static void handle_rxflvl_irq(uint8_t rhport) {
   const volatile uint32_t* rx_fifo = dwc2->fifo[0];
 
   // Pop control word off FIFO
-  const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm;
-  const uint8_t epnum = grxstsp_bm.ep_ch_num;
+  const dwc2_grxstsp_t grxstsp = {.value = dwc2->grxstsp};
+  const uint8_t epnum = grxstsp.ep_ch_num;
 
   dwc2_dep_t* epout = &dwc2->epout[epnum];
 
-  switch (grxstsp_bm.packet_status) {
+  switch (grxstsp.packet_status) {
     case GRXSTS_PKTSTS_GLOBAL_OUT_NAK:
       // Global OUT NAK: do nothing
       break;
@@ -790,7 +785,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
 
     case GRXSTS_PKTSTS_RX_DATA: {
       // Out packet received
-      const uint16_t byte_count = grxstsp_bm.byte_count;
+      const uint16_t byte_count = grxstsp.byte_count;
       xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
       if (byte_count) {
@@ -804,7 +799,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
 
         // short packet, minus remaining bytes (xfer_size)
         if (byte_count < xfer->max_size) {
-          xfer->total_len -= epout->tsiz_bm.xfer_size;
+          const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
+          xfer->total_len -= tsiz.xfer_size;
           if (epnum == 0) {
             xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
             _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
@@ -866,11 +862,13 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
   // - 64 bytes or
   // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL)
   if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) {
-    const uint16_t remain_packets = epin->tsiz_bm.packet_count;
+    dwc2_ep_tsize_t tsiz = {.value = epin->tsiz};
+    const uint16_t remain_packets = tsiz.packet_count;
 
     // Process every single packet (only whole packets can be written to fifo)
     for (uint16_t i = 0; i < remain_packets; i++) {
-      const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size;
+      tsiz.value = epin->tsiz;
+      const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size;
       const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size);
 
       // Check if dtxfsts has enough space available
@@ -889,7 +887,8 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
     }
 
     // Turn off TXFE if all bytes are written.
-    if (epin->tsiz_bm.xfer_size == 0) {
+    tsiz.value = epin->tsiz;
+    if (tsiz.xfer_size == 0) {
       dwc2->diepempmsk &= ~(1 << epnum);
     }
   }
@@ -920,7 +919,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
         xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
         // determine actual received bytes
-        const uint16_t remain = epout->tsiz_bm.xfer_size;
+        const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz};
+        const uint16_t remain = tsiz.xfer_size;
         xfer->total_len -= remain;
 
         // this is ZLP, so prepare EP0 for next setup
@@ -956,7 +956,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
 static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const bool is_dma = dma_device_enabled(dwc2);
-  const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
+  const uint8_t ep_count = dwc2_ep_count(dwc2);
   const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos;
   dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0];
 

configs/builds.json

@@ -36,6 +36,12 @@
 			"out":"lib/libesp_hw_support.a",
 			"targets":["esp32s3"]
 		},
+		{
+			"file":"libesp_lcd.a",
+			"src":"build/esp-idf/esp_lcd/libesp_lcd.a",
+			"out":"lib/libesp_lcd.a",
+			"targets":["esp32s3"]
+		},
 		{
 			"file":"sections.ld",
 			"src":"build/esp-idf/esp_system/ld/sections.ld",

configs/defconfig.40m

@@ -1 +1,3 @@
 CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED=40

configs/defconfig.80m

@@ -1 +1,3 @@
 CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_SPIRAM_SPEED_80M=y
+CONFIG_SPIRAM_SPEED=80

configs/defconfig.common

@@ -78,7 +78,7 @@ CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304
 CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
 CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y
 CONFIG_HAL_ASSERTION_DISABLE=y
-CONFIG_HEAP_POISONING_LIGHT=y
+CONFIG_HEAP_POISONING_DISABLED=y
 CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024
 CONFIG_HTTPD_WS_SUPPORT=y
 CONFIG_LOG_DEFAULT_LEVEL_NONE=y
@@ -158,7 +158,7 @@ CONFIG_MBEDTLS_ROM_MD5=y
 CONFIG_MBEDTLS_HARDWARE_ECC=y
 CONFIG_MBEDTLS_HARDWARE_AES=y
 CONFIG_MBEDTLS_HARDWARE_MPI=y
-CONFIG_MBEDTLS_HARDWARE_SHA=y
+# CONFIG_MBEDTLS_HARDWARE_SHA is not set
 # CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK is not set
 # CONFIG_MBEDTLS_HAVE_TIME is not set
 # CONFIG_MBEDTLS_ECDSA_DETERMINISTIC is not set
@@ -178,6 +178,8 @@ CONFIG_MBEDTLS_ECP_C=y
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
+# CONFIG_MBEDTLS_SHA1_C is not set
+# CONFIG_MBEDTLS_SHA1_ALT is not set
 # CONFIG_MBEDTLS_DHM_C is not set
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
 # CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set
@@ -227,6 +229,14 @@ CONFIG_LITTLEFS_MAX_PARTITIONS=2
 CONFIG_LITTLEFS_MULTIVERSION=y
 CONFIG_LITTLEFS_DISK_VERSION_2_0=y
 
+#
+# TinyUSB Config
+#
+CONFIG_TINYUSB_CDC_MAX_PORTS=2
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
+CONFIG_USB_HOST_HUB_MULTI_LEVEL=y
+CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT=y
+
 #
 # Disable Cameras not used
 #

configs/defconfig.esp32

@@ -33,7 +33,6 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_OCCUPY_HSPI_HOST=y
-CONFIG_ULP_COPROC_ENABLED=y
 # CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 is not set
 # CONFIG_UNITY_ENABLE_FLOAT is not set
 # CONFIG_UNITY_ENABLE_DOUBLE is not set

configs/defconfig.esp32p4

@@ -20,6 +20,10 @@ CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=3120
 CONFIG_CACHE_L2_CACHE_256KB=y
 CONFIG_CACHE_L2_CACHE_LINE_128B=y
 
+# RGB Display Optimizations
+CONFIG_LCD_RGB_ISR_IRAM_SAFE=y
+CONFIG_LCD_RGB_RESTART_IN_VSYNC=y
+
 CONFIG_SLAVE_IDF_TARGET_ESP32C6=y
 CONFIG_ESP_SDIO_BUS_WIDTH=4
 CONFIG_ESP_SDIO_CLOCK_FREQ_KHZ=40000

configs/defconfig.esp32s3

@@ -7,6 +7,8 @@ CONFIG_ULP_COPROC_RESERVE_MEM=4096
 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y
+CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
+CONFIG_ESP32S3_DATA_CACHE_16KB=y
 CONFIG_RTC_CLK_CAL_CYCLES=576
 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO=y
 # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set

configs/defconfig.opi_ram

@@ -7,5 +7,6 @@ CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
 # I2S_ISR_IRAM_SAFE has to be set!! Done in common config
 CONFIG_GDMA_ISR_IRAM_SAFE=y
 # Enable the XIP-PSRAM feature, so the ext-mem cache won't be disabled when SPI1 is operating the main flash
+CONFIG_SPIRAM_XIP_FROM_PSRAM=y
 CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
 CONFIG_SPIRAM_RODATA=y

tools/config.sh

@@ -11,7 +11,7 @@ fi
 
 # Arduino branch to use
 if [ -z $AR_BRANCH ]; then
-    AR_BRANCH="main"
+    AR_BRANCH="release/v3.1.x"
 fi
 
 if [ -z $IDF_TARGET ]; then