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GrumpyOldPizzaGrumpyOldPizza
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add RCC/SM tracking for SRAM1/SRAM2; remove RCC/SM tracking for EXTI/GPIO
1 parent a9f9fdd commit 9ae87f3

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8 files changed

+103
-73
lines changed

8 files changed

+103
-73
lines changed

‎system/libstm32l4_dragonfly/armv7m.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,11 @@
3737

3838
static inline void armv7m_core_yield(void)
3939
{
40-
__asm__ volatile ("wfe");
40+
/* This odd aequence seems to be required for at least STM32L4. Traces on the logic analyzer
41+
* showed that after blocking on wfe, then the subsequent wfe would not block. The only WAR
42+
* is to explicitly clear the EVENT flag via the SEV; WFE sequence.
43+
*/
44+
__asm__ volatile ("wfe; sev; wfe");
4145
}
4246

4347
extern int armv7m_core_priority(void);

‎system/libstm32l4_dragonfly/stm32l4_dma.c

Lines changed: 30 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -76,26 +76,50 @@ static const IRQn_Type stm32l4_dma_interrupt_table[16] = {
7676
typedef struct _stm32l4_dma_driver_t {
7777
stm32l4_dma_t *instances[16];
7878
volatile uint32_t mask;
79+
volatile uint32_t sram1;
80+
volatile uint32_t sram2;
7981
volatile uint32_t flash;
8082
volatile uint32_t dma1;
8183
volatile uint32_t dma2;
8284
} stm32l4_dma_driver_t;
8385

8486
static stm32l4_dma_driver_t stm32l4_dma_driver;
8587

86-
static inline void stm32l4_dma_track(uint32_t channel, uint32_t address)
88+
static void stm32l4_dma_track(uint32_t channel, uint32_t address)
8789
{
88-
if (address < 0x10000000)
90+
if (address < 0x40000000)
8991
{
90-
stm32l4_system_periph_cond_wake(SYSTEM_PERIPH_FLASH, &stm32l4_dma_driver.flash, (1ul << channel));
92+
if (address >= 0x20000000)
93+
{
94+
stm32l4_system_periph_cond_wake(SYSTEM_PERIPH_SRAM1, &stm32l4_dma_driver.sram1, (1ul << channel));
95+
}
96+
else if (address >= 0x10000000)
97+
{
98+
stm32l4_system_periph_cond_wake(SYSTEM_PERIPH_SRAM2, &stm32l4_dma_driver.sram2, (1ul << channel));
99+
}
100+
else
101+
{
102+
stm32l4_system_periph_cond_wake(SYSTEM_PERIPH_FLASH, &stm32l4_dma_driver.flash, (1ul << channel));
103+
}
91104
}
92105
}
93106

94-
static inline void stm32l4_dma_untrack(uint32_t channel, uint32_t address)
107+
static void stm32l4_dma_untrack(uint32_t channel, uint32_t address)
95108
{
96-
if (address < 0x10000000)
109+
if (address < 0x40000000)
97110
{
98-
stm32l4_system_periph_cond_sleep(SYSTEM_PERIPH_FLASH, &stm32l4_dma_driver.flash, (1ul << channel));
111+
if (address >= 0x20000000)
112+
{
113+
stm32l4_system_periph_cond_sleep(SYSTEM_PERIPH_SRAM1, &stm32l4_dma_driver.sram1, (1ul << channel));
114+
}
115+
else if (address >= 0x10000000)
116+
{
117+
stm32l4_system_periph_cond_sleep(SYSTEM_PERIPH_SRAM2, &stm32l4_dma_driver.sram2, (1ul << channel));
118+
}
119+
else
120+
{
121+
stm32l4_system_periph_cond_sleep(SYSTEM_PERIPH_FLASH, &stm32l4_dma_driver.flash, (1ul << channel));
122+
}
99123
}
100124
}
101125

‎system/libstm32l4_dragonfly/stm32l4_exti.c

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@
3636

3737
#include "armv7m.h"
3838

39-
4039
typedef struct _stm32l4_exti_driver_t {
4140
stm32l4_exti_t *instances[1];
4241
} stm32l4_exti_driver_t;
@@ -105,20 +104,13 @@ bool stm32l4_exti_enable(stm32l4_exti_t *exti)
105104

106105
bool stm32l4_exti_disable(stm32l4_exti_t *exti)
107106
{
108-
unsigned int group;
109-
110107
if (exti->state != EXTI_STATE_READY)
111108
{
112109
return false;
113110
}
114111

115112
armv7m_atomic_and(&EXTI->IMR1, ~0x0000ffff);
116113

117-
for (group = 0; group < 8; group++)
118-
{
119-
stm32l4_system_periph_cond_sleep((SYSTEM_PERIPH_GPIOA + group), &exti->gpio[group], ~0ul);
120-
}
121-
122114
NVIC_DisableIRQ(EXTI15_10_IRQn);
123115
NVIC_DisableIRQ(EXTI9_5_IRQn);
124116
NVIC_DisableIRQ(EXTI4_IRQn);
@@ -175,14 +167,6 @@ bool stm32l4_exti_notify(stm32l4_exti_t *exti, uint16_t pin, uint32_t control, s
175167
mask = 1ul << index;
176168

177169
armv7m_atomic_and(&EXTI->IMR1, ~mask);
178-
179-
if (exti->enables & mask)
180-
{
181-
o_group = (SYSCFG->EXTICR[index >> 2] >> ((index & 3) << 2)) & 15;
182-
183-
stm32l4_system_periph_cond_sleep((SYSTEM_PERIPH_GPIOA + o_group), &exti->gpio[o_group], (1ul << index));
184-
}
185-
186170
armv7m_atomic_and(&exti->enables, ~mask);
187171

188172
exti->channels[index].callback = callback;
@@ -216,8 +200,6 @@ bool stm32l4_exti_notify(stm32l4_exti_t *exti, uint16_t pin, uint32_t control, s
216200
{
217201
armv7m_atomic_or(&EXTI->IMR1, mask);
218202
}
219-
220-
stm32l4_system_periph_cond_wake((SYSTEM_PERIPH_GPIOA + group), &exti->gpio[group], (1ul << index));
221203
}
222204

223205
return true;

‎system/libstm32l4_dragonfly/stm32l4_exti.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,6 @@ typedef struct _stm32l4_exti_t {
5757
uint8_t priority;
5858
uint32_t enables;
5959
uint32_t mask;
60-
volatile uint32_t gpio[8];
6160
struct {
6261
stm32l4_exti_callback_t callback;
6362
void* context;

‎system/libstm32l4_dragonfly/stm32l4_system.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
* WITH THE SOFTWARE.
2727
*/
2828

29-
#include "stm32l4xx.h"
29+
#include <stdlib.h>
3030

3131
#include "armv7m.h"
3232

@@ -46,6 +46,8 @@ static stm32l4_system_device_t stm32l4_system_device;
4646

4747
static volatile uint32_t * const stm32l4_system_xlate_RSTR[] = {
4848
&RCC->AHB1RSTR, /* SYSTEM_PERIPH_FLASH */
49+
NULL, /* SYSTEM_PERIPH_SRAM1 */
50+
NULL, /* SYSTEM_PERIPH_SRAM2 */
4951
&RCC->AHB1RSTR, /* SYSTEM_PERIPH_DMA1 */
5052
&RCC->AHB1RSTR, /* SYSTEM_PERIPH_DMA2 */
5153
&RCC->AHB2RSTR, /* SYSTEM_PERIPH_GPIOA */
@@ -94,6 +96,8 @@ static volatile uint32_t * const stm32l4_system_xlate_RSTR[] = {
9496

9597
static uint32_t const stm32l4_system_xlate_RSTMSK[] = {
9698
RCC_AHB1RSTR_FLASHRST, /* SYSTEM_PERIPH_FLASH */
99+
0, /* SYSTEM_PERIPH_SRAM1 */
100+
0, /* SYSTEM_PERIPH_SRAM2 */
97101
RCC_AHB1RSTR_DMA1RST, /* SYSTEM_PERIPH_DMA1 */
98102
RCC_AHB1RSTR_DMA2RST, /* SYSTEM_PERIPH_DMA2 */
99103
RCC_AHB2RSTR_GPIOARST, /* SYSTEM_PERIPH_GPIOA */
@@ -142,6 +146,8 @@ static uint32_t const stm32l4_system_xlate_RSTMSK[] = {
142146

143147
static volatile uint32_t * const stm32l4_system_xlate_ENR[] = {
144148
&RCC->AHB1ENR, /* SYSTEM_PERIPH_FLASH */
149+
NULL, /* SYSTEM_PERIPH_SRAM1 */
150+
NULL, /* SYSTEM_PERIPH_SRAM2 */
145151
&RCC->AHB1ENR, /* SYSTEM_PERIPH_DMA1 */
146152
&RCC->AHB1ENR, /* SYSTEM_PERIPH_DMA2 */
147153
&RCC->AHB2ENR, /* SYSTEM_PERIPH_GPIOA */
@@ -190,6 +196,8 @@ static volatile uint32_t * const stm32l4_system_xlate_ENR[] = {
190196

191197
static uint32_t const stm32l4_system_xlate_ENMSK[] = {
192198
RCC_AHB1ENR_FLASHEN, /* SYSTEM_PERIPH_FLASH */
199+
0, /* SYSTEM_PERIPH_SRAM1 */
200+
0, /* SYSTEM_PERIPH_SRAM2 */
193201
RCC_AHB1ENR_DMA1EN, /* SYSTEM_PERIPH_DMA1 */
194202
RCC_AHB1ENR_DMA2EN, /* SYSTEM_PERIPH_DMA2 */
195203
RCC_AHB2ENR_GPIOAEN, /* SYSTEM_PERIPH_GPIOA */
@@ -238,6 +246,8 @@ static uint32_t const stm32l4_system_xlate_ENMSK[] = {
238246

239247
static volatile uint32_t * const stm32l4_system_xlate_SMENR[] = {
240248
&RCC->AHB1SMENR, /* SYSTEM_PERIPH_FLASH */
249+
&RCC->AHB1SMENR, /* SYSTEM_PERIPH_SRAM1 */
250+
&RCC->AHB2SMENR, /* SYSTEM_PERIPH_SRAM2 */
241251
&RCC->AHB1SMENR, /* SYSTEM_PERIPH_DMA1 */
242252
&RCC->AHB1SMENR, /* SYSTEM_PERIPH_DMA2 */
243253
&RCC->AHB2SMENR, /* SYSTEM_PERIPH_GPIOA */
@@ -286,6 +296,8 @@ static volatile uint32_t * const stm32l4_system_xlate_SMENR[] = {
286296

287297
static uint32_t const stm32l4_system_xlate_SMENMSK[] = {
288298
RCC_AHB1SMENR_FLASHSMEN, /* SYSTEM_PERIPH_FLASH */
299+
RCC_AHB1SMENR_SRAM1SMEN, /* SYSTEM_PERIPH_SRAM1 */
300+
RCC_AHB2SMENR_SRAM2SMEN, /* SYSTEM_PERIPH_SRAM2 */
289301
RCC_AHB1SMENR_DMA1SMEN, /* SYSTEM_PERIPH_DMA1 */
290302
RCC_AHB1SMENR_DMA2SMEN, /* SYSTEM_PERIPH_DMA2 */
291303
RCC_AHB2SMENR_GPIOASMEN, /* SYSTEM_PERIPH_GPIOA */

‎system/libstm32l4_dragonfly/stm32l4_system.h

Lines changed: 46 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -38,50 +38,52 @@
3838
#endif
3939

4040
#define SYSTEM_PERIPH_FLASH 0
41-
#define SYSTEM_PERIPH_DMA1 1
42-
#define SYSTEM_PERIPH_DMA2 2
43-
#define SYSTEM_PERIPH_GPIOA 3
44-
#define SYSTEM_PERIPH_GPIOB 4
45-
#define SYSTEM_PERIPH_GPIOC 5
46-
#define SYSTEM_PERIPH_GPIOD 6
47-
#define SYSTEM_PERIPH_GPIOE 7
48-
#define SYSTEM_PERIPH_GPIOF 8
49-
#define SYSTEM_PERIPH_GPIOG 9
50-
#define SYSTEM_PERIPH_GPIOH 10
51-
#define SYSTEM_PERIPH_USB 11
52-
#define SYSTEM_PERIPH_ADC 12
53-
#define SYSTEM_PERIPH_QSPI 13
54-
#define SYSTEM_PERIPH_USART1 14
55-
#define SYSTEM_PERIPH_USART2 15
56-
#define SYSTEM_PERIPH_USART3 16
57-
#define SYSTEM_PERIPH_UART4 17
58-
#define SYSTEM_PERIPH_UART5 18
59-
#define SYSTEM_PERIPH_LPUART1 19
60-
#define SYSTEM_PERIPH_I2C1 20
61-
#define SYSTEM_PERIPH_I2C2 21
62-
#define SYSTEM_PERIPH_I2C3 22
63-
#define SYSTEM_PERIPH_SPI1 23
64-
#define SYSTEM_PERIPH_SPI2 24
65-
#define SYSTEM_PERIPH_SPI3 25
66-
#define SYSTEM_PERIPH_SDIO 26
67-
#define SYSTEM_PERIPH_SAI1 27
68-
#define SYSTEM_PERIPH_SAI2 28
69-
#define SYSTEM_PERIPH_DFSDM 29
70-
#define SYSTEM_PERIPH_CAN 30
71-
#define SYSTEM_PERIPH_TIM1 31
72-
#define SYSTEM_PERIPH_TIM2 32
73-
#define SYSTEM_PERIPH_TIM3 33
74-
#define SYSTEM_PERIPH_TIM4 34
75-
#define SYSTEM_PERIPH_TIM5 35
76-
#define SYSTEM_PERIPH_TIM6 36
77-
#define SYSTEM_PERIPH_TIM7 37
78-
#define SYSTEM_PERIPH_TIM8 38
79-
#define SYSTEM_PERIPH_TIM15 39
80-
#define SYSTEM_PERIPH_TIM16 40
81-
#define SYSTEM_PERIPH_TIM17 41
82-
#define SYSTEM_PERIPH_LPTIM1 42
83-
#define SYSTEM_PERIPH_LPTIM2 43
84-
#define SYSTEM_PERIPH_DAC 44
41+
#define SYSTEM_PERIPH_SRAM1 1
42+
#define SYSTEM_PERIPH_SRAM2 2
43+
#define SYSTEM_PERIPH_DMA1 3
44+
#define SYSTEM_PERIPH_DMA2 4
45+
#define SYSTEM_PERIPH_GPIOA 5
46+
#define SYSTEM_PERIPH_GPIOB 6
47+
#define SYSTEM_PERIPH_GPIOC 7
48+
#define SYSTEM_PERIPH_GPIOD 8
49+
#define SYSTEM_PERIPH_GPIOE 9
50+
#define SYSTEM_PERIPH_GPIOF 10
51+
#define SYSTEM_PERIPH_GPIOG 11
52+
#define SYSTEM_PERIPH_GPIOH 12
53+
#define SYSTEM_PERIPH_USB 13
54+
#define SYSTEM_PERIPH_ADC 14
55+
#define SYSTEM_PERIPH_QSPI 15
56+
#define SYSTEM_PERIPH_USART1 16
57+
#define SYSTEM_PERIPH_USART2 17
58+
#define SYSTEM_PERIPH_USART3 18
59+
#define SYSTEM_PERIPH_UART4 19
60+
#define SYSTEM_PERIPH_UART5 20
61+
#define SYSTEM_PERIPH_LPUART1 21
62+
#define SYSTEM_PERIPH_I2C1 22
63+
#define SYSTEM_PERIPH_I2C2 23
64+
#define SYSTEM_PERIPH_I2C3 24
65+
#define SYSTEM_PERIPH_SPI1 25
66+
#define SYSTEM_PERIPH_SPI2 26
67+
#define SYSTEM_PERIPH_SPI3 27
68+
#define SYSTEM_PERIPH_SDIO 28
69+
#define SYSTEM_PERIPH_SAI1 29
70+
#define SYSTEM_PERIPH_SAI2 30
71+
#define SYSTEM_PERIPH_DFSDM 31
72+
#define SYSTEM_PERIPH_CAN 32
73+
#define SYSTEM_PERIPH_TIM1 33
74+
#define SYSTEM_PERIPH_TIM2 34
75+
#define SYSTEM_PERIPH_TIM3 35
76+
#define SYSTEM_PERIPH_TIM4 36
77+
#define SYSTEM_PERIPH_TIM5 37
78+
#define SYSTEM_PERIPH_TIM6 38
79+
#define SYSTEM_PERIPH_TIM7 39
80+
#define SYSTEM_PERIPH_TIM8 40
81+
#define SYSTEM_PERIPH_TIM15 41
82+
#define SYSTEM_PERIPH_TIM16 42
83+
#define SYSTEM_PERIPH_TIM17 43
84+
#define SYSTEM_PERIPH_LPTIM1 44
85+
#define SYSTEM_PERIPH_LPTIM2 45
86+
#define SYSTEM_PERIPH_DAC 46
8587

8688
extern void stm32l4_system_periph_reset(unsigned int periph);
8789
extern void stm32l4_system_periph_enable(unsigned int periph);

‎system/libstm32l4_dragonfly/system_stm32l4xx.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -226,15 +226,22 @@ void SystemInit(void)
226226
SYSCFG->MEMRMP = (SYSCFG->MEMRMP & ~SYSCFG_MEMRMP_MEM_MODE);
227227
RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN;
228228

229-
RCC->AHB1SMENR &= ~RCC_AHB1SMENR_FLASHSMEN;
229+
RCC->AHB1SMENR &= ~(RCC_AHB1SMENR_FLASHSMEN |
230+
RCC_AHB1SMENR_SRAM1SMEN);
231+
230232
RCC->AHB2SMENR &= ~(RCC_AHB2SMENR_GPIOASMEN |
231233
RCC_AHB2SMENR_GPIOBSMEN |
232234
RCC_AHB2SMENR_GPIOCSMEN |
233235
RCC_AHB2SMENR_GPIODSMEN |
234236
RCC_AHB2SMENR_GPIOESMEN |
235237
RCC_AHB2SMENR_GPIOFSMEN |
236238
RCC_AHB2SMENR_GPIOGSMEN |
237-
RCC_AHB2SMENR_GPIOHSMEN);
239+
RCC_AHB2SMENR_GPIOHSMEN |
240+
RCC_AHB2SMENR_SRAM2SMEN);
241+
242+
RCC->APB1SMENR1 &= ~RCC_APB1SMENR1_PWRSMEN;
243+
244+
RCC->APB2SMENR &= ~RCC_APB2SMENR_SYSCFGSMEN;
238245

239246
/* Configure the Vector Table location add offset address ------------------*/
240247
#ifdef VECT_TAB_SRAM

‎variants/dragonfly/libstm32l4_dragonfly.a

1.23 KB
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