@@ -905,19 +905,19 @@ bool stm32l4_system_configure(uint32_t hclk, uint32_t pclk1, uint32_t pclk2)
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while (!(RCC -> CR & RCC_CR_MSIRDY ))
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{
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}
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-
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- if (stm32l4_system_device .lseclk == 32768 )
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- {
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- /* Enable the MSI PLL */
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- RCC -> CR |= RCC_CR_MSIPLLEN ;
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- }
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}
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else
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{
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RCC -> CR = (RCC -> CR & ~RCC_CR_MSIRANGE ) | msirange | RCC_CR_MSIRGSEL ;
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armv7m_clock_spin (500 );
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}
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+
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+ if (stm32l4_system_device .lseclk == 32768 )
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+ {
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+ /* Enable the MSI PLL */
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+ RCC -> CR |= RCC_CR_MSIPLLEN ;
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+ }
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RCC -> CFGR = (RCC -> CFGR & ~RCC_CFGR_SW ) | RCC_CFGR_SW_MSI ;
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@@ -996,19 +996,19 @@ bool stm32l4_system_configure(uint32_t hclk, uint32_t pclk1, uint32_t pclk2)
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while (!(RCC -> CR & RCC_CR_MSIRDY ))
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{
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}
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-
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- if (stm32l4_system_device .lseclk == 32768 )
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- {
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- /* Enable the MSI PLL */
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- RCC -> CR |= RCC_CR_MSIPLLEN ;
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- }
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}
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else
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{
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RCC -> CR = (RCC -> CR & ~RCC_CR_MSIRANGE ) | RCC_CR_MSIRANGE_11 | RCC_CR_MSIRGSEL ;
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armv7m_clock_spin (500 );
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}
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+
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+ if (stm32l4_system_device .lseclk == 32768 )
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+ {
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+ /* Enable the MSI PLL */
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+ RCC -> CR |= RCC_CR_MSIPLLEN ;
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+ }
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}
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}
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else
@@ -1153,16 +1153,19 @@ bool stm32l4_system_clk48_enable(void)
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while (!(RCC -> CR & RCC_CR_MSIRDY ))
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{
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}
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-
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- /* Enable the MSI PLL */
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- RCC -> CR |= RCC_CR_MSIPLLEN ;
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}
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else
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{
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RCC -> CR = (RCC -> CR & ~RCC_CR_MSIRANGE ) | RCC_CR_MSIRANGE_11 | RCC_CR_MSIRGSEL ;
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armv7m_clock_spin (500 );
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}
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+
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+ if (stm32l4_system_device .lseclk == 32768 )
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+ {
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+ /* Enable the MSI PLL */
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+ RCC -> CR |= RCC_CR_MSIPLLEN ;
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+ }
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}
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}
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