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GrumpyOldPizzaGrumpyOldPizza
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allow selection of F_CPU via menu
1 parent 5b187ca commit 52b6452

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8 files changed

+58
-11
lines changed

8 files changed

+58
-11
lines changed

‎boards.txt

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
# See: http://code.google.com/p/arduino/wiki/Platforms
22

3+
menu.CpuFrequency=CPU Frequency
4+
35
##############################################################
46

57
# Tlera Dragonfly
@@ -31,3 +33,16 @@ dragonfly.build.variant_system_lib=stm32l4_dragonfly
3133
dragonfly.build.variant_system_include="-I{runtime.platform.path}/system/libstm32l4_dragonfly/CMSIS/Include" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/CMSIS/Device/ST/STM32L4xx/Include" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/USB/HAL/Inc" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/USB/Core/Inc" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/USB/Class/CDC/Inc" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/USB/Class/MSC/Inc" "-I{runtime.platform.path}/system/libstm32l4_dragonfly/USB" "-I{runtime.platform.path}/system/libstm32l4_dragonfly"
3234
dragonfly.build.vid=0x1209
3335
dragonfly.build.pid=0x6667
36+
37+
dragonfly.menu.CpuFrequency.80=80 MHz
38+
dragonfly.menu.CpuFrequency.80.build.f_cpu=80000000L
39+
dragonfly.menu.CpuFrequency.72=72 MHz
40+
dragonfly.menu.CpuFrequency.72.build.f_cpu=72000000L
41+
dragonfly.menu.CpuFrequency.64=64 MHz
42+
dragonfly.menu.CpuFrequency.64.build.f_cpu=64000000L
43+
dragonfly.menu.CpuFrequency.48=48 MHz
44+
dragonfly.menu.CpuFrequency.48.build.f_cpu=48000000L
45+
dragonfly.menu.CpuFrequency.32=32 MHz
46+
dragonfly.menu.CpuFrequency.32.build.f_cpu=32000000L
47+
dragonfly.menu.CpuFrequency.16=16 MHz
48+
dragonfly.menu.CpuFrequency.16.build.f_cpu=16000000L

‎cores/stm32l4/wiring.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,11 @@ void UsageFault_Handler(void)
5353

5454
void init( void )
5555
{
56-
stm32l4_system_configure(F_CPU, F_CPU, F_CPU/2, F_CPU/2);
56+
#if (F_CPU <= 32000000)
57+
stm32l4_system_configure(F_CPU, F_CPU, F_CPU, F_CPU, true);
58+
#else
59+
stm32l4_system_configure(F_CPU, F_CPU, F_CPU/2, F_CPU/2, true);
60+
#endif
5761

5862
armv7m_svcall_initialize();
5963
armv7m_pendsv_initialize();

‎libraries/SPI/SPI.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,16 @@ class SPISettings {
6666

6767
if (bitOrder != MSBFIRST) { control |= SPI_CR1_LSBFIRST; }
6868

69+
#if (F_CPU <= 32000000)
70+
if (clock >= (F_CPU / 2)) { control |= 0; }
71+
else if (clock >= (F_CPU / 4)) { control |= (SPI_CR1_BR_0); }
72+
else if (clock >= (F_CPU / 8)) { control |= (SPI_CR1_BR_1); }
73+
else if (clock >= (F_CPU / 16)) { control |= (SPI_CR1_BR_0 | SPI_CR1_BR_1); }
74+
else if (clock >= (F_CPU / 32)) { control |= (SPI_CR1_BR_2); }
75+
else if (clock >= (F_CPU / 64)) { control |= (SPI_CR1_BR_0 | SPI_CR1_BR_2); }
76+
else if (clock >= (F_CPU / 128)) { control |= (SPI_CR1_BR_1 | SPI_CR1_BR_2); }
77+
else { control |= (SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_BR_2); }
78+
#else
6979
if (clock >= (F_CPU / 4)) { control |= 0; }
7080
else if (clock >= (F_CPU / 8)) { control |= (SPI_CR1_BR_0); }
7181
else if (clock >= (F_CPU / 16)) { control |= (SPI_CR1_BR_1); }
@@ -74,6 +84,7 @@ class SPISettings {
7484
else if (clock >= (F_CPU / 128)) { control |= (SPI_CR1_BR_0 | SPI_CR1_BR_2); }
7585
else if (clock >= (F_CPU / 256)) { control |= (SPI_CR1_BR_1 | SPI_CR1_BR_2); }
7686
else { control |= (SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_BR_2); }
87+
#endif
7788

7889
this->_control = control;
7990
}

‎system/libstm32l4_dragonfly/USB/HAL/Src/stm32l4xx_hal_pcd.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
324324
return HAL_OK;
325325
}
326326
#if defined (USB_OTG_FS)
327+
extern uint32_t stm32l4_system_hclk(void);
327328
/**
328329
* @brief Handles PCD interrupt request.
329330
* @param hpcd: PCD handle
@@ -566,7 +567,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
566567
used by application. In the low AHB frequency range it is used to stretch enough the USB response
567568
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
568569
latency to the Data FIFO */
569-
570+
571+
hclk = stm32l4_system_hclk();
572+
570573
if((hclk >= 14200000)&&(hclk < 15000000))
571574
{
572575
/* hclk Clock Range between 14.2-15 MHz */

‎system/libstm32l4_dragonfly/stm32l4_qspi.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -317,6 +317,8 @@ bool stm32l4_qspi_disable(stm32l4_qspi_t *qspi)
317317

318318
bool stm32l4_qspi_configure(stm32l4_qspi_t *qspi, uint32_t clock, uint32_t option)
319319
{
320+
uint32_t hclk;
321+
320322
if ((qspi->state != QSPI_STATE_READY) && (qspi->state != QSPI_STATE_BUSY))
321323
{
322324
return false;
@@ -332,14 +334,21 @@ bool stm32l4_qspi_configure(stm32l4_qspi_t *qspi, uint32_t clock, uint32_t optio
332334
return false;
333335
}
334336

337+
hclk = stm32l4_system_hclk();
338+
339+
if (clock > hclk)
340+
{
341+
clock = hclk;
342+
}
343+
335344
qspi->clock = clock;
336345
qspi->option = option;
337346

338347
stm32l4_qspi_start(qspi);
339348

340349
QUADSPI->CR &= ~QUADSPI_CR_EN;
341350

342-
QUADSPI->CR = (((stm32l4_system_hclk() / qspi->clock) -1) << 24) | QUADSPI_CR_APMS | QUADSPI_CR_FTHRES_1;
351+
QUADSPI->CR = (((hclk / clock) -1) << 24) | QUADSPI_CR_APMS | QUADSPI_CR_FTHRES_1;
343352
// QUADSPI->CR = QUADSPI_CR_APMS | QUADSPI_CR_FTHRES_1;
344353

345354
QUADSPI->DCR = QUADSPI_DCR_FSIZE | ((qspi->option & QSPI_OPTION_MODE_MASK) >> QSPI_OPTION_MODE_SHIFT);

‎system/libstm32l4_dragonfly/stm32l4_system.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -404,12 +404,12 @@ void stm32l4_system_bootloader(void)
404404
#endif
405405
}
406406

407-
bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, uint32_t pclk2)
407+
bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, uint32_t pclk2, bool clk48)
408408
{
409409
uint32_t fclk, fvco, fpll, fpllout, mout, nout, rout, n, r;
410410
uint32_t count, msirange, hpre, ppre1, ppre2, latency;
411411

412-
if ((sysclk <= 24000000) && stm32l4_system_device.clk48)
412+
if (!clk48 && ((sysclk <= 24000000) && stm32l4_system_device.clk48))
413413
{
414414
return false;
415415
}
@@ -533,7 +533,7 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
533533
nout = 8;
534534
rout = 2;
535535

536-
if (sysclk <= 24000000)
536+
if (!clk48 && (sysclk <= 24000000))
537537
{
538538
/* Range 2, use MSI */
539539

@@ -552,6 +552,11 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
552552
{
553553
/* Range 1, use HSE/PLL or MSI/PLL */
554554

555+
if (sysclk < 16000000)
556+
{
557+
sysclk = 16000000;
558+
}
559+
555560
if (sysclk > 80000000)
556561
{
557562
sysclk = 80000000;
@@ -679,7 +684,7 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
679684
RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)) | (hpre | ppre1 | ppre2);
680685

681686

682-
if (sysclk <= 24000000)
687+
if (!clk48 && (sysclk <= 24000000))
683688
{
684689
/* Range 2, use MSI */
685690

@@ -825,7 +830,7 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
825830
SystemCoreClock = sysclk;
826831
}
827832

828-
if (sysclk <= 24000000)
833+
if (!clk48 && (sysclk <= 24000000))
829834
{
830835
if (hclk <= 6000000) { latency = FLASH_ACR_LATENCY_0WS; }
831836
else if (hclk <= 12000000) { latency = FLASH_ACR_LATENCY_1WS; }
@@ -859,7 +864,7 @@ bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, ui
859864

860865
bool stm32l4_system_clk48_enable(void)
861866
{
862-
if ((stm32l4_system_device.sysclk <= 24000000) || (stm32l4_system_device.lseclk != 32768))
867+
if (((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) || (stm32l4_system_device.lseclk != 32768))
863868
{
864869
return false;
865870
}
@@ -898,7 +903,7 @@ bool stm32l4_system_clk48_enable(void)
898903

899904
bool stm32l4_system_clk48_disable(void)
900905
{
901-
if ((stm32l4_system_device.sysclk <= 24000000) || (stm32l4_system_device.lseclk != 32768))
906+
if (((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) || (stm32l4_system_device.lseclk != 32768))
902907
{
903908
return false;
904909
}

‎system/libstm32l4_dragonfly/stm32l4_system.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ extern void stm32l4_system_periph_reset(unsigned int periph);
8686
extern void stm32l4_system_periph_enable(unsigned int periph);
8787
extern void stm32l4_system_periph_disable(unsigned int periph);
8888
extern void stm32l4_system_bootloader(void);
89-
extern bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, uint32_t pclk2);
89+
extern bool stm32l4_system_configure(uint32_t sysclk, uint32_t hclk, uint32_t pclk1, uint32_t pclk2, bool clk48);
9090
extern bool stm32l4_system_clk48_enable(void);
9191
extern bool stm32l4_system_clk48_disable(void);
9292
extern uint32_t stm32l4_system_sysclk(void);

‎variants/dragonfly/libstm32l4_dragonfly.a

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