Removing the old -RV32 directory name from parts of the documentation (#1196)

rwardd · web-flow · commit 874fa7bed4b3 · 2024-11-20T12:08:15.000+05:30
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 
diff --git a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
@@ -32,7 +32,7 @@
  * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
  *
  * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   FreeRTOS\Source\portable\GCC\RISC-V\portASM.S.  There is only one
  *   portASM.S file because the same file is used no matter which RISC-V chip is
  *   in use.
  *
diff --git a/portable/GCC/RISC-V/readme.txt b/portable/GCC/RISC-V/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */

Original file line number	Diff line number	Diff line change
`@@ -31,7 +31,7 @@`
`31`	`31`	`* common across all currently supported RISC-V chips (implementations of the`
`32`	`32`	`* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:`
`33`	`33`	`*`
`34`		`- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that`
	`34`	`+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that`
`35`	`35`	`* is common to all currently supported RISC-V chips. There is only one`
`36`	`36`	`* portASM.S file because the same file is built for all RISC-V target chips.`
`37`	`37`	`*`
`@@ -46,7 +46,7 @@`
`46`	`46`	`* compiler's!) include path. For example, if the chip in use includes a core`
`47`	`47`	`* local interrupter (CLINT) and does not include any chip specific register`
`48`	`48`	`* extensions then add the path below to the assembler's include path:`
`49`		`- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions`
	`49`	`+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions`
`50`	`50`	`*`
`51`	`51`	`*/`
`52`	`52`
Original file line number	Diff line number	Diff line change
`@@ -3,7 +3,7 @@`
`3`	`3`	`* common across all currently supported RISC-V chips (implementations of the`
`4`	`4`	`* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:`
`5`	`5`	`*`
`6`		`- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that`
	`6`	`+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that`
`7`	`7`	`* is common to all currently supported RISC-V chips. There is only one`
`8`	`8`	`* portASM.S file because the same file is built for all RISC-V target chips.`
`9`	`9`	`*`
`@@ -18,6 +18,6 @@`
`18`	`18`	`* compiler's!) include path. For example, if the chip in use includes a core`
`19`	`19`	`* local interrupter (CLINT) and does not include any chip specific register`
`20`	`20`	`* extensions then add the path below to the assembler's include path:`
`21`		`- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions`
	`21`	`+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions`
`22`	`22`	`*`
`23`	`23`	`*/`
Original file line number	Diff line number	Diff line change
`@@ -32,7 +32,7 @@`
`32`	`32`	`* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:`
`33`	`33`	`*`
`34`	`34`	`* + The code that is common to all RISC-V chips is implemented in`
`35`		`- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one`
	`35`	`+ * FreeRTOS\Source\portable\GCC\RISC-V\portASM.S. There is only one`
`36`	`36`	`* portASM.S file because the same file is used no matter which RISC-V chip is`
`37`	`37`	`* in use.`
`38`	`38`	`*`