@@ -1341,3 +1341,109 @@ entry:
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%call = call float %fptr (i32 poison) #7
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ret float %call
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}
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+
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+ define float @float_return_undef_float_arg (ptr nocapture %fptr ) #6 {
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+ ; CHECK-8M-LABEL: float_return_undef_float_arg:
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+ ; CHECK-8M: @ %bb.0: @ %entry
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+ ; CHECK-8M-NEXT: push {r7, lr}
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+ ; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-8M-NEXT: bic r0, r0, #1
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+ ; CHECK-8M-NEXT: sub sp, #136
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+ ; CHECK-8M-NEXT: vmov r12, s0
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+ ; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
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+ ; CHECK-8M-NEXT: vmov s0, r12
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+ ; CHECK-8M-NEXT: ldr r1, [sp, #64]
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+ ; CHECK-8M-NEXT: bic r1, r1, #159
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+ ; CHECK-8M-NEXT: bic r1, r1, #4026531840
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+ ; CHECK-8M-NEXT: vmsr fpscr, r1
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+ ; CHECK-8M-NEXT: mov r1, r0
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+ ; CHECK-8M-NEXT: mov r2, r0
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+ ; CHECK-8M-NEXT: mov r3, r0
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+ ; CHECK-8M-NEXT: mov r4, r0
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+ ; CHECK-8M-NEXT: mov r5, r0
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+ ; CHECK-8M-NEXT: mov r6, r0
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+ ; CHECK-8M-NEXT: mov r7, r0
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+ ; CHECK-8M-NEXT: mov r8, r0
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+ ; CHECK-8M-NEXT: mov r9, r0
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+ ; CHECK-8M-NEXT: mov r10, r0
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+ ; CHECK-8M-NEXT: mov r11, r0
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+ ; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
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+ ; CHECK-8M-NEXT: blxns r0
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+ ; CHECK-8M-NEXT: vmov r12, s0
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+ ; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
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+ ; CHECK-8M-NEXT: vmov s0, r12
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+ ; CHECK-8M-NEXT: add sp, #136
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+ ; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-8M-NEXT: pop {r7, pc}
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+ ;
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+ ; CHECK-81M-LABEL: float_return_undef_float_arg:
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+ ; CHECK-81M: @ %bb.0: @ %entry
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+ ; CHECK-81M-NEXT: push {r7, lr}
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+ ; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-81M-NEXT: bic r0, r0, #1
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+ ; CHECK-81M-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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+ ; CHECK-81M-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
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+ ; CHECK-81M-NEXT: vstr fpcxts, [sp, #-8]!
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+ ; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
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+ ; CHECK-81M-NEXT: blxns r0
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+ ; CHECK-81M-NEXT: vldr fpcxts, [sp], #8
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+ ; CHECK-81M-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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+ ; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-81M-NEXT: pop {r7, pc}
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+ entry:
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+ %call = call float %fptr (float undef ) #7
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+ ret float %call
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+ }
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+
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+ define float @float_return_poison_float_arg (ptr nocapture %fptr ) #6 {
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+ ; CHECK-8M-LABEL: float_return_poison_float_arg:
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+ ; CHECK-8M: @ %bb.0: @ %entry
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+ ; CHECK-8M-NEXT: push {r7, lr}
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+ ; CHECK-8M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-8M-NEXT: bic r0, r0, #1
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+ ; CHECK-8M-NEXT: sub sp, #136
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+ ; CHECK-8M-NEXT: vmov r12, s0
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+ ; CHECK-8M-NEXT: vlstm sp, {d0 - d15}
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+ ; CHECK-8M-NEXT: vmov s0, r12
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+ ; CHECK-8M-NEXT: ldr r1, [sp, #64]
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+ ; CHECK-8M-NEXT: bic r1, r1, #159
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+ ; CHECK-8M-NEXT: bic r1, r1, #4026531840
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+ ; CHECK-8M-NEXT: vmsr fpscr, r1
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+ ; CHECK-8M-NEXT: mov r1, r0
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+ ; CHECK-8M-NEXT: mov r2, r0
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+ ; CHECK-8M-NEXT: mov r3, r0
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+ ; CHECK-8M-NEXT: mov r4, r0
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+ ; CHECK-8M-NEXT: mov r5, r0
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+ ; CHECK-8M-NEXT: mov r6, r0
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+ ; CHECK-8M-NEXT: mov r7, r0
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+ ; CHECK-8M-NEXT: mov r8, r0
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+ ; CHECK-8M-NEXT: mov r9, r0
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+ ; CHECK-8M-NEXT: mov r10, r0
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+ ; CHECK-8M-NEXT: mov r11, r0
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+ ; CHECK-8M-NEXT: msr apsr_nzcvqg, r0
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+ ; CHECK-8M-NEXT: blxns r0
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+ ; CHECK-8M-NEXT: vmov r12, s0
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+ ; CHECK-8M-NEXT: vlldm sp, {d0 - d15}
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+ ; CHECK-8M-NEXT: vmov s0, r12
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+ ; CHECK-8M-NEXT: add sp, #136
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+ ; CHECK-8M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-8M-NEXT: pop {r7, pc}
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+ ;
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+ ; CHECK-81M-LABEL: float_return_poison_float_arg:
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+ ; CHECK-81M: @ %bb.0: @ %entry
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+ ; CHECK-81M-NEXT: push {r7, lr}
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+ ; CHECK-81M-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-81M-NEXT: bic r0, r0, #1
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+ ; CHECK-81M-NEXT: vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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+ ; CHECK-81M-NEXT: vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
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+ ; CHECK-81M-NEXT: vstr fpcxts, [sp, #-8]!
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+ ; CHECK-81M-NEXT: clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
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+ ; CHECK-81M-NEXT: blxns r0
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+ ; CHECK-81M-NEXT: vldr fpcxts, [sp], #8
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+ ; CHECK-81M-NEXT: vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
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+ ; CHECK-81M-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
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+ ; CHECK-81M-NEXT: pop {r7, pc}
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+ entry:
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+ %call = call float %fptr (float poison) #7
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+ ret float %call
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+ }
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