@@ -7,6 +7,9 @@ function %br_icmp(i32, i32) -> i32 {
7
7
ebb0(v0: i32, v1: i32):
8
8
[Op1icscc#39,%rdx] v2 = icmp slt v0, v1
9
9
[Op1t8jccd_long#85] brnz v2, ebb1
10
+ [-] fallthrough ebb2
11
+
12
+ ebb2:
10
13
[Op1ret#c3] return v1
11
14
12
15
ebb1:
18
21
; nextln: v9 = ifcmp v0, v1
19
22
; nextln: v2 = trueif slt v9
20
23
; nextln: brif slt v9, ebb1
24
+ ; nextln: fallthrough ebb2
25
+ ; nextln:
26
+ ; nextln: ebb2:
21
27
; nextln: return v1
22
28
; nextln:
23
29
; nextln: ebb1:
@@ -31,6 +37,9 @@ function %br_icmp_inverse(i32, i32) -> i32 {
31
37
ebb0(v0: i32, v1: i32):
32
38
[Op1icscc#39,%rdx] v2 = icmp slt v0, v1
33
39
[Op1t8jccd_long#84] brz v2, ebb1
40
+ [-] fallthrough ebb2
41
+
42
+ ebb2:
34
43
[Op1ret#c3] return v1
35
44
36
45
ebb1:
42
51
; nextln: v9 = ifcmp v0, v1
43
52
; nextln: v2 = trueif slt v9
44
53
; nextln: brif sge v9, ebb1
54
+ ; nextln: fallthrough ebb2
55
+ ; nextln:
56
+ ; nextln: ebb2:
45
57
; nextln: return v1
46
58
; nextln:
47
59
; nextln: ebb1:
@@ -55,6 +67,9 @@ function %br_icmp_imm(i32, i32) -> i32 {
55
67
ebb0(v0: i32, v1: i32):
56
68
[Op1icscc_ib#7083] v2 = icmp_imm slt v0, 2
57
69
[Op1t8jccd_long#84] brz v2, ebb1
70
+ [-] fallthrough ebb2
71
+
72
+ ebb2:
58
73
[Op1ret#c3] return v1
59
74
60
75
ebb1:
66
81
; nextln: v9 = ifcmp_imm v0, 2
67
82
; nextln: v2 = trueif slt v9
68
83
; nextln: brif sge v9, ebb1
84
+ ; nextln: fallthrough ebb2
85
+ ; nextln:
86
+ ; nextln: ebb2:
69
87
; nextln: return v1
70
88
; nextln:
71
89
; nextln: ebb1:
@@ -79,6 +97,9 @@ function %br_fcmp(f32, f32) -> f32 {
79
97
ebb0(v0: f32, v1: f32):
80
98
[Op2fcscc#42e,%rdx] v2 = fcmp gt v0, v1
81
99
[Op1t8jccd_long#84] brz v2, ebb1
100
+ [-] fallthrough ebb2
101
+
102
+ ebb2:
82
103
[Op1ret#c3] return v1
83
104
84
105
ebb1:
91
112
; nextln: v19 = ffcmp v0, v1
92
113
; nextln: v2 = trueff gt v19
93
114
; nextln: brff ule v19, ebb1
115
+ ; nextln: fallthrough ebb2
116
+ ; nextln:
117
+ ; nextln: ebb2:
94
118
; nextln: return v1
95
119
; nextln:
96
120
; nextln: ebb1:
0 commit comments