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[STM32L1XX] Add STM32CUBE_L1 hal common files
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‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/Release_Notes_stm32l1xx_hal.html

Lines changed: 19 additions & 1 deletion
Large diffs are not rendered by default.

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32_hal_legacy.h

Lines changed: 155 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32_hal_legacy.h
44
* @author MCD Application Team
5-
* @version V1.1.3
6-
* @date 04-March-2016
5+
* @version V1.2.0
6+
* @date 01-July-2016
77
* @brief This file contains aliases definition for the STM32Cube HAL constants
88
* macros and functions maintained for legacy purpose.
99
******************************************************************************
@@ -129,7 +129,6 @@
129129
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
130130
* @{
131131
*/
132-
133132
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
134133
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
135134
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@@ -144,6 +143,73 @@
144143
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
145144
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
146145
#endif /* STM32F373xC || STM32F378xx */
146+
147+
#if defined(STM32L0) || defined(STM32L4)
148+
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
149+
150+
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
151+
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
152+
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
153+
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
154+
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
155+
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
156+
157+
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
158+
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
159+
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
160+
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
161+
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
162+
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
163+
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
164+
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
165+
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
166+
#if defined(STM32L0)
167+
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
168+
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
169+
/* to the second dedicated IO (only for COMP2). */
170+
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
171+
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
172+
#else
173+
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
174+
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
175+
#endif
176+
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
177+
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
178+
179+
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
180+
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
181+
182+
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
183+
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
184+
#if defined(COMP_CSR_LOCK)
185+
#define COMP_FLAG_LOCK COMP_CSR_LOCK
186+
#elif defined(COMP_CSR_COMP1LOCK)
187+
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
188+
#elif defined(COMP_CSR_COMPxLOCK)
189+
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
190+
#endif
191+
192+
#if defined(STM32L4)
193+
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
194+
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
195+
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
196+
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
197+
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
198+
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
199+
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
200+
#endif
201+
202+
#if defined(STM32L0)
203+
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
204+
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
205+
#else
206+
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
207+
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
208+
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
209+
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
210+
#endif
211+
212+
#endif
147213
/**
148214
* @}
149215
*/
@@ -384,6 +450,7 @@
384450
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
385451
#endif /* STM32F0 || STM32F3 || STM32F1 */
386452

453+
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
387454
/**
388455
* @}
389456
*/
@@ -424,7 +491,7 @@
424491
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
425492
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
426493
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
427-
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1)
494+
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
428495
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
429496
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
430497
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -875,9 +942,12 @@
875942
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
876943
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
877944
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
945+
#if defined(STM32F1)
946+
#else
878947
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
879948
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
880949
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
950+
#endif
881951
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
882952
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
883953
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@@ -897,9 +967,41 @@
897967
#define DCMI_IT_OVF DCMI_IT_OVR
898968
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
899969
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
970+
971+
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
972+
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
973+
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
974+
900975
/**
901976
* @}
902977
*/
978+
979+
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
980+
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
981+
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
982+
* @{
983+
*/
984+
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
985+
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
986+
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
987+
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
988+
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
989+
990+
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
991+
#define CM_RGB888 DMA2D_INPUT_RGB888
992+
#define CM_RGB565 DMA2D_INPUT_RGB565
993+
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
994+
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
995+
#define CM_L8 DMA2D_INPUT_L8
996+
#define CM_AL44 DMA2D_INPUT_AL44
997+
#define CM_AL88 DMA2D_INPUT_AL88
998+
#define CM_L4 DMA2D_INPUT_L4
999+
#define CM_A8 DMA2D_INPUT_A8
1000+
#define CM_A4 DMA2D_INPUT_A4
1001+
/**
1002+
* @}
1003+
*/
1004+
#endif /* STM32L4xx || STM32F7*/
9031005

9041006
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
9051007
* @{
@@ -957,7 +1059,10 @@
9571059
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
9581060
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
9591061
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
1062+
#if defined(STM32L0)
1063+
#else
9601064
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
1065+
#endif
9611066
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
9621067
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
9631068
/**
@@ -1461,10 +1566,28 @@
14611566

14621567
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
14631568

1569+
#if defined(STM32L0) || defined(STM32L4)
1570+
/* Note: On these STM32 families, the only argument of this macro */
1571+
/* is COMP_FLAG_LOCK. */
1572+
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
1573+
/* argument. */
1574+
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
1575+
#endif
14641576
/**
14651577
* @}
14661578
*/
14671579

1580+
#if defined(STM32L0) || defined(STM32L4)
1581+
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
1582+
* @{
1583+
*/
1584+
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
1585+
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
1586+
/**
1587+
* @}
1588+
*/
1589+
#endif
1590+
14681591
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
14691592
* @{
14701593
*/
@@ -2508,7 +2631,7 @@
25082631
#endif
25092632

25102633
#if defined(STM32F7)
2511-
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
2634+
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
25122635
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
25132636
#endif
25142637

@@ -2625,6 +2748,31 @@
26252748

26262749
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
26272750
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
2751+
2752+
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
2753+
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
2754+
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
2755+
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
2756+
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
2757+
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
2758+
2759+
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
2760+
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
2761+
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
2762+
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
2763+
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
2764+
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
2765+
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
2766+
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
2767+
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
2768+
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
2769+
#define DfsdmClockSelection Dfsdm1ClockSelection
2770+
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
2771+
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
2772+
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
2773+
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
2774+
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
2775+
26282776
/**
26292777
* @}
26302778
*/
@@ -2913,6 +3061,8 @@
29133061
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
29143062
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
29153063
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
3064+
3065+
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
29163066
/**
29173067
* @}
29183068
*/

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l1xx_hal.c
44
* @author MCD Application Team
5-
* @version V1.1.3
6-
* @date 04-March-2016
5+
* @version V1.2.0
6+
* @date 01-July-2016
77
* @brief HAL module driver.
88
* This is the common part of the HAL initialization
99
*
@@ -72,11 +72,11 @@
7272
*/
7373

7474
/**
75-
* @brief STM32L1xx HAL Driver version number V1.1.3
75+
* @brief STM32L1xx HAL Driver version number
7676
*/
7777
#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
78-
#define __STM32L1xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
79-
#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
78+
#define __STM32L1xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
79+
#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
8080
#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
8181
#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
8282
|(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
@@ -96,7 +96,7 @@
9696
* @{
9797
*/
9898

99-
static __IO uint32_t uwTick;
99+
__IO uint32_t uwTick;
100100

101101
/**
102102
* @}

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32l1xx_hal.h
44
* @author MCD Application Team
5-
* @version V1.1.3
6-
* @date 04-March-2016
5+
* @version V1.2.0
6+
* @date 01-July-2016
77
* @brief This file contains all the functions prototypes for the HAL
88
* module driver.
99
******************************************************************************
@@ -69,7 +69,7 @@
6969
* @{
7070
*/
7171

72-
#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000)
72+
#define SYSCFG_BOOT_MAINFLASH (0x00000000U)
7373
#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
7474
#if defined(FSMC_R_BASE)
7575
#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
@@ -105,7 +105,7 @@
105105
* @{
106106
*/
107107

108-
#define TIM_SELECT_NONE ((uint32_t)0x00000000) /*!< None selected */
108+
#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */
109109
#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */
110110
#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */
111111
#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */
@@ -123,22 +123,22 @@
123123
* @{
124124
*/
125125
/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
126-
#define RI_INPUTCAPTUREROUTING_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
127-
#define RI_INPUTCAPTUREROUTING_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
128-
#define RI_INPUTCAPTUREROUTING_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
129-
#define RI_INPUTCAPTUREROUTING_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
130-
#define RI_INPUTCAPTUREROUTING_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
131-
#define RI_INPUTCAPTUREROUTING_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
132-
#define RI_INPUTCAPTUREROUTING_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
133-
#define RI_INPUTCAPTUREROUTING_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
134-
#define RI_INPUTCAPTUREROUTING_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
135-
#define RI_INPUTCAPTUREROUTING_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
136-
#define RI_INPUTCAPTUREROUTING_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
137-
#define RI_INPUTCAPTUREROUTING_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
138-
#define RI_INPUTCAPTUREROUTING_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
139-
#define RI_INPUTCAPTUREROUTING_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
140-
#define RI_INPUTCAPTUREROUTING_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
141-
#define RI_INPUTCAPTUREROUTING_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
126+
#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
127+
#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
128+
#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
129+
#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
130+
#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
131+
#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
132+
#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
133+
#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
134+
#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
135+
#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
136+
#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
137+
#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
138+
#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
139+
#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
140+
#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
141+
#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
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#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
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((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
@@ -164,7 +164,7 @@
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/** @defgroup RI_IOSwitch IO Switch
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* @{
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*/
167-
#define RI_ASCR1_REGISTER ((uint32_t)0x80000000)
167+
#define RI_ASCR1_REGISTER (0x80000000U)
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/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
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#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
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#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)

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