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Merge pull request #3911 from anangl/fix_iar_exporter
IAR exporter: extended debugger settings template with modifiable options needed for Nordic targets
2 parents f3499f5 + 377f759 commit 9c141b6

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+14
-5
lines changed

3 files changed

+14
-5
lines changed

tools/export/iar/__init__.py

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@@ -78,6 +78,9 @@ def iar_device(self):
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"FPU2": 0,
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"NrRegs": 0,
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"NEON": '',
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"CExtraOptionsCheck": 0,
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"CExtraOptions": "",
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"CMSISDAPJtagSpeedList": 0,
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}
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iar_defaults.update(device_info)

tools/export/iar/ewd.tmpl

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@@ -57,11 +57,11 @@
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</option>
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<option>
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<name>CExtraOptionsCheck</name>
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<state>0</state>
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<state>{{device.CExtraOptionsCheck}}</state>
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</option>
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<option>
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<name>CExtraOptions</name>
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<state></state>
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<state>{{device.CExtraOptions}}</state>
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</option>
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<option>
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<name>CFpuProcessor</name>
@@ -365,7 +365,7 @@
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<option>
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<name>CMSISDAPJtagSpeedList</name>
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<version>0</version>
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<state>0</state>
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<state>{{device.CMSISDAPJtagSpeedList}}</state>
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</option>
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<option>
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<name>CMSISDAPBreakpointRadio</name>

tools/export/iar/iar_definitions.json

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@@ -42,7 +42,10 @@
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"OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB"
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},
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"nRF51822_xxAA": {
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"OGChipSelectEditMenu": "nRF51822-QFAA\tNordicSemi nRF51822-QFAA"
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"OGChipSelectEditMenu": "nRF51822-QFAA\tNordicSemi nRF51822-QFAA",
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"CExtraOptionsCheck": 1,
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"CExtraOptions": "--drv_vector_table_base=0x0",
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"CMSISDAPJtagSpeedList": 10
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},
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"EFM32GG990F1024": {
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"OGChipSelectEditMenu": "EFM32GG990F1024\tSiliconLaboratories EFM32GG990F1024"
@@ -163,7 +166,10 @@
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"OGChipSelectEditMenu": "STM32F407VG\tST STM32F407VG"
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},
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"nRF52832_xxAA":{
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"OGChipSelectEditMenu": "nRF52832-xxAA\tNordicSemi nRF52832-xxAA"
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"OGChipSelectEditMenu": "nRF52832-xxAA\tNordicSemi nRF52832-xxAA",
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"CExtraOptionsCheck": 1,
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"CExtraOptions": "--drv_vector_table_base=0x0",
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"CMSISDAPJtagSpeedList": 10
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},
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"NCS36510":{
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"OGChipSelectEditMenu": "NCS36510\tONSemiconductor NCS36510"

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