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Merge pull request #15343 from daniel-starke/complete-nucleo-h723zg
Add proper support for NUCLEO-H723ZG.
2 parents 90837c5 + ffcfa2f commit 7ab5260

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‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt

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@@ -9,6 +9,8 @@ elseif("NUCLEO_H743ZI" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H743ZI)
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elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H743ZI2)
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elseif("NUCLEO_H723ZG" IN_LIST MBED_TARGET_LABELS)
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add_subdirectory(TARGET_NUCLEO_H723ZG)
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endif()
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target_include_directories(mbed-emac

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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target_sources(mbed-emac
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INTERFACE
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stm32h7_eth_init.c
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)

‎connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c

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/* mbed Microcontroller Library
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
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#include "stm32h7xx_hal.h"
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#include "platform/mbed_critical.h"
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#define MCO_Pin GPIO_PIN_0
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#define MCO_GPIO_Port GPIOH
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#define RMII_MDC_Pin GPIO_PIN_1
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#define RMII_MDC_GPIO_Port GPIOC
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#define RMII_REF_CLK_Pin GPIO_PIN_1
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#define RMII_REF_CLK_GPIO_Port GPIOA
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#define RMII_MDIO_Pin GPIO_PIN_2
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#define RMII_MDIO_GPIO_Port GPIOA
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#define RMII_CRS_DV_Pin GPIO_PIN_7
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#define RMII_CRS_DV_GPIO_Port GPIOA
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#define RMII_RXD0_Pin GPIO_PIN_4
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#define RMII_RXD0_GPIO_Port GPIOC
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#define RMII_RXD1_Pin GPIO_PIN_5
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#define RMII_RXD1_GPIO_Port GPIOC
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#define RMII_TXD1_Pin GPIO_PIN_13
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#define RMII_TXD1_GPIO_Port GPIOB
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#define TMS_Pin GPIO_PIN_13
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#define TMS_GPIO_Port GPIOA
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#define TCK_Pin GPIO_PIN_14
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#define TCK_GPIO_Port GPIOA
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#define RMII_TX_EN_Pin GPIO_PIN_11
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#define RMII_TX_EN_GPIO_Port GPIOG
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#define RMII_TXD0_Pin GPIO_PIN_13
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#define RMII_TXD0_GPIO_Port GPIOG
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/**
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* Override HAL Eth Init function
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*/
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void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if (heth->Instance == ETH) {
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/* Disable DCache for STM32H7 family */
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core_util_critical_section_enter();
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SCB_DisableDCache();
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core_util_critical_section_exit();
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* Enable Peripheral clock */
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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/**ETH GPIO Configuration
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PC1 ------> ETH_MDC
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PA1 ------> ETH_REF_CLK
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PA2 ------> ETH_MDIO
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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PB13 ------> ETH_TXD1
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PG11 ------> ETH_TX_EN
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PG13 ------> ETH_TXD0
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*/
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GPIO_InitStruct.Pin = RMII_MDC_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_TXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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}
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}
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/**
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* Override HAL Eth DeInit function
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*/
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void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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{
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if (heth->Instance == ETH) {
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/* Disable Peripheral clock */
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__HAL_RCC_ETH1MAC_CLK_DISABLE();
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__HAL_RCC_ETH1TX_CLK_DISABLE();
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__HAL_RCC_ETH1RX_CLK_DISABLE();
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/**ETH GPIO Configuration
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PC1 ------> ETH_MDC
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PA1 ------> ETH_REF_CLK
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PA2 ------> ETH_MDIO
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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PB13 ------> ETH_TXD1
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PG11 ------> ETH_TX_EN
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PG13 ------> ETH_TXD0
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*/
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HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin);
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HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin);
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HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
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HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin);
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}
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}
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#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(TARGET_NUCLEO_H723ZG EXCLUDE_FROM_ALL)
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if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
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set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S)
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set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h723xg.ld)

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt

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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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add_library(mbed-nucleo-h723zg INTERFACE)
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target_sources(mbed-nucleo-h723zg
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INTERFACE
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PeripheralPins.c
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system_clock.c
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)
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target_include_directories(mbed-nucleo-h723zg
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INTERFACE
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.
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)
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target_link_libraries(mbed-nucleo-h723zg INTERFACE mbed-stm32h723xg)

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