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ADD NEW TARGET : NUCLEO_L486RG, based on existing NUCLEO_L476RG
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targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/TARGET_NUCLEO_L486RG/device/stm32l486xx.h

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/**
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******************************************************************************
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* @file stm32l4xx.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 29-April-2016
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* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32L4xx device used in the target application
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* - To use or not the peripheral�s drivers in application code(i.e.
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* code will be based on direct access to peripheral�s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l4xx
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* @{
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*/
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#ifndef __STM32L4xx_H
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#define __STM32L4xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32L4)
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#define STM32L4
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#endif /* STM32L4 */
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/* Uncomment the line below according to the target STM32L4 device used in your
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application
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*/
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#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
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!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
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/* #define STM32L431xx */ /*!< STM32L431xx Devices */
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/* #define STM32L432xx */ /*!< STM32L432xx Devices */
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/* #define STM32L433xx */ /*!< STM32L433xx Devices */
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/* #define STM32L442xx */ /*!< STM32L442xx Devices */
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/* #define STM32L443xx */ /*!< STM32L443xx Devices */
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/* #define STM32L471xx */ /*!< STM32L471xx Devices */
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/* #define STM32L475xx */ /*!< STM32L475xx Devices */
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/* #define STM32L476xx */ /*!< STM32L476xx Devices */
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/* #define STM32L485xx */ /*!< STM32L485xx Devices */
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#define STM32L486xx /*!< STM32L486xx Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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#define USE_HAL_DRIVER
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.1.1
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*/
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#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32L4_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
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#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
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|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
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|(__STM32L4_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32L431xx)
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#include "stm32l431xx.h"
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#elif defined(STM32L432xx)
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#include "stm32l432xx.h"
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#elif defined(STM32L433xx)
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#include "stm32l433xx.h"
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#elif defined(STM32L442xx)
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#include "stm32l442xx.h"
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#elif defined(STM32L443xx)
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#include "stm32l443xx.h"
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#elif defined(STM32L451xx)
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#include "stm32l451xx.h"
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#elif defined(STM32L452xx)
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#include "stm32l452xx.h"
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#elif defined(STM32L462xx)
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#include "stm32l462xx.h"
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#elif defined(STM32L471xx)
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#include "stm32l471xx.h"
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#elif defined(STM32L475xx)
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#include "stm32l475xx.h"
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#elif defined(STM32L476xx)
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#include "stm32l476xx.h"
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#elif defined(STM32L485xx)
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#include "stm32l485xx.h"
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#elif defined(STM32L486xx)
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#include "stm32l486xx.h"
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#elif defined(STM32L496xx)
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#include "stm32l496xx.h"
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#elif defined(STM32L4A6xx)
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#include "stm32l4a6xx.h"
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#elif defined(STM32L4R5xx)
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#include "stm32l4r5xx.h"
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#elif defined(STM32L4R9xx)
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#include "stm32l4r9xx.h"
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#elif defined(STM32L4S5xx)
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#include "stm32l4s5xx.h"
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#elif defined(STM32L4S9xx)
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#include "stm32l4s9xx.h"
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#else
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#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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ERROR = 0,
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SUCCESS = !ERROR
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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/**
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* @}
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*/
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#if defined (USE_HAL_DRIVER)
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#include "stm32l4xx_hal.h"
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#endif /* USE_HAL_DRIVER */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __STM32L4xx_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/TARGET_STM/mbed_rtx.h

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#define OS_CLOCK 80000000
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#endif
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#elif defined(TARGET_STM32L476RG)
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#elif (defined(TARGET_STM32L476RG) || defined(TARGET_STM32L486RG))
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#ifndef INITIAL_SP
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#define INITIAL_SP (0x20018000UL)

targets/targets.json

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"supported_form_factors": ["ARDUINO", "MORPHO"],
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"core": "Cortex-M4F",
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"default_toolchain": "ARM",
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"extra_labels": ["STM", "STM32L4", "STM32L476RG"],
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"extra_labels": ["STM", "STM32L4", "STM32L476RG", "L476_L486"],
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"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
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"inherits": ["Target"],
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"detect_code": ["0765"],
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"release_versions": ["2", "5"],
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"device_name": "stm32l476rg"
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},
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"NUCLEO_L486RG": {
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"supported_form_factors": ["ARDUINO", "MORPHO"],
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"core": "Cortex-M4F",
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"default_toolchain": "ARM",
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"extra_labels": ["STM", "STM32L4", "STM32L486RG", "L476_L486"],
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"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
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"inherits": ["Target"],
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"detect_code": ["0827"],
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"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
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"release_versions": ["2", "5"],
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"device_name": "stm32l486rg"
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},
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"STM32F3XX": {
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"inherits": ["Target"],
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"core": "Cortex-M4",

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