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47 | 47 | #define CG_GEAR_FC_4 (0x00000002UL) /*!< CG fc/4 register value */
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48 | 48 | #define CG_GEAR_FC_8 (0x00000003UL) /*!< CG fc/8 register value */
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49 | 49 | #define CG_GEAR_FC_16 (0x00000004UL) /*!< CG fc/16 register value */
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50 |
| -#define CG_PRCK_FC_1 (0x00000000UL) /*!< CG ƒÓT0 fc register value */ |
51 |
| -#define CG_PRCK_FC_2 (0x00000100UL) /*!< CG ƒÓT0 fc/2 register value */ |
52 |
| -#define CG_PRCK_FC_4 (0x00000200UL) /*!< CG ƒÓT0 fc/4 register value */ |
53 |
| -#define CG_PRCK_FC_8 (0x00000300UL) /*!< CG ƒÓT0 fc/8 register value */ |
54 |
| -#define CG_PRCK_FC_16 (0x00000400UL) /*!< CG ƒÓT0 fc/16 register value */ |
55 |
| -#define CG_PRCK_FC_32 (0x00000500UL) /*!< CG ƒÓT0 fc/32 register value */ |
56 |
| -#define CG_PRCK_FC_64 (0x00000600UL) /*!< CG ƒÓT0 fc/64 register value */ |
57 |
| -#define CG_PRCK_FC_128 (0x00000700UL) /*!< CG ƒÓT0 fc/128 register value */ |
58 |
| -#define CG_PRCK_FC_256 (0x00000800UL) /*!< CG ƒÓT0 fc/256 register value */ |
59 |
| -#define CG_PRCK_FC_512 (0x00000900UL) /*!< CG ƒÓT0 fc/512 register value */ |
60 |
| - |
61 |
| -#define CG_MCKSEL_1 (0x00000000UL) /*!< CG fsysm, mƒÓT0 fc value */ |
62 |
| -#define CG_MCKSEL_2 (0x00000040UL) /*!< CG fsysm, mƒÓT0 fc/2 value */ |
63 |
| -#define CG_MCKSEL_4 (0x00000080UL) /*!< CG fsysm, mƒÓT0 fc/4 value */ |
| 50 | +#define CG_PRCK_FC_1 (0x00000000UL) /*!< CG PhiT0 fc register value */ |
| 51 | +#define CG_PRCK_FC_2 (0x00000100UL) /*!< CG PhiT0 fc/2 register value */ |
| 52 | +#define CG_PRCK_FC_4 (0x00000200UL) /*!< CG PhiT0 fc/4 register value */ |
| 53 | +#define CG_PRCK_FC_8 (0x00000300UL) /*!< CG PhiT0 fc/8 register value */ |
| 54 | +#define CG_PRCK_FC_16 (0x00000400UL) /*!< CG PhiT0 fc/16 register value */ |
| 55 | +#define CG_PRCK_FC_32 (0x00000500UL) /*!< CG PhiT0 fc/32 register value */ |
| 56 | +#define CG_PRCK_FC_64 (0x00000600UL) /*!< CG PhiT0 fc/64 register value */ |
| 57 | +#define CG_PRCK_FC_128 (0x00000700UL) /*!< CG PhiT0 fc/128 register value*/ |
| 58 | +#define CG_PRCK_FC_256 (0x00000800UL) /*!< CG PhiT0 fc/256 register value*/ |
| 59 | +#define CG_PRCK_FC_512 (0x00000900UL) /*!< CG PhiT0 fc/512 register value*/ |
| 60 | + |
| 61 | +#define CG_MCKSEL_1 (0x00000000UL) /*!< CG fsysm, mPhiT0 fc value */ |
| 62 | +#define CG_MCKSEL_2 (0x00000040UL) /*!< CG fsysm, mPhiT0 fc/2 value */ |
| 63 | +#define CG_MCKSEL_4 (0x00000080UL) /*!< CG fsysm, mPhiT0 fc/4 value */ |
64 | 64 |
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65 | 65 | #define CG_GEAR_MASK ((uint32_t)0x00000007) /*!< CG GEAR mask */
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66 | 66 | #define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */
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