@@ -268,6 +268,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
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};
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static const struct arm64_ftr_bits ftr_id_aa64isar3 [] = {
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+ ARM64_FTR_BITS (FTR_VISIBLE , FTR_NONSTRICT , FTR_LOWER_SAFE , ID_AA64ISAR3_EL1_FPRCVT_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_NONSTRICT , FTR_LOWER_SAFE , ID_AA64ISAR3_EL1_FAMINMAX_SHIFT , 4 , 0 ),
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ARM64_FTR_END ,
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};
@@ -317,6 +318,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_F64MM_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_F32MM_SHIFT , 4 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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+ FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_F16MM_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_I8MM_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
@@ -329,6 +332,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_BF16_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_BitPerm_SHIFT , 4 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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+ FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_EltPerm_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
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FTR_STRICT , FTR_LOWER_SAFE , ID_AA64ZFR0_EL1_AES_SHIFT , 4 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SVE ),
@@ -373,6 +378,16 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
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FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_SF8DP4_SHIFT , 1 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_SF8DP2_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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+ FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_SBitPerm_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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+ FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_AES_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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+ FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_SFEXPA_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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+ FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_STMOP_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE_IF_IS_ENABLED (CONFIG_ARM64_SME ),
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+ FTR_STRICT , FTR_EXACT , ID_AA64SMFR0_EL1_SMOP4_SHIFT , 1 , 0 ),
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ARM64_FTR_END ,
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};
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@@ -381,6 +396,8 @@ static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = {
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8FMA_SHIFT , 1 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8DP4_SHIFT , 1 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8DP2_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8MM8_SHIFT , 1 , 0 ),
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+ ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8MM4_SHIFT , 1 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8E4M3_SHIFT , 1 , 0 ),
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ARM64_FTR_BITS (FTR_VISIBLE , FTR_STRICT , FTR_EXACT , ID_AA64FPFR0_EL1_F8E5M2_SHIFT , 1 , 0 ),
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ARM64_FTR_END ,
@@ -3092,19 +3109,24 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP (ID_AA64MMFR2_EL1 , AT , IMP , CAP_HWCAP , KERNEL_HWCAP_USCAT ),
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#ifdef CONFIG_ARM64_SVE
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HWCAP_CAP (ID_AA64PFR0_EL1 , SVE , IMP , CAP_HWCAP , KERNEL_HWCAP_SVE ),
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+ HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , SVEver , SVE2p2 , CAP_HWCAP , KERNEL_HWCAP_SVE2P2 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , SVEver , SVE2p1 , CAP_HWCAP , KERNEL_HWCAP_SVE2P1 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , SVEver , SVE2 , CAP_HWCAP , KERNEL_HWCAP_SVE2 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , AES , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEAES ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , AES , PMULL128 , CAP_HWCAP , KERNEL_HWCAP_SVEPMULL ),
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+ HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , AES , AES2 , CAP_HWCAP , KERNEL_HWCAP_SVE_AES2 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , BitPerm , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEBITPERM ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , B16B16 , IMP , CAP_HWCAP , KERNEL_HWCAP_SVE_B16B16 ),
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+ HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , B16B16 , BFSCALE , CAP_HWCAP , KERNEL_HWCAP_SVE_BFSCALE ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , BF16 , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEBF16 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , BF16 , EBF16 , CAP_HWCAP , KERNEL_HWCAP_SVE_EBF16 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , SHA3 , IMP , CAP_HWCAP , KERNEL_HWCAP_SVESHA3 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , SM4 , IMP , CAP_HWCAP , KERNEL_HWCAP_SVESM4 ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , I8MM , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEI8MM ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , F32MM , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEF32MM ),
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HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , F64MM , IMP , CAP_HWCAP , KERNEL_HWCAP_SVEF64MM ),
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+ HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , F16MM , IMP , CAP_HWCAP , KERNEL_HWCAP_SVE_F16MM ),
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+ HWCAP_CAP_MATCH_ID (has_sve_feature , ID_AA64ZFR0_EL1 , EltPerm , IMP , CAP_HWCAP , KERNEL_HWCAP_SVE_ELTPERM ),
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#endif
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#ifdef CONFIG_ARM64_GCS
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HWCAP_CAP (ID_AA64PFR1_EL1 , GCS , IMP , CAP_HWCAP , KERNEL_HWCAP_GCS ),
@@ -3124,6 +3146,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP (ID_AA64MMFR0_EL1 , ECV , IMP , CAP_HWCAP , KERNEL_HWCAP_ECV ),
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HWCAP_CAP (ID_AA64MMFR1_EL1 , AFP , IMP , CAP_HWCAP , KERNEL_HWCAP_AFP ),
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HWCAP_CAP (ID_AA64ISAR2_EL1 , CSSC , IMP , CAP_HWCAP , KERNEL_HWCAP_CSSC ),
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+ HWCAP_CAP (ID_AA64ISAR2_EL1 , CSSC , CMPBR , CAP_HWCAP , KERNEL_HWCAP_CMPBR ),
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HWCAP_CAP (ID_AA64ISAR2_EL1 , RPRFM , IMP , CAP_HWCAP , KERNEL_HWCAP_RPRFM ),
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HWCAP_CAP (ID_AA64ISAR2_EL1 , RPRES , IMP , CAP_HWCAP , KERNEL_HWCAP_RPRES ),
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HWCAP_CAP (ID_AA64ISAR2_EL1 , WFxT , IMP , CAP_HWCAP , KERNEL_HWCAP_WFXT ),
@@ -3133,6 +3156,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP (ID_AA64PFR1_EL1 , SME , IMP , CAP_HWCAP , KERNEL_HWCAP_SME ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , FA64 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_FA64 ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , LUTv2 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_LUTV2 ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SMEver , SME2p2 , CAP_HWCAP , KERNEL_HWCAP_SME2P2 ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , SMEver , SME2p1 , CAP_HWCAP , KERNEL_HWCAP_SME2P1 ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , SMEver , SME2 , CAP_HWCAP , KERNEL_HWCAP_SME2 ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , I16I64 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_I16I64 ),
@@ -3150,6 +3174,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP (ID_AA64SMFR0_EL1 , SF8FMA , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SF8FMA ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , SF8DP4 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SF8DP4 ),
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HWCAP_CAP (ID_AA64SMFR0_EL1 , SF8DP2 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SF8DP2 ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SF8MM8 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SF8MM8 ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SF8MM4 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SF8MM4 ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SBitPerm , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SBITPERM ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , AES , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_AES ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SFEXPA , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SFEXPA ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , STMOP , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_STMOP ),
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+ HWCAP_CAP (ID_AA64SMFR0_EL1 , SMOP4 , IMP , CAP_HWCAP , KERNEL_HWCAP_SME_SMOP4 ),
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#endif /* CONFIG_ARM64_SME */
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HWCAP_CAP (ID_AA64FPFR0_EL1 , F8CVT , IMP , CAP_HWCAP , KERNEL_HWCAP_F8CVT ),
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HWCAP_CAP (ID_AA64FPFR0_EL1 , F8FMA , IMP , CAP_HWCAP , KERNEL_HWCAP_F8FMA ),
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