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torvaldstorvalds
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Merge tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Just regular drm fixes, amdgpu, xe and i915 mostly, but a few scattered fixes. I think one of the i915 fixes fixes some build combos that Guenter was seeing. amdgpu: - Add new tiling flag for DCC write compress disable - Add BO metadata flag for DCC - Fix potential out of bounds access in display - Seamless boot fix - CONFIG_FRAME_WARN fix - PSR1 fix xe: - OA uAPI related fixes - Fix SRIOV migration initialization - Restore devcoredump to a sane state i915: - Fix the build error with clamp after WARN_ON on gcc 13.x+ - HDCP related fixes - PMU fix zero delta busyness issue - Fix page cleanup on DMA remap failure - Drop 64bpp YUV formats from ICL+ SDR planes - GuC log related fix - DisplayPort related fixes ivpu: - Fix error handling komeda: - add return check zynqmp: - fix locking in DP code ast: - fix AST DP timeout cec: - fix broken CEC adapter check" * tag 'drm-fixes-2025-02-08' of https://gitlab.freedesktop.org/drm/kernel: (29 commits) drm/i915/dp: Fix potential infinite loop in 128b/132b SST Revert "drm/amd/display: Use HW lock mgr for PSR1" drm/amd/display: Respect user's CONFIG_FRAME_WARN more for dml files accel/amdxdna: Add MODULE_FIRMWARE() declarations drm/i915/dp: Iterate DSC BPP from high to low on all platforms drm/xe: Fix and re-enable xe_print_blob_ascii85() drm/xe/devcoredump: Move exec queue snapshot to Contexts section drm/xe/oa: Set stream->pollin in xe_oa_buffer_check_unlocked drm/xe/pf: Fix migration initialization drm/xe/oa: Preserve oa_ctrl unused bits drm/amd/display: Fix seamless boot sequence drm/amd/display: Fix out-of-bound accesses drm/amdgpu: add a BO metadata flag to disable write compression for Vulkan drm/i915/backlight: Return immediately when scale() finds invalid parameters drm/i915/dp: Return min bpc supported by source instead of 0 drm/i915/dp: fix the Adaptive sync Operation mode for SDP drm/i915/guc: Debug print LRC state entries only if the context is pinned drm/i915: Drop 64bpp YUV formats from ICL+ SDR planes drm/i915: Fix page cleanup on DMA remap failure drm/i915/pmu: Fix zero delta busyness issue ...
2 parents 8aa0f49 + 4f6993b commit 7ee983c

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41 files changed

+249
-148
lines changed

‎drivers/accel/amdxdna/amdxdna_pci_drv.c

+5
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,11 @@
2121

2222
#define AMDXDNA_AUTOSUSPEND_DELAY 5000 /* milliseconds */
2323

24+
MODULE_FIRMWARE("amdnpu/1502_00/npu.sbin");
25+
MODULE_FIRMWARE("amdnpu/17f0_10/npu.sbin");
26+
MODULE_FIRMWARE("amdnpu/17f0_11/npu.sbin");
27+
MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin");
28+
2429
/*
2530
* Bind the driver base on (vendor_id, device_id) pair and later use the
2631
* (device_id, rev_id) pair as a key to select the devices. The devices with

‎drivers/accel/ivpu/ivpu_drv.c

+6-2
Original file line numberDiff line numberDiff line change
@@ -397,15 +397,19 @@ int ivpu_boot(struct ivpu_device *vdev)
397397
if (ivpu_fw_is_cold_boot(vdev)) {
398398
ret = ivpu_pm_dct_init(vdev);
399399
if (ret)
400-
goto err_diagnose_failure;
400+
goto err_disable_ipc;
401401

402402
ret = ivpu_hw_sched_init(vdev);
403403
if (ret)
404-
goto err_diagnose_failure;
404+
goto err_disable_ipc;
405405
}
406406

407407
return 0;
408408

409+
err_disable_ipc:
410+
ivpu_ipc_disable(vdev);
411+
ivpu_hw_irq_disable(vdev);
412+
disable_irq(vdev->irq);
409413
err_diagnose_failure:
410414
ivpu_hw_diagnose_failure(vdev);
411415
ivpu_mmu_evtq_dump(vdev);

‎drivers/accel/ivpu/ivpu_pm.c

+47-37
Original file line numberDiff line numberDiff line change
@@ -115,41 +115,57 @@ static int ivpu_resume(struct ivpu_device *vdev)
115115
return ret;
116116
}
117117

118-
static void ivpu_pm_recovery_work(struct work_struct *work)
118+
static void ivpu_pm_reset_begin(struct ivpu_device *vdev)
119119
{
120-
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
121-
struct ivpu_device *vdev = pm->vdev;
122-
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
123-
int ret;
124-
125-
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
126-
127-
ret = pm_runtime_resume_and_get(vdev->drm.dev);
128-
if (ret)
129-
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
130-
131-
ivpu_jsm_state_dump(vdev);
132-
ivpu_dev_coredump(vdev);
120+
pm_runtime_disable(vdev->drm.dev);
133121

134122
atomic_inc(&vdev->pm->reset_counter);
135123
atomic_set(&vdev->pm->reset_pending, 1);
136124
down_write(&vdev->pm->reset_lock);
125+
}
126+
127+
static void ivpu_pm_reset_complete(struct ivpu_device *vdev)
128+
{
129+
int ret;
137130

138-
ivpu_suspend(vdev);
139131
ivpu_pm_prepare_cold_boot(vdev);
140132
ivpu_jobs_abort_all(vdev);
141133
ivpu_ms_cleanup_all(vdev);
142134

143135
ret = ivpu_resume(vdev);
144-
if (ret)
136+
if (ret) {
145137
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
138+
pm_runtime_set_suspended(vdev->drm.dev);
139+
} else {
140+
pm_runtime_set_active(vdev->drm.dev);
141+
}
146142

147143
up_write(&vdev->pm->reset_lock);
148144
atomic_set(&vdev->pm->reset_pending, 0);
149145

150-
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
151146
pm_runtime_mark_last_busy(vdev->drm.dev);
152-
pm_runtime_put_autosuspend(vdev->drm.dev);
147+
pm_runtime_enable(vdev->drm.dev);
148+
}
149+
150+
static void ivpu_pm_recovery_work(struct work_struct *work)
151+
{
152+
struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
153+
struct ivpu_device *vdev = pm->vdev;
154+
char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
155+
156+
ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
157+
158+
ivpu_pm_reset_begin(vdev);
159+
160+
if (!pm_runtime_status_suspended(vdev->drm.dev)) {
161+
ivpu_jsm_state_dump(vdev);
162+
ivpu_dev_coredump(vdev);
163+
ivpu_suspend(vdev);
164+
}
165+
166+
ivpu_pm_reset_complete(vdev);
167+
168+
kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
153169
}
154170

155171
void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
@@ -309,7 +325,10 @@ int ivpu_rpm_get(struct ivpu_device *vdev)
309325
int ret;
310326

311327
ret = pm_runtime_resume_and_get(vdev->drm.dev);
312-
drm_WARN_ON(&vdev->drm, ret < 0);
328+
if (ret < 0) {
329+
ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
330+
pm_runtime_set_suspended(vdev->drm.dev);
331+
}
313332

314333
return ret;
315334
}
@@ -325,35 +344,26 @@ void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev)
325344
struct ivpu_device *vdev = pci_get_drvdata(pdev);
326345

327346
ivpu_dbg(vdev, PM, "Pre-reset..\n");
328-
atomic_inc(&vdev->pm->reset_counter);
329-
atomic_set(&vdev->pm->reset_pending, 1);
330347

331-
pm_runtime_get_sync(vdev->drm.dev);
332-
down_write(&vdev->pm->reset_lock);
333-
ivpu_prepare_for_reset(vdev);
334-
ivpu_hw_reset(vdev);
335-
ivpu_pm_prepare_cold_boot(vdev);
336-
ivpu_jobs_abort_all(vdev);
337-
ivpu_ms_cleanup_all(vdev);
348+
ivpu_pm_reset_begin(vdev);
349+
350+
if (!pm_runtime_status_suspended(vdev->drm.dev)) {
351+
ivpu_prepare_for_reset(vdev);
352+
ivpu_hw_reset(vdev);
353+
}
338354

339355
ivpu_dbg(vdev, PM, "Pre-reset done.\n");
340356
}
341357

342358
void ivpu_pm_reset_done_cb(struct pci_dev *pdev)
343359
{
344360
struct ivpu_device *vdev = pci_get_drvdata(pdev);
345-
int ret;
346361

347362
ivpu_dbg(vdev, PM, "Post-reset..\n");
348-
ret = ivpu_resume(vdev);
349-
if (ret)
350-
ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
351-
up_write(&vdev->pm->reset_lock);
352-
atomic_set(&vdev->pm->reset_pending, 0);
353-
ivpu_dbg(vdev, PM, "Post-reset done.\n");
354363

355-
pm_runtime_mark_last_busy(vdev->drm.dev);
356-
pm_runtime_put_autosuspend(vdev->drm.dev);
364+
ivpu_pm_reset_complete(vdev);
365+
366+
ivpu_dbg(vdev, PM, "Post-reset done.\n");
357367
}
358368

359369
void ivpu_pm_init(struct ivpu_device *vdev)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -119,9 +119,10 @@
119119
* - 3.57.0 - Compute tunneling on GFX10+
120120
* - 3.58.0 - Add GFX12 DCC support
121121
* - 3.59.0 - Cleared VRAM
122+
* - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
122123
*/
123124
#define KMS_DRIVER_MAJOR 3
124-
#define KMS_DRIVER_MINOR 59
125+
#define KMS_DRIVER_MINOR 60
125126
#define KMS_DRIVER_PATCHLEVEL 0
126127

127128
/*

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+6-2
Original file line numberDiff line numberDiff line change
@@ -309,7 +309,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
309309
mutex_lock(&adev->mman.gtt_window_lock);
310310
while (src_mm.remaining) {
311311
uint64_t from, to, cur_size, tiling_flags;
312-
uint32_t num_type, data_format, max_com;
312+
uint32_t num_type, data_format, max_com, write_compress_disable;
313313
struct dma_fence *next;
314314

315315
/* Never copy more than 256MiB at once to avoid a timeout */
@@ -340,9 +340,13 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
340340
max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
341341
num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
342342
data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
343+
write_compress_disable =
344+
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
343345
copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |
344346
AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |
345-
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format));
347+
AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |
348+
AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,
349+
write_compress_disable));
346350
}
347351

348352
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+2
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@ struct amdgpu_copy_mem {
119119
#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
120120
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
121121
#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
122+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
123+
#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
122124

123125
#define AMDGPU_COPY_FLAGS_SET(field, value) \
124126
(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)

‎drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

+3-2
Original file line numberDiff line numberDiff line change
@@ -1741,11 +1741,12 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
17411741
uint32_t byte_count,
17421742
uint32_t copy_flags)
17431743
{
1744-
uint32_t num_type, data_format, max_com;
1744+
uint32_t num_type, data_format, max_com, write_cm;
17451745

17461746
max_com = AMDGPU_COPY_FLAGS_GET(copy_flags, MAX_COMPRESSED);
17471747
data_format = AMDGPU_COPY_FLAGS_GET(copy_flags, DATA_FORMAT);
17481748
num_type = AMDGPU_COPY_FLAGS_GET(copy_flags, NUMBER_TYPE);
1749+
write_cm = AMDGPU_COPY_FLAGS_GET(copy_flags, WRITE_COMPRESS_DISABLE) ? 2 : 1;
17491750

17501751
ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
17511752
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
@@ -1762,7 +1763,7 @@ static void sdma_v7_0_emit_copy_buffer(struct amdgpu_ib *ib,
17621763
if ((copy_flags & (AMDGPU_COPY_FLAGS_READ_DECOMPRESSED | AMDGPU_COPY_FLAGS_WRITE_COMPRESSED)))
17631764
ib->ptr[ib->length_dw++] = SDMA_DCC_DATA_FORMAT(data_format) | SDMA_DCC_NUM_TYPE(num_type) |
17641765
((copy_flags & AMDGPU_COPY_FLAGS_READ_DECOMPRESSED) ? SDMA_DCC_READ_CM(2) : 0) |
1765-
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(1) : 0) |
1766+
((copy_flags & AMDGPU_COPY_FLAGS_WRITE_COMPRESSED) ? SDMA_DCC_WRITE_CM(write_cm) : 0) |
17661767
SDMA_DCC_MAX_COM(max_com) | SDMA_DCC_MAX_UCOM(1);
17671768
else
17681769
ib->ptr[ib->length_dw++] = 0;

‎drivers/gpu/drm/amd/display/dc/core/dc.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -2133,7 +2133,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
21332133

21342134
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
21352135

2136-
if (context->stream_count > get_seamless_boot_stream_count(context) ||
2136+
if (get_seamless_boot_stream_count(context) == 0 ||
21372137
context->stream_count == 0) {
21382138
/* Must wait for no flips to be pending before doing optimize bw */
21392139
hwss_wait_for_no_pipes_pending(dc, context);

‎drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

+1-2
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,7 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
6363

6464
bool should_use_dmub_lock(struct dc_link *link)
6565
{
66-
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
67-
link->psr_settings.psr_version == DC_PSR_VERSION_1)
66+
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
6867
return true;
6968

7069
if (link->replay_settings.replay_feature_enabled)

‎drivers/gpu/drm/amd/display/dc/dml/Makefile

+9-5
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,15 @@ dml_ccflags := $(CC_FLAGS_FPU)
2929
dml_rcflags := $(CC_FLAGS_NO_FPU)
3030

3131
ifneq ($(CONFIG_FRAME_WARN),0)
32-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33-
frame_warn_flag := -Wframe-larger-than=3072
34-
else
35-
frame_warn_flag := -Wframe-larger-than=2048
36-
endif
32+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
33+
frame_warn_limit := 3072
34+
else
35+
frame_warn_limit := 2048
36+
endif
37+
38+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
39+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
40+
endif
3741
endif
3842

3943
CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)

‎drivers/gpu/drm/amd/display/dc/dml2/Makefile

+13-9
Original file line numberDiff line numberDiff line change
@@ -28,15 +28,19 @@ dml2_ccflags := $(CC_FLAGS_FPU)
2828
dml2_rcflags := $(CC_FLAGS_NO_FPU)
2929

3030
ifneq ($(CONFIG_FRAME_WARN),0)
31-
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32-
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33-
frame_warn_flag := -Wframe-larger-than=4096
34-
else
35-
frame_warn_flag := -Wframe-larger-than=3072
36-
endif
37-
else
38-
frame_warn_flag := -Wframe-larger-than=2048
39-
endif
31+
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
32+
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
33+
frame_warn_limit := 4096
34+
else
35+
frame_warn_limit := 3072
36+
endif
37+
else
38+
frame_warn_limit := 2048
39+
endif
40+
41+
ifeq ($(call test-lt, $(CONFIG_FRAME_WARN), $(frame_warn_limit)),y)
42+
frame_warn_flag := -Wframe-larger-than=$(frame_warn_limit)
43+
endif
4044
endif
4145

4246
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -1017,7 +1017,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
10171017
if (disp_cfg_stream_location < 0)
10181018
disp_cfg_stream_location = dml_dispcfg->num_streams++;
10191019

1020-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1020+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
10211021
populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);
10221022
adjust_dml21_hblank_timing_config_from_pipe_ctx(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);
10231023
populate_dml21_output_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]);
@@ -1042,7 +1042,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
10421042
if (disp_cfg_plane_location < 0)
10431043
disp_cfg_plane_location = dml_dispcfg->num_planes++;
10441044

1045-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1045+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
10461046

10471047
populate_dml21_surface_config_from_plane_state(in_dc, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location].surface, context->stream_status[stream_index].plane_states[plane_index]);
10481048
populate_dml21_plane_config_from_plane_state(dml_ctx, &dml_dispcfg->plane_descriptors[disp_cfg_plane_location], context->stream_status[stream_index].plane_states[plane_index], context, stream_index);

‎drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,7 @@ static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *
786786
case SIGNAL_TYPE_DISPLAY_PORT_MST:
787787
case SIGNAL_TYPE_DISPLAY_PORT:
788788
out->OutputEncoder[location] = dml_dp;
789-
if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
789+
if (location < MAX_HPO_DP2_ENCODERS && dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
790790
out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
791791
break;
792792
case SIGNAL_TYPE_EDP:
@@ -1343,7 +1343,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
13431343
if (disp_cfg_stream_location < 0)
13441344
disp_cfg_stream_location = dml_dispcfg->num_timings++;
13451345

1346-
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1346+
ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
13471347

13481348
populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
13491349
populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
@@ -1383,7 +1383,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat
13831383
if (disp_cfg_plane_location < 0)
13841384
disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
13851385

1386-
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1386+
ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location < __DML2_WRAPPER_MAX_STREAMS_PLANES__);
13871387

13881388
populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
13891389
populate_dml_plane_cfg_from_plane_state(

‎drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,8 @@ bool hubbub3_program_watermarks(
129129
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
130130
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);
131131

132-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
132+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
133+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
133134

134135
return wm_pending;
135136
}

‎drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -750,7 +750,8 @@ static bool hubbub31_program_watermarks(
750750
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
751751
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
752752

753-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
753+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
754+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
754755
return wm_pending;
755756
}
756757

‎drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -786,7 +786,8 @@ static bool hubbub32_program_watermarks(
786786
REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
787787
DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
788788

789-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
789+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
790+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
790791

791792
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
792793

‎drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c

+2-1
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,8 @@ static bool hubbub35_program_watermarks(
326326
DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/
327327
REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);
328328

329-
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
329+
if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
330+
hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
330331

331332
hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
332333

‎drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

+2
Original file line numberDiff line numberDiff line change
@@ -500,6 +500,8 @@ void hubp3_init(struct hubp *hubp)
500500
//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
501501
REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
502502

503+
REG_UPDATE(DCHUBP_CNTL, HUBP_TTU_DISABLE, 0);
504+
503505
hubp_reset(hubp);
504506
}
505507

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