@@ -384,7 +384,7 @@ Nucleo_64.menu.pnum.NUCLEO_L053R8.build.mcu=cortex-m0plus
384
384
Nucleo_64.menu.pnum.NUCLEO_L053R8.build.board=NUCLEO_L053R8
385
385
Nucleo_64.menu.pnum.NUCLEO_L053R8.build.series=STM32L0xx
386
386
Nucleo_64.menu.pnum.NUCLEO_L053R8.build.product_line=STM32L053xx
387
- Nucleo_64.menu.pnum.NUCLEO_L053R8.build.variant=STM32L0xx/NUCLEO_L053R8
387
+ Nucleo_64.menu.pnum.NUCLEO_L053R8.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
388
388
Nucleo_64.menu.pnum.NUCLEO_L053R8.build.cmsis_lib_gcc=arm_cortexM0l_math
389
389
Nucleo_64.menu.pnum.NUCLEO_L053R8.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
390
390
@@ -397,7 +397,7 @@ Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.mcu=cortex-m0plus
397
397
Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.board=NUCLEO_L073RZ
398
398
Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.series=STM32L0xx
399
399
Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.product_line=STM32L073xx
400
- Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.variant=STM32L0xx/NUCLEO_L073RZ
400
+ Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
401
401
Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.cmsis_lib_gcc=arm_cortexM0l_math
402
402
Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
403
403
@@ -568,7 +568,7 @@ Nucleo_32.menu.pnum.NUCLEO_L031K6.build.mcu=cortex-m0plus
568
568
Nucleo_32.menu.pnum.NUCLEO_L031K6.build.board=NUCLEO_L031K6
569
569
Nucleo_32.menu.pnum.NUCLEO_L031K6.build.series=STM32L0xx
570
570
Nucleo_32.menu.pnum.NUCLEO_L031K6.build.product_line=STM32L031xx
571
- Nucleo_32.menu.pnum.NUCLEO_L031K6.build.variant=STM32L0xx/NUCLEO_L031K6
571
+ Nucleo_32.menu.pnum.NUCLEO_L031K6.build.variant=STM32L0xx/L031K(4-6)Tx_L041K6Tx
572
572
Nucleo_32.menu.pnum.NUCLEO_L031K6.build.cmsis_lib_gcc=arm_cortexM0l_math
573
573
574
574
# NUCLEO_L412KB board
@@ -752,7 +752,8 @@ Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.mcu=cortex-m0plus
752
752
Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.board=DISCO_L072CZ_LRWAN1
753
753
Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.series=STM32L0xx
754
754
Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.product_line=STM32L072xx
755
- Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.variant=STM32L0xx/DISCO_L072CZ_LRWAN1
755
+ Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
756
+ Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
756
757
Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.cmsis_lib_gcc=arm_cortexM0l_math
757
758
Disco.menu.pnum.DISCO_L072CZ_LRWAN1.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
758
759
@@ -2890,7 +2891,8 @@ GenL0.menu.pnum.THUNDERPACK_L072.upload.maximum_data_size=20480
2890
2891
GenL0.menu.pnum.THUNDERPACK_L072.build.board=THUNDERPACK_L072
2891
2892
GenL0.menu.pnum.THUNDERPACK_L072.build.product_line=STM32L072xx
2892
2893
GenL0.menu.pnum.THUNDERPACK_L072.build.variant_h=variant_{build.board}.h
2893
- GenL0.menu.pnum.THUNDERPACK_L072.build.variant=STM32L0xx/THUNDERPACK_L072
2894
+ GenL0.menu.pnum.THUNDERPACK_L072..build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
2895
+ GenL0.menu.pnum.THUNDERPACK_L072.build.variant=STM32L0xx/L072K(B-Z)Tx_L082K(B-Z)Tx
2894
2896
2895
2897
# Piconomix PX-HER0 board
2896
2898
GenL0.menu.pnum.PX_HER0=PX-HER0
@@ -2899,7 +2901,224 @@ GenL0.menu.pnum.PX_HER0.upload.maximum_data_size=20480
2899
2901
GenL0.menu.pnum.PX_HER0.build.board=PX_HER0
2900
2902
GenL0.menu.pnum.PX_HER0.build.product_line=STM32L072xx
2901
2903
GenL0.menu.pnum.PX_HER0.build.variant_h=variant_{build.board}.h
2902
- GenL0.menu.pnum.PX_HER0.build.variant=STM32L0xx/PX_HER0
2904
+ GenL0.menu.pnum.PX_HER0.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
2905
+ GenL0.menu.pnum.PX_HER0.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
2906
+
2907
+ # Generic L031K4Tx
2908
+ GenL0.menu.pnum.GENERIC_L031K4TX=Generic L031K4Tx
2909
+ GenL0.menu.pnum.GENERIC_L031K4TX.upload.maximum_size=16384
2910
+ GenL0.menu.pnum.GENERIC_L031K4TX.upload.maximum_data_size=8192
2911
+ GenL0.menu.pnum.GENERIC_L031K4TX.build.board=GENERIC_L031K4TX
2912
+ GenL0.menu.pnum.GENERIC_L031K4TX.build.product_line=STM32L031xx
2913
+ GenL0.menu.pnum.GENERIC_L031K4TX.build.variant=STM32L0xx/L031K(4-6)Tx_L041K6Tx
2914
+
2915
+ # Generic L031K6Tx
2916
+ GenL0.menu.pnum.GENERIC_L031K6TX=Generic L031K6Tx
2917
+ GenL0.menu.pnum.GENERIC_L031K6TX.upload.maximum_size=32768
2918
+ GenL0.menu.pnum.GENERIC_L031K6TX.upload.maximum_data_size=8192
2919
+ GenL0.menu.pnum.GENERIC_L031K6TX.build.board=GENERIC_L031K6TX
2920
+ GenL0.menu.pnum.GENERIC_L031K6TX.build.product_line=STM32L031xx
2921
+ GenL0.menu.pnum.GENERIC_L031K6TX.build.variant=STM32L0xx/L031K(4-6)Tx_L041K6Tx
2922
+
2923
+ # Generic L041K6Tx
2924
+ GenL0.menu.pnum.GENERIC_L041K6TX=Generic L041K6Tx
2925
+ GenL0.menu.pnum.GENERIC_L041K6TX.upload.maximum_size=32768
2926
+ GenL0.menu.pnum.GENERIC_L041K6TX.upload.maximum_data_size=8192
2927
+ GenL0.menu.pnum.GENERIC_L041K6TX.build.board=GENERIC_L041K6TX
2928
+ GenL0.menu.pnum.GENERIC_L041K6TX.build.product_line=STM32L041xx
2929
+ GenL0.menu.pnum.GENERIC_L041K6TX.build.variant=STM32L0xx/L031K(4-6)Tx_L041K6Tx
2930
+
2931
+ # Generic L051C6Tx
2932
+ GenL0.menu.pnum.GENERIC_L051C6TX=Generic L051C6Tx
2933
+ GenL0.menu.pnum.GENERIC_L051C6TX.upload.maximum_size=32768
2934
+ GenL0.menu.pnum.GENERIC_L051C6TX.upload.maximum_data_size=8192
2935
+ GenL0.menu.pnum.GENERIC_L051C6TX.build.board=GENERIC_L051C6TX
2936
+ GenL0.menu.pnum.GENERIC_L051C6TX.build.product_line=STM32L051xx
2937
+ GenL0.menu.pnum.GENERIC_L051C6TX.build.variant=STM32L0xx/L051C(6-8)
2938
+
2939
+ # Generic L051C6Ux
2940
+ GenL0.menu.pnum.GENERIC_L051C6UX=Generic L051C6Ux
2941
+ GenL0.menu.pnum.GENERIC_L051C6UX.upload.maximum_size=32768
2942
+ GenL0.menu.pnum.GENERIC_L051C6UX.upload.maximum_data_size=8192
2943
+ GenL0.menu.pnum.GENERIC_L051C6UX.build.board=GENERIC_L051C6UX
2944
+ GenL0.menu.pnum.GENERIC_L051C6UX.build.product_line=STM32L051xx
2945
+ GenL0.menu.pnum.GENERIC_L051C6UX.build.variant=STM32L0xx/L051C(6-8)
2946
+
2947
+ # Generic L051C8Tx
2948
+ GenL0.menu.pnum.GENERIC_L051C8TX=Generic L051C8Tx
2949
+ GenL0.menu.pnum.GENERIC_L051C8TX.upload.maximum_size=65536
2950
+ GenL0.menu.pnum.GENERIC_L051C8TX.upload.maximum_data_size=8192
2951
+ GenL0.menu.pnum.GENERIC_L051C8TX.build.board=GENERIC_L051C8TX
2952
+ GenL0.menu.pnum.GENERIC_L051C8TX.build.product_line=STM32L051xx
2953
+ GenL0.menu.pnum.GENERIC_L051C8TX.build.variant=STM32L0xx/L051C(6-8)
2954
+
2955
+ # Generic L051C8Ux
2956
+ GenL0.menu.pnum.GENERIC_L051C8UX=Generic L051C8Ux
2957
+ GenL0.menu.pnum.GENERIC_L051C8UX.upload.maximum_size=65536
2958
+ GenL0.menu.pnum.GENERIC_L051C8UX.upload.maximum_data_size=8192
2959
+ GenL0.menu.pnum.GENERIC_L051C8UX.build.board=GENERIC_L051C8UX
2960
+ GenL0.menu.pnum.GENERIC_L051C8UX.build.product_line=STM32L051xx
2961
+ GenL0.menu.pnum.GENERIC_L051C8UX.build.variant=STM32L0xx/L051C(6-8)
2962
+
2963
+ # Generic L052R6Tx
2964
+ GenL0.menu.pnum.GENERIC_L052R6TX=Generic L052R6Tx
2965
+ GenL0.menu.pnum.GENERIC_L052R6TX.upload.maximum_size=32768
2966
+ GenL0.menu.pnum.GENERIC_L052R6TX.upload.maximum_data_size=8192
2967
+ GenL0.menu.pnum.GENERIC_L052R6TX.build.board=GENERIC_L052R6TX
2968
+ GenL0.menu.pnum.GENERIC_L052R6TX.build.product_line=STM32L052xx
2969
+ GenL0.menu.pnum.GENERIC_L052R6TX.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
2970
+
2971
+ # Generic L052R8Tx
2972
+ GenL0.menu.pnum.GENERIC_L052R8TX=Generic L052R8Tx
2973
+ GenL0.menu.pnum.GENERIC_L052R8TX.upload.maximum_size=65536
2974
+ GenL0.menu.pnum.GENERIC_L052R8TX.upload.maximum_data_size=8192
2975
+ GenL0.menu.pnum.GENERIC_L052R8TX.build.board=GENERIC_L052R8TX
2976
+ GenL0.menu.pnum.GENERIC_L052R8TX.build.product_line=STM32L052xx
2977
+ GenL0.menu.pnum.GENERIC_L052R8TX.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
2978
+
2979
+ # Generic L053R6Tx
2980
+ GenL0.menu.pnum.GENERIC_L053R6TX=Generic L053R6Tx
2981
+ GenL0.menu.pnum.GENERIC_L053R6TX.upload.maximum_size=32768
2982
+ GenL0.menu.pnum.GENERIC_L053R6TX.upload.maximum_data_size=8192
2983
+ GenL0.menu.pnum.GENERIC_L053R6TX.build.board=GENERIC_L053R6TX
2984
+ GenL0.menu.pnum.GENERIC_L053R6TX.build.product_line=STM32L053xx
2985
+ GenL0.menu.pnum.GENERIC_L053R6TX.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
2986
+
2987
+ # Generic L053R8Tx
2988
+ GenL0.menu.pnum.GENERIC_L053R8TX=Generic L053R8Tx
2989
+ GenL0.menu.pnum.GENERIC_L053R8TX.upload.maximum_size=65536
2990
+ GenL0.menu.pnum.GENERIC_L053R8TX.upload.maximum_data_size=8192
2991
+ GenL0.menu.pnum.GENERIC_L053R8TX.build.board=GENERIC_L053R8TX
2992
+ GenL0.menu.pnum.GENERIC_L053R8TX.build.product_line=STM32L053xx
2993
+ GenL0.menu.pnum.GENERIC_L053R8TX.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
2994
+
2995
+ # Generic L063R8Tx
2996
+ GenL0.menu.pnum.GENERIC_L063R8TX=Generic L063R8Tx
2997
+ GenL0.menu.pnum.GENERIC_L063R8TX.upload.maximum_size=65536
2998
+ GenL0.menu.pnum.GENERIC_L063R8TX.upload.maximum_data_size=8192
2999
+ GenL0.menu.pnum.GENERIC_L063R8TX.build.board=GENERIC_L063R8TX
3000
+ GenL0.menu.pnum.GENERIC_L063R8TX.build.product_line=STM32L063xx
3001
+ GenL0.menu.pnum.GENERIC_L063R8TX.build.variant=STM32L0xx/L052R(6-8)Tx_L053R(6-8)Tx_L063R8Tx
3002
+
3003
+ # Generic L072CBYx
3004
+ GenL0.menu.pnum.GENERIC_L072CBYX=Generic L072CBYx
3005
+ GenL0.menu.pnum.GENERIC_L072CBYX.upload.maximum_size=131072
3006
+ GenL0.menu.pnum.GENERIC_L072CBYX.upload.maximum_data_size=20480
3007
+ GenL0.menu.pnum.GENERIC_L072CBYX.build.board=GENERIC_L072CBYX
3008
+ GenL0.menu.pnum.GENERIC_L072CBYX.build.product_line=STM32L072xx
3009
+ GenL0.menu.pnum.GENERIC_L072CBYX.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
3010
+
3011
+ # Generic L072CZEx
3012
+ GenL0.menu.pnum.GENERIC_L072CZEX=Generic L072CZEx
3013
+ GenL0.menu.pnum.GENERIC_L072CZEX.upload.maximum_size=196608
3014
+ GenL0.menu.pnum.GENERIC_L072CZEX.upload.maximum_data_size=20480
3015
+ GenL0.menu.pnum.GENERIC_L072CZEX.build.board=GENERIC_L072CZEX
3016
+ GenL0.menu.pnum.GENERIC_L072CZEX.build.product_line=STM32L072xx
3017
+ GenL0.menu.pnum.GENERIC_L072CZEX.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
3018
+
3019
+ # Generic L072CZYx
3020
+ GenL0.menu.pnum.GENERIC_L072CZYX=Generic L072CZYx
3021
+ GenL0.menu.pnum.GENERIC_L072CZYX.upload.maximum_size=196608
3022
+ GenL0.menu.pnum.GENERIC_L072CZYX.upload.maximum_data_size=20480
3023
+ GenL0.menu.pnum.GENERIC_L072CZYX.build.board=GENERIC_L072CZYX
3024
+ GenL0.menu.pnum.GENERIC_L072CZYX.build.product_line=STM32L072xx
3025
+ GenL0.menu.pnum.GENERIC_L072CZYX.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
3026
+
3027
+ # Generic L072KBTx
3028
+ GenL0.menu.pnum.GENERIC_L072KBTX=Generic L072KBTx
3029
+ GenL0.menu.pnum.GENERIC_L072KBTX.upload.maximum_size=131072
3030
+ GenL0.menu.pnum.GENERIC_L072KBTX.upload.maximum_data_size=20480
3031
+ GenL0.menu.pnum.GENERIC_L072KBTX.build.board=GENERIC_L072KBTX
3032
+ GenL0.menu.pnum.GENERIC_L072KBTX.build.product_line=STM32L072xx
3033
+ GenL0.menu.pnum.GENERIC_L072KBTX.build.variant=STM32L0xx/L072K(B-Z)Tx_L082K(B-Z)Tx
3034
+
3035
+ # Generic L072KZTx
3036
+ GenL0.menu.pnum.GENERIC_L072KZTX=Generic L072KZTx
3037
+ GenL0.menu.pnum.GENERIC_L072KZTX.upload.maximum_size=196608
3038
+ GenL0.menu.pnum.GENERIC_L072KZTX.upload.maximum_data_size=20480
3039
+ GenL0.menu.pnum.GENERIC_L072KZTX.build.board=GENERIC_L072KZTX
3040
+ GenL0.menu.pnum.GENERIC_L072KZTX.build.product_line=STM32L072xx
3041
+ GenL0.menu.pnum.GENERIC_L072KZTX.build.variant=STM32L0xx/L072K(B-Z)Tx_L082K(B-Z)Tx
3042
+
3043
+ # Generic L072RBTx
3044
+ GenL0.menu.pnum.GENERIC_L072RBTX=Generic L072RBTx
3045
+ GenL0.menu.pnum.GENERIC_L072RBTX.upload.maximum_size=131072
3046
+ GenL0.menu.pnum.GENERIC_L072RBTX.upload.maximum_data_size=20480
3047
+ GenL0.menu.pnum.GENERIC_L072RBTX.build.board=GENERIC_L072RBTX
3048
+ GenL0.menu.pnum.GENERIC_L072RBTX.build.product_line=STM32L072xx
3049
+ GenL0.menu.pnum.GENERIC_L072RBTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
3050
+
3051
+ # Generic L072RZTx
3052
+ GenL0.menu.pnum.GENERIC_L072RZTX=Generic L072RZTx
3053
+ GenL0.menu.pnum.GENERIC_L072RZTX.upload.maximum_size=196608
3054
+ GenL0.menu.pnum.GENERIC_L072RZTX.upload.maximum_data_size=20480
3055
+ GenL0.menu.pnum.GENERIC_L072RZTX.build.board=GENERIC_L072RZTX
3056
+ GenL0.menu.pnum.GENERIC_L072RZTX.build.product_line=STM32L072xx
3057
+ GenL0.menu.pnum.GENERIC_L072RZTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
3058
+
3059
+ # Generic L073CZYx
3060
+ GenL0.menu.pnum.GENERIC_L073CZYX=Generic L073CZYx
3061
+ GenL0.menu.pnum.GENERIC_L073CZYX.upload.maximum_size=196608
3062
+ GenL0.menu.pnum.GENERIC_L073CZYX.upload.maximum_data_size=20480
3063
+ GenL0.menu.pnum.GENERIC_L073CZYX.build.board=GENERIC_L073CZYX
3064
+ GenL0.menu.pnum.GENERIC_L073CZYX.build.product_line=STM32L073xx
3065
+ GenL0.menu.pnum.GENERIC_L073CZYX.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
3066
+
3067
+ # Generic L073RBTx
3068
+ GenL0.menu.pnum.GENERIC_L073RBTX=Generic L073RBTx
3069
+ GenL0.menu.pnum.GENERIC_L073RBTX.upload.maximum_size=131072
3070
+ GenL0.menu.pnum.GENERIC_L073RBTX.upload.maximum_data_size=20480
3071
+ GenL0.menu.pnum.GENERIC_L073RBTX.build.board=GENERIC_L073RBTX
3072
+ GenL0.menu.pnum.GENERIC_L073RBTX.build.product_line=STM32L073xx
3073
+ GenL0.menu.pnum.GENERIC_L073RBTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
3074
+
3075
+ # Generic L073RZTx
3076
+ GenL0.menu.pnum.GENERIC_L073RZTX=Generic L073RZTx
3077
+ GenL0.menu.pnum.GENERIC_L073RZTX.upload.maximum_size=196608
3078
+ GenL0.menu.pnum.GENERIC_L073RZTX.upload.maximum_data_size=20480
3079
+ GenL0.menu.pnum.GENERIC_L073RZTX.build.board=GENERIC_L073RZTX
3080
+ GenL0.menu.pnum.GENERIC_L073RZTX.build.product_line=STM32L073xx
3081
+ GenL0.menu.pnum.GENERIC_L073RZTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
3082
+
3083
+ # Generic L082CZYx
3084
+ GenL0.menu.pnum.GENERIC_L082CZYX=Generic L082CZYx
3085
+ GenL0.menu.pnum.GENERIC_L082CZYX.upload.maximum_size=196608
3086
+ GenL0.menu.pnum.GENERIC_L082CZYX.upload.maximum_data_size=20480
3087
+ GenL0.menu.pnum.GENERIC_L082CZYX.build.board=GENERIC_L082CZYX
3088
+ GenL0.menu.pnum.GENERIC_L082CZYX.build.product_line=STM32L082xx
3089
+ GenL0.menu.pnum.GENERIC_L082CZYX.build.variant=STM32L0xx/L072C(B-Z)Yx_L072CZEx_L073CZYx_L082CZYx
3090
+
3091
+ # Generic L082KBTx
3092
+ GenL0.menu.pnum.GENERIC_L082KBTX=Generic L082KBTx
3093
+ GenL0.menu.pnum.GENERIC_L082KBTX.upload.maximum_size=131072
3094
+ GenL0.menu.pnum.GENERIC_L082KBTX.upload.maximum_data_size=20480
3095
+ GenL0.menu.pnum.GENERIC_L082KBTX.build.board=GENERIC_L082KBTX
3096
+ GenL0.menu.pnum.GENERIC_L082KBTX.build.product_line=STM32L082xx
3097
+ GenL0.menu.pnum.GENERIC_L082KBTX.build.variant=STM32L0xx/L072K(B-Z)Tx_L082K(B-Z)Tx
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+
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+ # Generic L082KZTx
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+ GenL0.menu.pnum.GENERIC_L082KZTX=Generic L082KZTx
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+ GenL0.menu.pnum.GENERIC_L082KZTX.upload.maximum_size=196608
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+ GenL0.menu.pnum.GENERIC_L082KZTX.upload.maximum_data_size=20480
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+ GenL0.menu.pnum.GENERIC_L082KZTX.build.board=GENERIC_L082KZTX
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+ GenL0.menu.pnum.GENERIC_L082KZTX.build.product_line=STM32L082xx
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+ GenL0.menu.pnum.GENERIC_L082KZTX.build.variant=STM32L0xx/L072K(B-Z)Tx_L082K(B-Z)Tx
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+
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+ # Generic L083RBTx
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+ GenL0.menu.pnum.GENERIC_L083RBTX=Generic L083RBTx
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+ GenL0.menu.pnum.GENERIC_L083RBTX.upload.maximum_size=131072
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+ GenL0.menu.pnum.GENERIC_L083RBTX.upload.maximum_data_size=20480
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+ GenL0.menu.pnum.GENERIC_L083RBTX.build.board=GENERIC_L083RBTX
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+ GenL0.menu.pnum.GENERIC_L083RBTX.build.product_line=STM32L083xx
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+ GenL0.menu.pnum.GENERIC_L083RBTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
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+
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+ # Generic L083RZTx
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+ GenL0.menu.pnum.GENERIC_L083RZTX=Generic L083RZTx
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+ GenL0.menu.pnum.GENERIC_L083RZTX.upload.maximum_size=196608
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+ GenL0.menu.pnum.GENERIC_L083RZTX.upload.maximum_data_size=20480
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+ GenL0.menu.pnum.GENERIC_L083RZTX.build.board=GENERIC_L083RZTX
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+ GenL0.menu.pnum.GENERIC_L083RZTX.build.product_line=STM32L083xx
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+ GenL0.menu.pnum.GENERIC_L083RZTX.build.variant=STM32L0xx/L072R(B-Z)Tx_L073R(B-Z)Tx_L083R(B-Z)Tx
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# Upload menu
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GenL0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
@@ -3839,7 +4058,8 @@ LoRa.menu.pnum.RHF76_052.build.mcu=cortex-m0plus
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LoRa.menu.pnum.RHF76_052.build.board=RHF76_052
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LoRa.menu.pnum.RHF76_052.build.series=STM32L0xx
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LoRa.menu.pnum.RHF76_052.build.product_line=STM32L051xx
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- LoRa.menu.pnum.RHF76_052.build.variant=STM32L0xx/RHF76_052
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+ LoRa.menu.pnum.RHF76_052.build.variant=STM32L0xx/L051C(6-8)
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+ LoRa.menu.pnum.RHF76_052.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
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LoRa.menu.pnum.RHF76_052.build.cmsis_lib_gcc=arm_cortexM0l_math
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LoRa.menu.pnum.RHF76_052.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
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